Lines Matching +full:channel +full:- +full:2
12 * the Free Software Foundation, either version 2 of the License, or
47 #define DPDMA_ISR (0x0004 >> 2)
48 #define DPDMA_IMR (0x0008 >> 2)
49 #define DPDMA_IEN (0x000C >> 2)
50 #define DPDMA_IDS (0x0010 >> 2)
51 #define DPDMA_EISR (0x0014 >> 2)
52 #define DPDMA_EIMR (0x0018 >> 2)
53 #define DPDMA_EIEN (0x001C >> 2)
54 #define DPDMA_EIDS (0x0020 >> 2)
55 #define DPDMA_CNTL (0x0100 >> 2)
57 #define DPDMA_GBL (0x0104 >> 2)
61 #define DPDMA_ALC0_CNTL (0x0108 >> 2)
62 #define DPDMA_ALC0_STATUS (0x010C >> 2)
63 #define DPDMA_ALC0_MAX (0x0110 >> 2)
64 #define DPDMA_ALC0_MIN (0x0114 >> 2)
65 #define DPDMA_ALC0_ACC (0x0118 >> 2)
66 #define DPDMA_ALC0_ACC_TRAN (0x011C >> 2)
67 #define DPDMA_ALC1_CNTL (0x0120 >> 2)
68 #define DPDMA_ALC1_STATUS (0x0124 >> 2)
69 #define DPDMA_ALC1_MAX (0x0128 >> 2)
70 #define DPDMA_ALC1_MIN (0x012C >> 2)
71 #define DPDMA_ALC1_ACC (0x0130 >> 2)
72 #define DPDMA_ALC1_ACC_TRAN (0x0134 >> 2)
74 #define DPDMA_DSCR_STRT_ADDRE_CH(n) ((0x0200 + n * 0x100) >> 2)
75 #define DPDMA_DSCR_STRT_ADDR_CH(n) ((0x0204 + n * 0x100) >> 2)
76 #define DPDMA_DSCR_NEXT_ADDRE_CH(n) ((0x0208 + n * 0x100) >> 2)
77 #define DPDMA_DSCR_NEXT_ADDR_CH(n) ((0x020C + n * 0x100) >> 2)
78 #define DPDMA_PYLD_CUR_ADDRE_CH(n) ((0x0210 + n * 0x100) >> 2)
79 #define DPDMA_PYLD_CUR_ADDR_CH(n) ((0x0214 + n * 0x100) >> 2)
81 #define DPDMA_CNTL_CH(n) ((0x0218 + n * 0x100) >> 2)
85 #define DPDMA_STATUS_CH(n) ((0x021C + n * 0x100) >> 2)
97 #define DPDMA_VDO_CH(n) ((0x0220 + n * 0x100) >> 2)
98 #define DPDMA_PYLD_SZ_CH(n) ((0x0224 + n * 0x100) >> 2)
99 #define DPDMA_DSCR_ID_CH(n) ((0x0228 + n * 0x100) >> 2)
162 return ((desc->control & DSCR_CTRL_LAST_DESCRIPTOR) != 0); in xlnx_dpdma_desc_is_last()
167 return ((desc->control & DSCR_CTRL_LAST_DESCRIPTOR_OF_FRAME) != 0); in xlnx_dpdma_desc_is_last_of_frame()
178 addr = (uint64_t)desc->source_address in xlnx_dpdma_desc_get_source_address()
179 + (extract64(desc->address_extension, 16, 16) << 32); in xlnx_dpdma_desc_get_source_address()
182 addr = (uint64_t)desc->source_address2 in xlnx_dpdma_desc_get_source_address()
183 + (extract64(desc->address_extension_23, 0, 16) << 32); in xlnx_dpdma_desc_get_source_address()
185 case 2: in xlnx_dpdma_desc_get_source_address()
186 addr = (uint64_t)desc->source_address3 in xlnx_dpdma_desc_get_source_address()
187 + (extract64(desc->address_extension_23, 16, 16) << 32); in xlnx_dpdma_desc_get_source_address()
190 addr = (uint64_t)desc->source_address4 in xlnx_dpdma_desc_get_source_address()
191 + (extract64(desc->address_extension_45, 0, 16) << 32); in xlnx_dpdma_desc_get_source_address()
194 addr = (uint64_t)desc->source_address5 in xlnx_dpdma_desc_get_source_address()
195 + (extract64(desc->address_extension_45, 16, 16) << 32); in xlnx_dpdma_desc_get_source_address()
207 return desc->xfer_size; in xlnx_dpdma_desc_get_transfer_size()
212 return extract32(desc->line_size_stride, 0, 18); in xlnx_dpdma_desc_get_line_size()
217 return extract32(desc->line_size_stride, 18, 14) * 16; in xlnx_dpdma_desc_get_line_stride()
222 return (desc->control & DSCR_CTRL_ENABLE_CRC) != 0; in xlnx_dpdma_desc_crc_enabled()
239 return crc == desc->crc; in xlnx_dpdma_desc_check_crc()
244 return (desc->control & DSCR_CTRL_EN_DSCR_DONE_INTR) != 0; in xlnx_dpdma_desc_completion_interrupt()
249 return (desc->control & DSCR_CTRL_PREAMBLE) == CONTROL_PREAMBLE_VALUE; in xlnx_dpdma_desc_is_valid()
254 return (desc->control & DSCR_CTRL_DESCRIPTOR_MODE) == 0; in xlnx_dpdma_desc_is_contiguous()
259 return (desc->control & DSCR_CTRL_EN_DSCR_UPDATE) != 0; in xlnx_dpdma_desc_update_enabled()
264 desc->timestamp_msb |= STATUS_DONE; in xlnx_dpdma_desc_set_done()
269 return (desc->timestamp_msb & STATUS_DONE) != 0; in xlnx_dpdma_desc_is_already_done()
274 return (desc->control & DSCR_CTRL_IGNORE_DONE) != 0; in xlnx_dpdma_desc_ignore_done_bit()
292 flags = ((s->registers[DPDMA_ISR] & (~s->registers[DPDMA_IMR])) in xlnx_dpdma_update_irq()
293 || (s->registers[DPDMA_EISR] & (~s->registers[DPDMA_EIMR]))); in xlnx_dpdma_update_irq()
294 qemu_set_irq(s->irq, flags); in xlnx_dpdma_update_irq()
298 uint8_t channel) in xlnx_dpdma_descriptor_start_address() argument
300 return (s->registers[DPDMA_DSCR_STRT_ADDRE_CH(channel)] << 16) in xlnx_dpdma_descriptor_start_address()
301 + s->registers[DPDMA_DSCR_STRT_ADDR_CH(channel)]; in xlnx_dpdma_descriptor_start_address()
305 uint8_t channel) in xlnx_dpdma_descriptor_next_address() argument
307 return ((uint64_t)s->registers[DPDMA_DSCR_NEXT_ADDRE_CH(channel)] << 32) in xlnx_dpdma_descriptor_next_address()
308 + s->registers[DPDMA_DSCR_NEXT_ADDR_CH(channel)]; in xlnx_dpdma_descriptor_next_address()
312 uint8_t channel) in xlnx_dpdma_is_channel_enabled() argument
314 return (s->registers[DPDMA_CNTL_CH(channel)] & DPDMA_CNTL_CH_EN) != 0; in xlnx_dpdma_is_channel_enabled()
318 uint8_t channel) in xlnx_dpdma_is_channel_paused() argument
320 return (s->registers[DPDMA_CNTL_CH(channel)] & DPDMA_CNTL_CH_PAUSED) != 0; in xlnx_dpdma_is_channel_paused()
324 uint8_t channel) in xlnx_dpdma_is_channel_retriggered() argument
327 bool channel_is_retriggered = s->registers[DPDMA_GBL] in xlnx_dpdma_is_channel_retriggered()
328 & DPDMA_GBL_RTRG_CH(channel); in xlnx_dpdma_is_channel_retriggered()
329 s->registers[DPDMA_GBL] &= ~DPDMA_GBL_RTRG_CH(channel); in xlnx_dpdma_is_channel_retriggered()
334 uint8_t channel) in xlnx_dpdma_is_channel_triggered() argument
336 return s->registers[DPDMA_GBL] & DPDMA_GBL_TRG_CH(channel); in xlnx_dpdma_is_channel_triggered()
339 static void xlnx_dpdma_update_desc_info(XlnxDPDMAState *s, uint8_t channel, in xlnx_dpdma_update_desc_info() argument
342 s->registers[DPDMA_DSCR_NEXT_ADDRE_CH(channel)] = in xlnx_dpdma_update_desc_info()
343 extract32(desc->address_extension, 0, 16); in xlnx_dpdma_update_desc_info()
344 s->registers[DPDMA_DSCR_NEXT_ADDR_CH(channel)] = desc->next_descriptor; in xlnx_dpdma_update_desc_info()
345 s->registers[DPDMA_PYLD_CUR_ADDRE_CH(channel)] = in xlnx_dpdma_update_desc_info()
346 extract32(desc->address_extension, 16, 16); in xlnx_dpdma_update_desc_info()
347 s->registers[DPDMA_PYLD_CUR_ADDR_CH(channel)] = desc->source_address; in xlnx_dpdma_update_desc_info()
348 s->registers[DPDMA_VDO_CH(channel)] = in xlnx_dpdma_update_desc_info()
349 extract32(desc->line_size_stride, 18, 14) in xlnx_dpdma_update_desc_info()
350 + (extract32(desc->line_size_stride, 0, 18) in xlnx_dpdma_update_desc_info()
352 s->registers[DPDMA_PYLD_SZ_CH(channel)] = desc->xfer_size; in xlnx_dpdma_update_desc_info()
353 s->registers[DPDMA_DSCR_ID_CH(channel)] = desc->descriptor_id; in xlnx_dpdma_update_desc_info()
356 s->registers[DPDMA_STATUS_CH(channel)] = in xlnx_dpdma_update_desc_info()
357 extract32(desc->control, 0, 8) << 13; in xlnx_dpdma_update_desc_info()
358 if ((desc->control & DSCR_CTRL_EN_DSCR_DONE_INTR) != 0) { in xlnx_dpdma_update_desc_info()
359 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_EN_DSCR_INTR; in xlnx_dpdma_update_desc_info()
361 if ((desc->control & DSCR_CTRL_EN_DSCR_UPDATE) != 0) { in xlnx_dpdma_update_desc_info()
362 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_EN_DSCR_UP; in xlnx_dpdma_update_desc_info()
364 if ((desc->timestamp_msb & STATUS_DONE) != 0) { in xlnx_dpdma_update_desc_info()
365 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_DSCR_DONE; in xlnx_dpdma_update_desc_info()
367 if ((desc->control & DSCR_CTRL_IGNORE_DONE) != 0) { in xlnx_dpdma_update_desc_info()
368 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_IGNR_DONE; in xlnx_dpdma_update_desc_info()
370 if ((desc->control & DSCR_CTRL_LAST_DESCRIPTOR_OF_FRAME) != 0) { in xlnx_dpdma_update_desc_info()
371 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_LDSCR_FRAME; in xlnx_dpdma_update_desc_info()
373 if ((desc->control & DSCR_CTRL_LAST_DESCRIPTOR) != 0) { in xlnx_dpdma_update_desc_info()
374 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_LAST_DSCR; in xlnx_dpdma_update_desc_info()
376 if ((desc->control & DSCR_CTRL_ENABLE_CRC) != 0) { in xlnx_dpdma_update_desc_info()
377 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_EN_CRC; in xlnx_dpdma_update_desc_info()
379 if ((desc->control & DSCR_CTRL_DESCRIPTOR_MODE) != 0) { in xlnx_dpdma_update_desc_info()
380 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_MODE; in xlnx_dpdma_update_desc_info()
382 if ((desc->control & DSCR_CTRL_AXI_BURST_TYPE) != 0) { in xlnx_dpdma_update_desc_info()
383 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_BURST_TYPE; in xlnx_dpdma_update_desc_info()
401 offset = offset >> 2; in xlnx_dpdma_read()
410 assert(offset <= (0xFFC >> 2)); in xlnx_dpdma_read()
411 return s->registers[offset]; in xlnx_dpdma_read()
422 offset = offset >> 2; in xlnx_dpdma_write()
426 s->registers[DPDMA_ISR] &= ~value; in xlnx_dpdma_write()
430 s->registers[DPDMA_IMR] &= ~value; in xlnx_dpdma_write()
433 s->registers[DPDMA_IMR] |= value; in xlnx_dpdma_write()
436 s->registers[DPDMA_EISR] &= ~value; in xlnx_dpdma_write()
440 s->registers[DPDMA_EIMR] &= ~value; in xlnx_dpdma_write()
443 s->registers[DPDMA_EIMR] |= value; in xlnx_dpdma_write()
449 case DPDMA_DSCR_NEXT_ADDRE_CH(2): in xlnx_dpdma_write()
455 case DPDMA_DSCR_NEXT_ADDR_CH(2): in xlnx_dpdma_write()
461 case DPDMA_PYLD_CUR_ADDRE_CH(2): in xlnx_dpdma_write()
467 case DPDMA_PYLD_CUR_ADDR_CH(2): in xlnx_dpdma_write()
473 case DPDMA_STATUS_CH(2): in xlnx_dpdma_write()
479 case DPDMA_VDO_CH(2): in xlnx_dpdma_write()
485 case DPDMA_PYLD_SZ_CH(2): in xlnx_dpdma_write()
491 case DPDMA_DSCR_ID_CH(2): in xlnx_dpdma_write()
503 * We store the value anyway so we can know if the channel is in xlnx_dpdma_write()
506 s->registers[offset] |= value & 0x00000FFF; in xlnx_dpdma_write()
510 case DPDMA_DSCR_STRT_ADDRE_CH(2): in xlnx_dpdma_write()
515 s->registers[offset] = value; in xlnx_dpdma_write()
518 s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(0); in xlnx_dpdma_write()
520 s->registers[offset] = value; in xlnx_dpdma_write()
523 s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(1); in xlnx_dpdma_write()
525 s->registers[offset] = value; in xlnx_dpdma_write()
527 case DPDMA_CNTL_CH(2): in xlnx_dpdma_write()
528 s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(2); in xlnx_dpdma_write()
530 s->registers[offset] = value; in xlnx_dpdma_write()
533 s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(3); in xlnx_dpdma_write()
535 s->registers[offset] = value; in xlnx_dpdma_write()
538 s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(4); in xlnx_dpdma_write()
540 s->registers[offset] = value; in xlnx_dpdma_write()
543 s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(5); in xlnx_dpdma_write()
545 s->registers[offset] = value; in xlnx_dpdma_write()
548 assert(offset <= (0xFFC >> 2)); in xlnx_dpdma_write()
549 s->registers[offset] = value; in xlnx_dpdma_write()
573 memory_region_init_io(&s->iomem, obj, &dma_ops, s, in xlnx_dpdma_init()
575 sysbus_init_mmio(sbd, &s->iomem); in xlnx_dpdma_init()
576 sysbus_init_irq(sbd, &s->irq); in xlnx_dpdma_init()
584 memset(s->registers, 0, sizeof(s->registers)); in xlnx_dpdma_reset()
585 s->registers[DPDMA_IMR] = 0x07FFFFFF; in xlnx_dpdma_reset()
586 s->registers[DPDMA_EIMR] = 0xFFFFFFFF; in xlnx_dpdma_reset()
587 s->registers[DPDMA_ALC0_MIN] = 0x0000FFFF; in xlnx_dpdma_reset()
588 s->registers[DPDMA_ALC1_MIN] = 0x0000FFFF; in xlnx_dpdma_reset()
591 s->data[i] = NULL; in xlnx_dpdma_reset()
592 s->operation_finished[i] = true; in xlnx_dpdma_reset()
600 dc->vmsd = &vmstate_xlnx_dpdma; in xlnx_dpdma_class_init()
629 desc->control = le32_to_cpu(desc->control); in xlnx_dpdma_read_descriptor()
630 desc->descriptor_id = le32_to_cpu(desc->descriptor_id); in xlnx_dpdma_read_descriptor()
631 desc->xfer_size = le32_to_cpu(desc->xfer_size); in xlnx_dpdma_read_descriptor()
632 desc->line_size_stride = le32_to_cpu(desc->line_size_stride); in xlnx_dpdma_read_descriptor()
633 desc->timestamp_lsb = le32_to_cpu(desc->timestamp_lsb); in xlnx_dpdma_read_descriptor()
634 desc->timestamp_msb = le32_to_cpu(desc->timestamp_msb); in xlnx_dpdma_read_descriptor()
635 desc->address_extension = le32_to_cpu(desc->address_extension); in xlnx_dpdma_read_descriptor()
636 desc->next_descriptor = le32_to_cpu(desc->next_descriptor); in xlnx_dpdma_read_descriptor()
637 desc->source_address = le32_to_cpu(desc->source_address); in xlnx_dpdma_read_descriptor()
638 desc->address_extension_23 = le32_to_cpu(desc->address_extension_23); in xlnx_dpdma_read_descriptor()
639 desc->address_extension_45 = le32_to_cpu(desc->address_extension_45); in xlnx_dpdma_read_descriptor()
640 desc->source_address2 = le32_to_cpu(desc->source_address2); in xlnx_dpdma_read_descriptor()
641 desc->source_address3 = le32_to_cpu(desc->source_address3); in xlnx_dpdma_read_descriptor()
642 desc->source_address4 = le32_to_cpu(desc->source_address4); in xlnx_dpdma_read_descriptor()
643 desc->source_address5 = le32_to_cpu(desc->source_address5); in xlnx_dpdma_read_descriptor()
644 desc->crc = le32_to_cpu(desc->crc); in xlnx_dpdma_read_descriptor()
676 size_t xlnx_dpdma_start_operation(XlnxDPDMAState *s, uint8_t channel, in xlnx_dpdma_start_operation() argument
685 assert(channel <= 5); in xlnx_dpdma_start_operation()
687 DPRINTF("start dpdma channel 0x%" PRIX8 "\n", channel); in xlnx_dpdma_start_operation()
689 if (!xlnx_dpdma_is_channel_triggered(s, channel)) { in xlnx_dpdma_start_operation()
690 DPRINTF("Channel isn't triggered..\n"); in xlnx_dpdma_start_operation()
694 if (!xlnx_dpdma_is_channel_enabled(s, channel)) { in xlnx_dpdma_start_operation()
695 DPRINTF("Channel isn't enabled..\n"); in xlnx_dpdma_start_operation()
699 if (xlnx_dpdma_is_channel_paused(s, channel)) { in xlnx_dpdma_start_operation()
700 DPRINTF("Channel is paused..\n"); in xlnx_dpdma_start_operation()
705 if ((s->operation_finished[channel]) in xlnx_dpdma_start_operation()
706 || xlnx_dpdma_is_channel_retriggered(s, channel)) { in xlnx_dpdma_start_operation()
707 desc_addr = xlnx_dpdma_descriptor_start_address(s, channel); in xlnx_dpdma_start_operation()
708 s->operation_finished[channel] = false; in xlnx_dpdma_start_operation()
710 desc_addr = xlnx_dpdma_descriptor_next_address(s, channel); in xlnx_dpdma_start_operation()
714 s->registers[DPDMA_EISR] |= ((1 << 1) << channel); in xlnx_dpdma_start_operation()
716 s->operation_finished[channel] = true; in xlnx_dpdma_start_operation()
721 xlnx_dpdma_update_desc_info(s, channel, &desc); in xlnx_dpdma_start_operation()
729 s->registers[DPDMA_EISR] |= ((1 << 7) << channel); in xlnx_dpdma_start_operation()
731 s->operation_finished[channel] = true; in xlnx_dpdma_start_operation()
738 s->registers[DPDMA_EISR] |= ((1 << 13) << channel); in xlnx_dpdma_start_operation()
740 s->operation_finished[channel] = true; in xlnx_dpdma_start_operation()
748 s->registers[DPDMA_EISR] |= ((1 << 25) << channel); in xlnx_dpdma_start_operation()
750 s->operation_finished[channel] = true; in xlnx_dpdma_start_operation()
758 s->operation_finished[channel] = done; in xlnx_dpdma_start_operation()
759 if (s->data[channel]) { in xlnx_dpdma_start_operation()
768 &s->data[channel][ptr], in xlnx_dpdma_start_operation()
771 s->registers[DPDMA_ISR] |= ((1 << 12) << channel); in xlnx_dpdma_start_operation()
777 transfer_len -= line_size; in xlnx_dpdma_start_operation()
793 - (source_addr[frag] % DPDMA_FRAG_MAX_SZ); in xlnx_dpdma_start_operation()
797 &(s->data[channel][ptr]), in xlnx_dpdma_start_operation()
800 s->registers[DPDMA_ISR] |= ((1 << 12) << channel); in xlnx_dpdma_start_operation()
806 transfer_len -= fragment_len; in xlnx_dpdma_start_operation()
824 s->registers[DPDMA_ISR] |= (1 << channel); in xlnx_dpdma_start_operation()
833 void xlnx_dpdma_set_host_data_location(XlnxDPDMAState *s, uint8_t channel, in xlnx_dpdma_set_host_data_location() argument
842 assert(channel <= 5); in xlnx_dpdma_set_host_data_location()
843 s->data[channel] = p; in xlnx_dpdma_set_host_data_location()
848 s->registers[DPDMA_ISR] |= (1 << 27); in xlnx_dpdma_trigger_vsync_irq()