Lines Matching +full:channel +full:- +full:2
1 /* SPDX-License-Identifier: GPL-2.0+ */
17 #define DMA_START 0 /* DMA command - start DMA */
18 #define DMA_STOP 1 /* DMA command - stop DMA */
19 #define DMA_START_FH_RESET 2 /* DMA command - start DMA reset FH */
20 #define DMA_TAKEOVER 15 /* DMA command - commit the DMA conf */
32 #define TO_DMA_CFG 2 /* takeover command for the DMA config*/
36 #define DMA_CMD_START 2
41 #define DMA_STATE_START 2
46 #define STRM_P 2
51 #define RESET_TIME 2 /* cycle calc see in SCC_Reset */
62 u32 p_mci_id; /* memory channel ID */
85 u32 dma_status:2; /* state of DMA, of the DMA_STATE_ const*/
86 u32 dma_drs:2; /* DMA dir, either DMA_READ or DMA_WRITE*/
95 u32 rid:2; /* Register Identifier */
136 * System on Chip Channel ID
139 SCC_NULL = -1, /* illegal SCC identifier */
140 SCC_FE_3DCOMB_WR, /* SCC_FE_3DCOMB Write channel */
141 SCC_FE_3DCOMB_RD, /* SCC_FE_3DCOMB Read channel */
142 SCC_DI_TNR_WR, /* SCC_DI_TNR Write channel */
143 SCC_DI_TNR_FIELD_RD, /* SCC_DI_TNR_FIELD Read channel */
144 SCC_DI_TNR_FRAME_RD, /* SCC_DI_TNR_FRAME Read channel */
145 SCC_DI_MVAL_WR, /* SCC_DI_MVAL Write channel */
146 SCC_DI_MVAL_RD, /* SCC_DI_MVAL Read channel */
147 SCC_RC_FRAME_WR, /* SCC_RC_FRAME Write channel */
148 SCC_RC_FRAME0_RD, /* SCC_RC_FRAME0 Read channel */
149 SCC_OPT_FIELD0_RD, /* SCC_OPT_FIELD0 Read channel */
150 SCC_OPT_FIELD1_RD, /* SCC_OPT_FIELD1 Read channel */
151 SCC_OPT_FIELD2_RD, /* SCC_OPT_FIELD2 Read channel */
152 SCC_PIP_FRAME_WR, /* SCC_PIP_FRAME Write channel */
153 SCC_PIP_FRAME_RD, /* SCC_PIP_FRAME Read channel */
154 SCC_DP_AGPU_RD, /* SCC_DP_AGPU Read channel */
155 SCC_EWARP_RW, /* SCC_EWARP Read/Write channel */
156 SCC_DP_OSD_RD, /* SCC_DP_OSD Read channel */
157 SCC_DP_GRAPHIC_RD, /* SCC_DP_GRAPHIC Read channel */
158 SCC_DVP_OSD_RD, /* SCC_DVP_OSD Read channel */
159 SCC_DVP_VBI_RD, /* SCC_DVP_VBI Read channel */
160 SCC_TSIO_WR, /* SCC_TSIO Write channel */
161 SCC_TSIO_RD, /* SCC_TSIO Read channel */
162 SCC_TSD_WR, /* SCC_TSD Write channel */
163 SCC_VD_UD_ST_RW, /* SCC_VD_UD_ST Read/Write channel */
164 SCC_VD_FRR_RD, /* SCC_VD_FRR Read channel */
165 SCC_VD_FRW_DISP_WR, /* SCC_VD_FRW_DISP Write channel */
166 SCC_MR_VD_M_Y_RD, /* SCC_MR_VD_M_Y Read channel */
167 SCC_MR_VD_M_C_RD, /* SCC_MR_VD_M_C Read channel */
168 SCC_MR_VD_S_Y_RD, /* SCC_MR_VD_S_Y Read channel */
169 SCC_MR_VD_S_C_RD, /* SCC_MR_VD_S_C Read channel */
170 SCC_GA_WR, /* SCC_GA Write channel */
171 SCC_GA_SRC1_RD, /* SCC_GA_SRC1 Read channel */
172 SCC_GA_SRC2_RD, /* SCC_GA_SRC2 Read channel */
173 SCC_AD_RD, /* SCC_AD Read channel */
174 SCC_AD_WR, /* SCC_AD Write channel */
175 SCC_ABP_RD, /* SCC_ABP Read channel */
176 SCC_ABP_WR, /* SCC_ABP Write channel */
177 SCC_EBI_RW, /* SCC_EBI Read/Write channel */
178 SCC_USB_RW, /* SCC_USB Read/Write channel */
179 SCC_CPU1_SPDMA_RW, /* SCC_CPU1_SPDMA Read/Write channel */
180 SCC_CPU1_BRIDGE_RW, /* SCC_CPU1_BRIDGE Read/Write channel */