1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2012771d8Swdenk /* 3012771d8Swdenk * (C) Copyright 2000 4012771d8Swdenk * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. 5012771d8Swdenk */ 6012771d8Swdenk 7012771d8Swdenk /* winbond access routines and defines*/ 8012771d8Swdenk 9012771d8Swdenk /* from the winbond data sheet - 10012771d8Swdenk The W83C553F SIO controller with PCI arbiter is a multi-function PCI device. 11012771d8Swdenk Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller. 12012771d8Swdenk */ 13012771d8Swdenk 14012771d8Swdenk /*ISA bridge configuration space*/ 15012771d8Swdenk 16012771d8Swdenk #define W83C553F_VID 0x10AD 17012771d8Swdenk #define W83C553F_DID 0x0565 18012771d8Swdenk 19012771d8Swdenk #define WINBOND_PCICONTR 0x40 /*pci control reg*/ 20012771d8Swdenk #define WINBOND_SGBAR 0x41 /*scatter/gather base address reg*/ 21012771d8Swdenk #define WINBOND_LBCR 0x42 /*Line Buffer Control reg*/ 22012771d8Swdenk #define WINBOND_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/ 23012771d8Swdenk #define WINBOND_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/ 24012771d8Swdenk #define WINBOND_BTBAR 0x46 /*BIOS Timer Base Address Register*/ 25012771d8Swdenk #define WINBOND_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/ 26012771d8Swdenk #define WINBOND_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/ 27012771d8Swdenk #define WINBOND_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/ 28012771d8Swdenk #define WINBOND_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/ 29012771d8Swdenk #define WINBOND_CDR 0x4c /*Clock Divisor Register*/ 30012771d8Swdenk #define WINBOND_CSCR 0x4d /*Chip Select Control Register*/ 31012771d8Swdenk #define WINBOND_ATSCR 0x4e /*AT System Control register*/ 32012771d8Swdenk #define WINBOND_ATBCR 0x4f /*AT Bus ControL Register*/ 33012771d8Swdenk #define WINBOND_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/ 34012771d8Swdenk #define WINBOND_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/ 35012771d8Swdenk #define WINBOND_ABEER 0x62 /*Additional Break Event Enable Register*/ 36012771d8Swdenk #define WINBOND_DMABEER 0x63 /*DMA Break Event Enable Register*/ 37012771d8Swdenk 38012771d8Swdenk #define WINDOND_IDECSR 0x40 /*IDE Control/Status Register, Function 1*/ 39012771d8Swdenk 40012771d8Swdenk #define IPADCR_MBE512 0x1 41012771d8Swdenk #define IPADCR_MBE640 0x2 42012771d8Swdenk #define IPADCR_IPATOM4 0x10 43012771d8Swdenk #define IPADCR_IPATOM5 0x20 44012771d8Swdenk #define IPADCR_IPATOM6 0x40 45012771d8Swdenk #define IPADCR_IPATOM7 0x80 46012771d8Swdenk 47012771d8Swdenk #define CSCR_UBIOSCSE 0x10 48012771d8Swdenk #define CSCR_BIOSWP 0x20 49012771d8Swdenk 50012771d8Swdenk #define IDECSR_P0EN 0x01 51012771d8Swdenk #define IDECSR_P0F16 0x02 52012771d8Swdenk #define IDECSR_P1EN 0x10 53012771d8Swdenk #define IDECSR_P1F16 0x20 54012771d8Swdenk #define IDECSR_LEGIRQ 0x800 55012771d8Swdenk 56012771d8Swdenk /* 57012771d8Swdenk * Interrupt controller 58012771d8Swdenk */ 596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC1_ICW1 CONFIG_SYS_ISA_IO + 0x20 606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC1_ICW2 CONFIG_SYS_ISA_IO + 0x21 616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC1_ICW3 CONFIG_SYS_ISA_IO + 0x21 626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC1_ICW4 CONFIG_SYS_ISA_IO + 0x21 636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC1_OCW1 CONFIG_SYS_ISA_IO + 0x21 646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC1_OCW2 CONFIG_SYS_ISA_IO + 0x20 656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC1_OCW3 CONFIG_SYS_ISA_IO + 0x20 666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC1_ELC CONFIG_SYS_ISA_IO + 0x4D0 676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC2_ICW1 CONFIG_SYS_ISA_IO + 0xA0 686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC2_ICW2 CONFIG_SYS_ISA_IO + 0xA1 696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC2_ICW3 CONFIG_SYS_ISA_IO + 0xA1 706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC2_ICW4 CONFIG_SYS_ISA_IO + 0xA1 716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC2_OCW1 CONFIG_SYS_ISA_IO + 0xA1 726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC2_OCW2 CONFIG_SYS_ISA_IO + 0xA0 736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC2_OCW3 CONFIG_SYS_ISA_IO + 0xA0 746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC2_ELC CONFIG_SYS_ISA_IO + 0x4D1 75012771d8Swdenk 766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_TMR1_CMOD CONFIG_SYS_ISA_IO + 0x43 77012771d8Swdenk 78012771d8Swdenk /* 79012771d8Swdenk * DMA controller 80012771d8Swdenk */ 816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_DMA1 CONFIG_SYS_ISA_IO + 0x000 /* channel 0 - 3 */ 826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_DMA2 CONFIG_SYS_ISA_IO + 0x0C0 /* channel 4 - 7 */ 83012771d8Swdenk 84012771d8Swdenk /* command/status register bit definitions */ 85012771d8Swdenk 86012771d8Swdenk #define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */ 87012771d8Swdenk #define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */ 88012771d8Swdenk #define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */ 89012771d8Swdenk #define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */ 90012771d8Swdenk 91012771d8Swdenk #define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */ 92012771d8Swdenk #define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */ 93012771d8Swdenk #define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */ 94012771d8Swdenk #define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */ 95012771d8Swdenk 96012771d8Swdenk #define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */ 97012771d8Swdenk #define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */ 98012771d8Swdenk #define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */ 99012771d8Swdenk #define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */ 100012771d8Swdenk 101012771d8Swdenk /* mode register bit definitions */ 102012771d8Swdenk 103012771d8Swdenk #define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */ 104012771d8Swdenk #define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */ 105012771d8Swdenk #define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */ 106012771d8Swdenk #define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */ 107012771d8Swdenk #define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */ 108012771d8Swdenk #define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */ 109012771d8Swdenk #define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */ 110012771d8Swdenk #define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */ 111012771d8Swdenk #define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */ 112012771d8Swdenk #define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */ 113012771d8Swdenk #define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */ 114012771d8Swdenk #define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */ 115012771d8Swdenk #define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */ 116012771d8Swdenk #define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */ 117012771d8Swdenk 118012771d8Swdenk /* request register bit definitions */ 119012771d8Swdenk 120012771d8Swdenk #define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */ 121012771d8Swdenk #define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */ 122012771d8Swdenk #define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */ 123012771d8Swdenk #define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */ 124012771d8Swdenk #define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */ 125012771d8Swdenk 126012771d8Swdenk /* write single mask bit register bit definitions */ 127012771d8Swdenk 128012771d8Swdenk #define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */ 129012771d8Swdenk #define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */ 130012771d8Swdenk #define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */ 131012771d8Swdenk #define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */ 132012771d8Swdenk #define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */ 133012771d8Swdenk 134012771d8Swdenk /* read/write all mask bits register bit definitions */ 135012771d8Swdenk 136012771d8Swdenk #define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */ 137012771d8Swdenk #define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */ 138012771d8Swdenk #define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */ 139012771d8Swdenk #define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */ 140012771d8Swdenk 141012771d8Swdenk /* typedefs */ 142012771d8Swdenk 143012771d8Swdenk #define W83C553F_DMA1_CS 0x8 144012771d8Swdenk #define W83C553F_DMA1_WR 0x9 145012771d8Swdenk #define W83C553F_DMA1_WSMB 0xA 146012771d8Swdenk #define W83C553F_DMA1_WM 0xB 147012771d8Swdenk #define W83C553F_DMA1_CBP 0xC 148012771d8Swdenk #define W83C553F_DMA1_MC 0xD 149012771d8Swdenk #define W83C553F_DMA1_CM 0xE 150012771d8Swdenk #define W83C553F_DMA1_RWAMB 0xF 151012771d8Swdenk 152012771d8Swdenk #define W83C553F_DMA2_CS 0x10 153012771d8Swdenk #define W83C553F_DMA2_WR 0x12 154012771d8Swdenk #define W83C553F_DMA2_WSMB 0x14 155012771d8Swdenk #define W83C553F_DMA2_WM 0x16 156012771d8Swdenk #define W83C553F_DMA2_CBP 0x18 157012771d8Swdenk #define W83C553F_DMA2_MC 0x1A 158012771d8Swdenk #define W83C553F_DMA2_CM 0x1C 159012771d8Swdenk #define W83C553F_DMA2_RWAMB 0x1E 160012771d8Swdenk 161012771d8Swdenk void initialise_w83c553f(void); 162