11a59d1b8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 21da177e4SLinus Torvalds /* 31da177e4SLinus Torvalds * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk> 41da177e4SLinus Torvalds * Driver CA0106 chips. e.g. Sound Blaster Audigy LS and Live 24bit 5b18cd538STrent Piepho * Version: 0.0.22 61da177e4SLinus Torvalds * 71da177e4SLinus Torvalds * FEATURES currently supported: 81da177e4SLinus Torvalds * See ca0106_main.c for features. 91da177e4SLinus Torvalds * 101da177e4SLinus Torvalds * Changelog: 111da177e4SLinus Torvalds * Support interrupts per period. 121da177e4SLinus Torvalds * Removed noise from Center/LFE channel when in Analog mode. 131da177e4SLinus Torvalds * Rename and remove mixer controls. 141da177e4SLinus Torvalds * 0.0.6 151da177e4SLinus Torvalds * Use separate card based DMA buffer for periods table list. 161da177e4SLinus Torvalds * 0.0.7 171da177e4SLinus Torvalds * Change remove and rename ctrls into lists. 181da177e4SLinus Torvalds * 0.0.8 191da177e4SLinus Torvalds * Try to fix capture sources. 201da177e4SLinus Torvalds * 0.0.9 211da177e4SLinus Torvalds * Fix AC3 output. 221da177e4SLinus Torvalds * Enable S32_LE format support. 231da177e4SLinus Torvalds * 0.0.10 241da177e4SLinus Torvalds * Enable playback 48000 and 96000 rates. (Rates other that these do not work, even with "plug:front".) 251da177e4SLinus Torvalds * 0.0.11 261da177e4SLinus Torvalds * Add Model name recognition. 271da177e4SLinus Torvalds * 0.0.12 281da177e4SLinus Torvalds * Correct interrupt timing. interrupt at end of period, instead of in the middle of a playback period. 291da177e4SLinus Torvalds * Remove redundent "voice" handling. 301da177e4SLinus Torvalds * 0.0.13 311da177e4SLinus Torvalds * Single trigger call for multi channels. 321da177e4SLinus Torvalds * 0.0.14 331da177e4SLinus Torvalds * Set limits based on what the sound card hardware can do. 341da177e4SLinus Torvalds * playback periods_min=2, periods_max=8 351da177e4SLinus Torvalds * capture hw constraints require period_size = n * 64 bytes. 361da177e4SLinus Torvalds * playback hw constraints require period_size = n * 64 bytes. 371da177e4SLinus Torvalds * 0.0.15 381da177e4SLinus Torvalds * Separated ca0106.c into separate functional .c files. 391da177e4SLinus Torvalds * 0.0.16 401da177e4SLinus Torvalds * Implement 192000 sample rate. 411da177e4SLinus Torvalds * 0.0.17 421da177e4SLinus Torvalds * Add support for SB0410 and SB0413. 431da177e4SLinus Torvalds * 0.0.18 441da177e4SLinus Torvalds * Modified Copyright message. 451da177e4SLinus Torvalds * 0.0.19 461da177e4SLinus Torvalds * Added I2C and SPI registers. Filled in interrupt enable. 471da177e4SLinus Torvalds * 0.0.20 481da177e4SLinus Torvalds * Added GPIO info for SB Live 24bit. 497199acdcSJames Courtier-Dutton * 0.0.21 507199acdcSJames Courtier-Dutton * Implement support for Line-in capture on SB Live 24bit. 51b18cd538STrent Piepho * 0.0.22 52b18cd538STrent Piepho * Add support for mute control on SB Live 24bit (cards w/ SPI DAC) 531da177e4SLinus Torvalds * 5425985edcSLucas De Marchi * This code was initially based on code from ALSA's emu10k1x.c which is: 551da177e4SLinus Torvalds * Copyright (c) by Francisco Moraes <fmoraes@nc.rr.com> 561da177e4SLinus Torvalds */ 571da177e4SLinus Torvalds 581da177e4SLinus Torvalds /************************************************************************************************/ 591da177e4SLinus Torvalds /* PCI function 0 registers, address = <val> + PCIBASE0 */ 601da177e4SLinus Torvalds /************************************************************************************************/ 611da177e4SLinus Torvalds 62*fdb1e569STakashi Iwai #define CA0106_PTR 0x00 /* Indexed register set pointer register */ 631da177e4SLinus Torvalds /* NOTE: The CHANNELNUM and ADDRESS words can */ 641da177e4SLinus Torvalds /* be modified independently of each other. */ 651da177e4SLinus Torvalds /* CNL[1:0], ADDR[27:16] */ 661da177e4SLinus Torvalds 67*fdb1e569STakashi Iwai #define CA0106_DATA 0x04 /* Indexed register set data register */ 681da177e4SLinus Torvalds /* DATA[31:0] */ 691da177e4SLinus Torvalds 70*fdb1e569STakashi Iwai #define CA0106_IPR 0x08 /* Global interrupt pending register */ 711da177e4SLinus Torvalds /* Clear pending interrupts by writing a 1 to */ 721da177e4SLinus Torvalds /* the relevant bits and zero to the other bits */ 731da177e4SLinus Torvalds #define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */ 741da177e4SLinus Torvalds #define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */ 751da177e4SLinus Torvalds #define IPR_SPDIF_IN_USER 0x00004000 /* SPDIF input user data has 16 more bits */ 761da177e4SLinus Torvalds #define IPR_SPDIF_OUT_USER 0x00002000 /* SPDIF output user data needs 16 more bits */ 771da177e4SLinus Torvalds #define IPR_SPDIF_OUT_FRAME 0x00001000 /* SPDIF frame about to start */ 781da177e4SLinus Torvalds #define IPR_SPI 0x00000800 /* SPI transaction completed */ 791da177e4SLinus Torvalds #define IPR_I2C_EEPROM 0x00000400 /* I2C EEPROM transaction completed */ 801da177e4SLinus Torvalds #define IPR_I2C_DAC 0x00000200 /* I2C DAC transaction completed */ 811da177e4SLinus Torvalds #define IPR_AI 0x00000100 /* Audio pending register changed. See PTR reg 0x76 */ 821da177e4SLinus Torvalds #define IPR_GPI 0x00000080 /* General Purpose input changed */ 831da177e4SLinus Torvalds #define IPR_SRC_LOCKED 0x00000040 /* SRC lock status changed */ 841da177e4SLinus Torvalds #define IPR_SPDIF_STATUS 0x00000020 /* SPDIF status changed */ 851da177e4SLinus Torvalds #define IPR_TIMER2 0x00000010 /* 192000Hz Timer */ 861da177e4SLinus Torvalds #define IPR_TIMER1 0x00000008 /* 44100Hz Timer */ 871da177e4SLinus Torvalds #define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */ 881da177e4SLinus Torvalds #define IPR_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */ 891da177e4SLinus Torvalds #define IPR_PCI 0x00000001 /* PCI Bus error */ 901da177e4SLinus Torvalds 91*fdb1e569STakashi Iwai #define CA0106_INTE 0x0c /* Interrupt enable register */ 921da177e4SLinus Torvalds 931da177e4SLinus Torvalds #define INTE_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */ 941da177e4SLinus Torvalds #define INTE_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */ 951da177e4SLinus Torvalds #define INTE_SPDIF_IN_USER 0x00004000 /* SPDIF input user data has 16 more bits */ 961da177e4SLinus Torvalds #define INTE_SPDIF_OUT_USER 0x00002000 /* SPDIF output user data needs 16 more bits */ 971da177e4SLinus Torvalds #define INTE_SPDIF_OUT_FRAME 0x00001000 /* SPDIF frame about to start */ 981da177e4SLinus Torvalds #define INTE_SPI 0x00000800 /* SPI transaction completed */ 991da177e4SLinus Torvalds #define INTE_I2C_EEPROM 0x00000400 /* I2C EEPROM transaction completed */ 1001da177e4SLinus Torvalds #define INTE_I2C_DAC 0x00000200 /* I2C DAC transaction completed */ 1011da177e4SLinus Torvalds #define INTE_AI 0x00000100 /* Audio pending register changed. See PTR reg 0x75 */ 1021da177e4SLinus Torvalds #define INTE_GPI 0x00000080 /* General Purpose input changed */ 1031da177e4SLinus Torvalds #define INTE_SRC_LOCKED 0x00000040 /* SRC lock status changed */ 1041da177e4SLinus Torvalds #define INTE_SPDIF_STATUS 0x00000020 /* SPDIF status changed */ 1051da177e4SLinus Torvalds #define INTE_TIMER2 0x00000010 /* 192000Hz Timer */ 1061da177e4SLinus Torvalds #define INTE_TIMER1 0x00000008 /* 44100Hz Timer */ 1071da177e4SLinus Torvalds #define INTE_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */ 1081da177e4SLinus Torvalds #define INTE_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */ 1091da177e4SLinus Torvalds #define INTE_PCI 0x00000001 /* PCI Bus error */ 1101da177e4SLinus Torvalds 111*fdb1e569STakashi Iwai #define CA0106_UNKNOWN10 0x10 /* Unknown ??. Defaults to 0 */ 112*fdb1e569STakashi Iwai #define CA0106_HCFG 0x14 /* Hardware config register */ 1131da177e4SLinus Torvalds /* 0x1000 causes AC3 to fails. It adds a dither bit. */ 1141da177e4SLinus Torvalds 1151da177e4SLinus Torvalds #define HCFG_STAC 0x10000000 /* Special mode for STAC9460 Codec. */ 1161da177e4SLinus Torvalds #define HCFG_CAPTURE_I2S_BYPASS 0x08000000 /* 1 = bypass I2S input async SRC. */ 1171da177e4SLinus Torvalds #define HCFG_CAPTURE_SPDIF_BYPASS 0x04000000 /* 1 = bypass SPDIF input async SRC. */ 1181da177e4SLinus Torvalds #define HCFG_PLAYBACK_I2S_BYPASS 0x02000000 /* 0 = I2S IN mixer output, 1 = I2S IN1. */ 1191da177e4SLinus Torvalds #define HCFG_FORCE_LOCK 0x01000000 /* For test only. Force input SRC tracker to lock. */ 1201da177e4SLinus Torvalds #define HCFG_PLAYBACK_ATTENUATION 0x00006000 /* Playback attenuation mask. 0 = 0dB, 1 = 6dB, 2 = 12dB, 3 = Mute. */ 1211da177e4SLinus Torvalds #define HCFG_PLAYBACK_DITHER 0x00001000 /* 1 = Add dither bit to all playback channels. */ 1221da177e4SLinus Torvalds #define HCFG_PLAYBACK_S32_LE 0x00000800 /* 1 = S32_LE, 0 = S16_LE */ 1231da177e4SLinus Torvalds #define HCFG_CAPTURE_S32_LE 0x00000400 /* 1 = S32_LE, 0 = S16_LE (S32_LE current not working) */ 1241da177e4SLinus Torvalds #define HCFG_8_CHANNEL_PLAY 0x00000200 /* 1 = 8 channels, 0 = 2 channels per substream.*/ 1251da177e4SLinus Torvalds #define HCFG_8_CHANNEL_CAPTURE 0x00000100 /* 1 = 8 channels, 0 = 2 channels per substream.*/ 1261da177e4SLinus Torvalds #define HCFG_MONO 0x00000080 /* 1 = I2S Input mono */ 1271da177e4SLinus Torvalds #define HCFG_I2S_OUTPUT 0x00000010 /* 1 = I2S Output disabled */ 1281da177e4SLinus Torvalds #define HCFG_AC97 0x00000008 /* 0 = AC97 1.0, 1 = AC97 2.0 */ 1291da177e4SLinus Torvalds #define HCFG_LOCK_PLAYBACK_CACHE 0x00000004 /* 1 = Cancel bustmaster accesses to soundcache */ 1301da177e4SLinus Torvalds /* NOTE: This should generally never be used. */ 1311da177e4SLinus Torvalds #define HCFG_LOCK_CAPTURE_CACHE 0x00000002 /* 1 = Cancel bustmaster accesses to soundcache */ 1321da177e4SLinus Torvalds /* NOTE: This should generally never be used. */ 1331da177e4SLinus Torvalds #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */ 1341da177e4SLinus Torvalds /* Should be set to 1 when the EMU10K1 is */ 1351da177e4SLinus Torvalds /* completely initialized. */ 136*fdb1e569STakashi Iwai #define CA0106_GPIO 0x18 /* Defaults: 005f03a3-Analog, 005f02a2-SPDIF. */ 1371da177e4SLinus Torvalds /* Here pins 0,1,2,3,4,,6 are output. 5,7 are input */ 1381da177e4SLinus Torvalds /* For the Audigy LS, pin 0 (or bit 8) controls the SPDIF/Analog jack. */ 1391da177e4SLinus Torvalds /* SB Live 24bit: 1401da177e4SLinus Torvalds * bit 8 0 = SPDIF in and out / 1 = Analog (Mic or Line)-in. 1411da177e4SLinus Torvalds * bit 9 0 = Mute / 1 = Analog out. 1421da177e4SLinus Torvalds * bit 10 0 = Line-in / 1 = Mic-in. 1431da177e4SLinus Torvalds * bit 11 0 = ? / 1 = ? 144c82bf829SJames Courtier-Dutton * bit 12 0 = 48 Khz / 1 = 96 Khz Analog out on SB Live 24bit. 1451da177e4SLinus Torvalds * bit 13 0 = ? / 1 = ? 1461da177e4SLinus Torvalds * bit 14 0 = Mute / 1 = Analog out 1471da177e4SLinus Torvalds * bit 15 0 = ? / 1 = ? 1481da177e4SLinus Torvalds * Both bit 9 and bit 14 have to be set for analog sound to work on the SB Live 24bit. 1491da177e4SLinus Torvalds */ 1501da177e4SLinus Torvalds /* 8 general purpose programmable In/Out pins. 1511da177e4SLinus Torvalds * GPI [8:0] Read only. Default 0. 1521da177e4SLinus Torvalds * GPO [15:8] Default 0x9. (Default to SPDIF jack enabled for SPDIF) 1531da177e4SLinus Torvalds * GPO Enable [23:16] Default 0x0f. Setting a bit to 1, causes the pin to be an output pin. 1541da177e4SLinus Torvalds */ 155*fdb1e569STakashi Iwai #define CA0106_AC97DATA 0x1c /* AC97 register set data register (16 bit) */ 1561da177e4SLinus Torvalds 157*fdb1e569STakashi Iwai #define CA0106_AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */ 1581da177e4SLinus Torvalds 1591da177e4SLinus Torvalds /********************************************************************************************************/ 1601da177e4SLinus Torvalds /* CA0106 pointer-offset register set, accessed through the PTR and DATA registers */ 1611da177e4SLinus Torvalds /********************************************************************************************************/ 1621da177e4SLinus Torvalds 16325985edcSLucas De Marchi /* Initially all registers from 0x00 to 0x3f have zero contents. */ 1641da177e4SLinus Torvalds #define PLAYBACK_LIST_ADDR 0x00 /* Base DMA address of a list of pointers to each period/size */ 1651da177e4SLinus Torvalds /* One list entry: 4 bytes for DMA address, 1661da177e4SLinus Torvalds * 4 bytes for period_size << 16. 1671da177e4SLinus Torvalds * One list entry is 8 bytes long. 1681da177e4SLinus Torvalds * One list entry for each period in the buffer. 1691da177e4SLinus Torvalds */ 1701da177e4SLinus Torvalds /* ADDR[31:0], Default: 0x0 */ 1711da177e4SLinus Torvalds #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */ 1721da177e4SLinus Torvalds /* SIZE[21:16], Default: 0x8 */ 1731da177e4SLinus Torvalds #define PLAYBACK_LIST_PTR 0x02 /* Pointer to the current period being played */ 1741da177e4SLinus Torvalds /* PTR[5:0], Default: 0x0 */ 1751da177e4SLinus Torvalds #define PLAYBACK_UNKNOWN3 0x03 /* Not used ?? */ 176b595076aSUwe Kleine-König #define PLAYBACK_DMA_ADDR 0x04 /* Playback DMA address */ 1771da177e4SLinus Torvalds /* DMA[31:0], Default: 0x0 */ 1781da177e4SLinus Torvalds #define PLAYBACK_PERIOD_SIZE 0x05 /* Playback period size. win2000 uses 0x04000000 */ 1791da177e4SLinus Torvalds /* SIZE[31:16], Default: 0x0 */ 1801da177e4SLinus Torvalds #define PLAYBACK_POINTER 0x06 /* Playback period pointer. Used with PLAYBACK_LIST_PTR to determine buffer position currently in DAC */ 1811da177e4SLinus Torvalds /* POINTER[15:0], Default: 0x0 */ 1821da177e4SLinus Torvalds #define PLAYBACK_PERIOD_END_ADDR 0x07 /* Playback fifo end address */ 1831da177e4SLinus Torvalds /* END_ADDR[15:0], FLAG[16] 0 = don't stop, 1 = stop */ 1841da177e4SLinus Torvalds #define PLAYBACK_FIFO_OFFSET_ADDRESS 0x08 /* Current fifo offset address [21:16] */ 1851da177e4SLinus Torvalds /* Cache size valid [5:0] */ 1861da177e4SLinus Torvalds #define PLAYBACK_UNKNOWN9 0x09 /* 0x9 to 0xf Unused */ 1871da177e4SLinus Torvalds #define CAPTURE_DMA_ADDR 0x10 /* Capture DMA address */ 1881da177e4SLinus Torvalds /* DMA[31:0], Default: 0x0 */ 1891da177e4SLinus Torvalds #define CAPTURE_BUFFER_SIZE 0x11 /* Capture buffer size */ 1901da177e4SLinus Torvalds /* SIZE[31:16], Default: 0x0 */ 1911da177e4SLinus Torvalds #define CAPTURE_POINTER 0x12 /* Capture buffer pointer. Sample currently in ADC */ 1921da177e4SLinus Torvalds /* POINTER[15:0], Default: 0x0 */ 1931da177e4SLinus Torvalds #define CAPTURE_FIFO_OFFSET_ADDRESS 0x13 /* Current fifo offset address [21:16] */ 1941da177e4SLinus Torvalds /* Cache size valid [5:0] */ 1951da177e4SLinus Torvalds #define PLAYBACK_LAST_SAMPLE 0x20 /* The sample currently being played */ 1961da177e4SLinus Torvalds /* 0x21 - 0x3f unused */ 1971da177e4SLinus Torvalds #define BASIC_INTERRUPT 0x40 /* Used by both playback and capture interrupt handler */ 1981da177e4SLinus Torvalds /* Playback (0x1<<channel_id) */ 1991da177e4SLinus Torvalds /* Capture (0x100<<channel_id) */ 2001da177e4SLinus Torvalds /* Playback sample rate 96000 = 0x20000 */ 2011da177e4SLinus Torvalds /* Start Playback [3:0] (one bit per channel) 2021da177e4SLinus Torvalds * Start Capture [11:8] (one bit per channel) 2031da177e4SLinus Torvalds * Playback rate [23:16] (2 bits per channel) (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz) 2041da177e4SLinus Torvalds * Playback mixer in enable [27:24] (one bit per channel) 2051da177e4SLinus Torvalds * Playback mixer out enable [31:28] (one bit per channel) 2061da177e4SLinus Torvalds */ 2071da177e4SLinus Torvalds /* The Digital out jack is shared with the Center/LFE Analogue output. 2081da177e4SLinus Torvalds * The jack has 4 poles. I will call 1 - Tip, 2 - Next to 1, 3 - Next to 2, 4 - Next to 3 2091da177e4SLinus Torvalds * For Analogue: 1 -> Center Speaker, 2 -> Sub Woofer, 3 -> Ground, 4 -> Ground 2101da177e4SLinus Torvalds * For Digital: 1 -> Front SPDIF, 2 -> Rear SPDIF, 3 -> Center/Subwoofer SPDIF, 4 -> Ground. 21125985edcSLucas De Marchi * Standard 4 pole Video A/V cable with RCA outputs: 1 -> White, 2 -> Yellow, 3 -> Shield on all three, 4 -> Red. 2121da177e4SLinus Torvalds * So, from this you can see that you cannot use a Standard 4 pole Video A/V cable with the SB Audigy LS card. 2131da177e4SLinus Torvalds */ 2141da177e4SLinus Torvalds /* The Front SPDIF PCM gets mixed with samples from the AC97 codec, so can only work for Stereo PCM and not AC3/DTS 2151da177e4SLinus Torvalds * The Rear SPDIF can be used for Stereo PCM and also AC3/DTS 2161da177e4SLinus Torvalds * The Center/LFE SPDIF cannot be used for AC3/DTS, but can be used for Stereo PCM. 2171da177e4SLinus Torvalds * Summary: For ALSA we use the Rear channel for SPDIF Digital AC3/DTS output 2181da177e4SLinus Torvalds */ 2191da177e4SLinus Torvalds /* A standard 2 pole mono mini-jack to RCA plug can be used for SPDIF Stereo PCM output from the Front channel. 2201da177e4SLinus Torvalds * A standard 3 pole stereo mini-jack to 2 RCA plugs can be used for SPDIF AC3/DTS and Stereo PCM output utilising the Rear channel and just one of the RCA plugs. 2211da177e4SLinus Torvalds */ 2221da177e4SLinus Torvalds #define SPCS0 0x41 /* SPDIF output Channel Status 0 register. For Rear. default=0x02108004, non-audio=0x02108006 */ 2231da177e4SLinus Torvalds #define SPCS1 0x42 /* SPDIF output Channel Status 1 register. For Front */ 2241da177e4SLinus Torvalds #define SPCS2 0x43 /* SPDIF output Channel Status 2 register. For Center/LFE */ 2251da177e4SLinus Torvalds #define SPCS3 0x44 /* SPDIF output Channel Status 3 register. Unknown */ 2261da177e4SLinus Torvalds /* When Channel set to 0: */ 2271da177e4SLinus Torvalds #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */ 2281da177e4SLinus Torvalds #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */ 2291da177e4SLinus Torvalds #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */ 2301da177e4SLinus Torvalds #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */ 2311da177e4SLinus Torvalds #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */ 2321da177e4SLinus Torvalds #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */ 2331da177e4SLinus Torvalds #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */ 2341da177e4SLinus Torvalds #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */ 2351da177e4SLinus Torvalds #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */ 2361da177e4SLinus Torvalds #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */ 2371da177e4SLinus Torvalds #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */ 2381da177e4SLinus Torvalds #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */ 2391da177e4SLinus Torvalds #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */ 2401da177e4SLinus Torvalds #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */ 2411da177e4SLinus Torvalds #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */ 2421da177e4SLinus Torvalds #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */ 2431da177e4SLinus Torvalds #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */ 2441da177e4SLinus Torvalds #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */ 2451da177e4SLinus Torvalds #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */ 2461da177e4SLinus Torvalds #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */ 2471da177e4SLinus Torvalds #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */ 2481da177e4SLinus Torvalds #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */ 2491da177e4SLinus Torvalds #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */ 2501da177e4SLinus Torvalds 2511da177e4SLinus Torvalds /* When Channel set to 1: */ 2521da177e4SLinus Torvalds #define SPCS_WORD_LENGTH_MASK 0x0000000f /* Word Length Mask */ 2531da177e4SLinus Torvalds #define SPCS_WORD_LENGTH_16 0x00000008 /* Word Length 16 bit */ 2541da177e4SLinus Torvalds #define SPCS_WORD_LENGTH_17 0x00000006 /* Word Length 17 bit */ 2551da177e4SLinus Torvalds #define SPCS_WORD_LENGTH_18 0x00000004 /* Word Length 18 bit */ 2561da177e4SLinus Torvalds #define SPCS_WORD_LENGTH_19 0x00000002 /* Word Length 19 bit */ 2571da177e4SLinus Torvalds #define SPCS_WORD_LENGTH_20A 0x0000000a /* Word Length 20 bit */ 2581da177e4SLinus Torvalds #define SPCS_WORD_LENGTH_20 0x00000009 /* Word Length 20 bit (both 0xa and 0x9 are 20 bit) */ 2591da177e4SLinus Torvalds #define SPCS_WORD_LENGTH_21 0x00000007 /* Word Length 21 bit */ 2601da177e4SLinus Torvalds #define SPCS_WORD_LENGTH_22 0x00000005 /* Word Length 22 bit */ 2611da177e4SLinus Torvalds #define SPCS_WORD_LENGTH_23 0x00000003 /* Word Length 23 bit */ 2621da177e4SLinus Torvalds #define SPCS_WORD_LENGTH_24 0x0000000b /* Word Length 24 bit */ 2631da177e4SLinus Torvalds #define SPCS_ORIGINAL_SAMPLE_RATE_MASK 0x000000f0 /* Original Sample rate */ 2641da177e4SLinus Torvalds #define SPCS_ORIGINAL_SAMPLE_RATE_NONE 0x00000000 /* Original Sample rate not indicated */ 2651da177e4SLinus Torvalds #define SPCS_ORIGINAL_SAMPLE_RATE_16000 0x00000010 /* Original Sample rate */ 2661da177e4SLinus Torvalds #define SPCS_ORIGINAL_SAMPLE_RATE_RES1 0x00000020 /* Original Sample rate */ 2671da177e4SLinus Torvalds #define SPCS_ORIGINAL_SAMPLE_RATE_32000 0x00000030 /* Original Sample rate */ 2681da177e4SLinus Torvalds #define SPCS_ORIGINAL_SAMPLE_RATE_12000 0x00000040 /* Original Sample rate */ 2691da177e4SLinus Torvalds #define SPCS_ORIGINAL_SAMPLE_RATE_11025 0x00000050 /* Original Sample rate */ 2701da177e4SLinus Torvalds #define SPCS_ORIGINAL_SAMPLE_RATE_8000 0x00000060 /* Original Sample rate */ 2711da177e4SLinus Torvalds #define SPCS_ORIGINAL_SAMPLE_RATE_RES2 0x00000070 /* Original Sample rate */ 2721da177e4SLinus Torvalds #define SPCS_ORIGINAL_SAMPLE_RATE_192000 0x00000080 /* Original Sample rate */ 2731da177e4SLinus Torvalds #define SPCS_ORIGINAL_SAMPLE_RATE_24000 0x00000090 /* Original Sample rate */ 2741da177e4SLinus Torvalds #define SPCS_ORIGINAL_SAMPLE_RATE_96000 0x000000a0 /* Original Sample rate */ 2751da177e4SLinus Torvalds #define SPCS_ORIGINAL_SAMPLE_RATE_48000 0x000000b0 /* Original Sample rate */ 2761da177e4SLinus Torvalds #define SPCS_ORIGINAL_SAMPLE_RATE_176400 0x000000c0 /* Original Sample rate */ 2771da177e4SLinus Torvalds #define SPCS_ORIGINAL_SAMPLE_RATE_22050 0x000000d0 /* Original Sample rate */ 2781da177e4SLinus Torvalds #define SPCS_ORIGINAL_SAMPLE_RATE_88200 0x000000e0 /* Original Sample rate */ 2791da177e4SLinus Torvalds #define SPCS_ORIGINAL_SAMPLE_RATE_44100 0x000000f0 /* Original Sample rate */ 2801da177e4SLinus Torvalds 2811da177e4SLinus Torvalds #define SPDIF_SELECT1 0x45 /* Enables SPDIF or Analogue outputs 0-SPDIF, 0xf00-Analogue */ 2821da177e4SLinus Torvalds /* 0x100 - Front, 0x800 - Rear, 0x200 - Center/LFE. 2831da177e4SLinus Torvalds * But as the jack is shared, use 0xf00. 2841da177e4SLinus Torvalds * The Windows2000 driver uses 0x0000000f for both digital and analog. 2851da177e4SLinus Torvalds * 0xf00 introduces interesting noises onto the Center/LFE. 2861da177e4SLinus Torvalds * If you turn the volume up, you hear computer noise, 2871da177e4SLinus Torvalds * e.g. mouse moving, changing between app windows etc. 2881da177e4SLinus Torvalds * So, I am going to set this to 0x0000000f all the time now, 2891da177e4SLinus Torvalds * same as the windows driver does. 2901da177e4SLinus Torvalds * Use register SPDIF_SELECT2(0x72) to switch between SPDIF and Analog. 2911da177e4SLinus Torvalds */ 2921da177e4SLinus Torvalds /* When Channel = 0: 2931da177e4SLinus Torvalds * Wide SPDIF format [3:0] (one bit for each channel) (0=20bit, 1=24bit) 2941da177e4SLinus Torvalds * Tristate SPDIF Output [11:8] (one bit for each channel) (0=Not tristate, 1=Tristate) 2951da177e4SLinus Torvalds * SPDIF Bypass enable [19:16] (one bit for each channel) (0=Not bypass, 1=Bypass) 2961da177e4SLinus Torvalds */ 2971da177e4SLinus Torvalds /* When Channel = 1: 2981da177e4SLinus Torvalds * SPDIF 0 User data [7:0] 2991da177e4SLinus Torvalds * SPDIF 1 User data [15:8] 3001da177e4SLinus Torvalds * SPDIF 0 User data [23:16] 3011da177e4SLinus Torvalds * SPDIF 0 User data [31:24] 3021da177e4SLinus Torvalds * User data can be sent by using the SPDIF output frame pending and SPDIF output user bit interrupts. 3031da177e4SLinus Torvalds */ 3041da177e4SLinus Torvalds #define WATERMARK 0x46 /* Test bit to indicate cache usage level */ 3051da177e4SLinus Torvalds #define SPDIF_INPUT_STATUS 0x49 /* SPDIF Input status register. Bits the same as SPCS. 3061da177e4SLinus Torvalds * When Channel = 0: Bits the same as SPCS channel 0. 3071da177e4SLinus Torvalds * When Channel = 1: Bits the same as SPCS channel 1. 3081da177e4SLinus Torvalds * When Channel = 2: 3091da177e4SLinus Torvalds * SPDIF Input User data [16:0] 3101da177e4SLinus Torvalds * SPDIF Input Frame count [21:16] 3111da177e4SLinus Torvalds */ 3121da177e4SLinus Torvalds #define CAPTURE_CACHE_DATA 0x50 /* 0x50-0x5f Recorded samples. */ 3131da177e4SLinus Torvalds #define CAPTURE_SOURCE 0x60 /* Capture Source 0 = MIC */ 3141da177e4SLinus Torvalds #define CAPTURE_SOURCE_CHANNEL0 0xf0000000 /* Mask for selecting the Capture sources */ 3151da177e4SLinus Torvalds #define CAPTURE_SOURCE_CHANNEL1 0x0f000000 /* 0 - SPDIF mixer output. */ 3161da177e4SLinus Torvalds #define CAPTURE_SOURCE_CHANNEL2 0x00f00000 /* 1 - What you hear or . 2 - ?? */ 3171da177e4SLinus Torvalds #define CAPTURE_SOURCE_CHANNEL3 0x000f0000 /* 3 - Mic in, Line in, TAD in, Aux in. */ 3181da177e4SLinus Torvalds #define CAPTURE_SOURCE_RECORD_MAP 0x0000ffff /* Default 0x00e4 */ 3191da177e4SLinus Torvalds /* Record Map [7:0] (2 bits per channel) 0=mapped to channel 0, 1=mapped to channel 1, 2=mapped to channel2, 3=mapped to channel3 3201da177e4SLinus Torvalds * Record source select for channel 0 [18:16] 3211da177e4SLinus Torvalds * Record source select for channel 1 [22:20] 3221da177e4SLinus Torvalds * Record source select for channel 2 [26:24] 3231da177e4SLinus Torvalds * Record source select for channel 3 [30:28] 3241da177e4SLinus Torvalds * 0 - SPDIF mixer output. 3251da177e4SLinus Torvalds * 1 - i2s mixer output. 3261da177e4SLinus Torvalds * 2 - SPDIF input. 3271da177e4SLinus Torvalds * 3 - i2s input. 3281da177e4SLinus Torvalds * 4 - AC97 capture. 3291da177e4SLinus Torvalds * 5 - SRC output. 3301da177e4SLinus Torvalds */ 3311da177e4SLinus Torvalds #define CAPTURE_VOLUME1 0x61 /* Capture volume per channel 0-3 */ 3321da177e4SLinus Torvalds #define CAPTURE_VOLUME2 0x62 /* Capture volume per channel 4-7 */ 3331da177e4SLinus Torvalds 3341da177e4SLinus Torvalds #define PLAYBACK_ROUTING1 0x63 /* Playback routing of channels 0-7. Effects AC3 output. Default 0x32765410 */ 3351da177e4SLinus Torvalds #define ROUTING1_REAR 0x77000000 /* Channel_id 0 sends to 10, Channel_id 1 sends to 32 */ 3361da177e4SLinus Torvalds #define ROUTING1_NULL 0x00770000 /* Channel_id 2 sends to 54, Channel_id 3 sends to 76 */ 3371da177e4SLinus Torvalds #define ROUTING1_CENTER_LFE 0x00007700 /* 0x32765410 means, send Channel_id 0 to FRONT, Channel_id 1 to REAR */ 3381da177e4SLinus Torvalds #define ROUTING1_FRONT 0x00000077 /* Channel_id 2 to CENTER_LFE, Channel_id 3 to NULL. */ 3391da177e4SLinus Torvalds /* Channel_id's handle stereo channels. Channel X is a single mono channel */ 3401da177e4SLinus Torvalds /* Host is input from the PCI bus. */ 3411da177e4SLinus Torvalds /* Host channel 0 [2:0] -> SPDIF Mixer/Router channel 0-7. 3421da177e4SLinus Torvalds * Host channel 1 [6:4] -> SPDIF Mixer/Router channel 0-7. 3431da177e4SLinus Torvalds * Host channel 2 [10:8] -> SPDIF Mixer/Router channel 0-7. 3441da177e4SLinus Torvalds * Host channel 3 [14:12] -> SPDIF Mixer/Router channel 0-7. 3451da177e4SLinus Torvalds * Host channel 4 [18:16] -> SPDIF Mixer/Router channel 0-7. 3461da177e4SLinus Torvalds * Host channel 5 [22:20] -> SPDIF Mixer/Router channel 0-7. 3471da177e4SLinus Torvalds * Host channel 6 [26:24] -> SPDIF Mixer/Router channel 0-7. 3481da177e4SLinus Torvalds * Host channel 7 [30:28] -> SPDIF Mixer/Router channel 0-7. 3491da177e4SLinus Torvalds */ 3501da177e4SLinus Torvalds 3511da177e4SLinus Torvalds #define PLAYBACK_ROUTING2 0x64 /* Playback Routing . Feeding Capture channels back into Playback. Effects AC3 output. Default 0x76767676 */ 3521da177e4SLinus Torvalds /* SRC is input from the capture inputs. */ 3531da177e4SLinus Torvalds /* SRC channel 0 [2:0] -> SPDIF Mixer/Router channel 0-7. 3541da177e4SLinus Torvalds * SRC channel 1 [6:4] -> SPDIF Mixer/Router channel 0-7. 3551da177e4SLinus Torvalds * SRC channel 2 [10:8] -> SPDIF Mixer/Router channel 0-7. 3561da177e4SLinus Torvalds * SRC channel 3 [14:12] -> SPDIF Mixer/Router channel 0-7. 3571da177e4SLinus Torvalds * SRC channel 4 [18:16] -> SPDIF Mixer/Router channel 0-7. 3581da177e4SLinus Torvalds * SRC channel 5 [22:20] -> SPDIF Mixer/Router channel 0-7. 3591da177e4SLinus Torvalds * SRC channel 6 [26:24] -> SPDIF Mixer/Router channel 0-7. 3601da177e4SLinus Torvalds * SRC channel 7 [30:28] -> SPDIF Mixer/Router channel 0-7. 3611da177e4SLinus Torvalds */ 3621da177e4SLinus Torvalds 3631da177e4SLinus Torvalds #define PLAYBACK_MUTE 0x65 /* Unknown. While playing 0x0, while silent 0x00fc0000 */ 3641da177e4SLinus Torvalds /* SPDIF Mixer input control: 3651da177e4SLinus Torvalds * Invert SRC to SPDIF Mixer [7-0] (One bit per channel) 3661da177e4SLinus Torvalds * Invert Host to SPDIF Mixer [15:8] (One bit per channel) 3671da177e4SLinus Torvalds * SRC to SPDIF Mixer disable [23:16] (One bit per channel) 3681da177e4SLinus Torvalds * Host to SPDIF Mixer disable [31:24] (One bit per channel) 3691da177e4SLinus Torvalds */ 3701da177e4SLinus Torvalds #define PLAYBACK_VOLUME1 0x66 /* Playback SPDIF volume per channel. Set to the same PLAYBACK_VOLUME(0x6a) */ 3711da177e4SLinus Torvalds /* PLAYBACK_VOLUME1 must be set to 30303030 for SPDIF AC3 Playback */ 3721da177e4SLinus Torvalds /* SPDIF mixer input volume. 0=12dB, 0x30=0dB, 0xFE=-51.5dB, 0xff=Mute */ 3731da177e4SLinus Torvalds /* One register for each of the 4 stereo streams. */ 3741da177e4SLinus Torvalds /* SRC Right volume [7:0] 3751da177e4SLinus Torvalds * SRC Left volume [15:8] 3761da177e4SLinus Torvalds * Host Right volume [23:16] 3771da177e4SLinus Torvalds * Host Left volume [31:24] 3781da177e4SLinus Torvalds */ 3791da177e4SLinus Torvalds #define CAPTURE_ROUTING1 0x67 /* Capture Routing. Default 0x32765410 */ 3801da177e4SLinus Torvalds /* Similar to register 0x63, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */ 3811da177e4SLinus Torvalds #define CAPTURE_ROUTING2 0x68 /* Unknown Routing. Default 0x76767676 */ 3821da177e4SLinus Torvalds /* Similar to register 0x64, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */ 3831da177e4SLinus Torvalds #define CAPTURE_MUTE 0x69 /* Unknown. While capturing 0x0, while silent 0x00fc0000 */ 3841da177e4SLinus Torvalds /* Similar to register 0x65, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */ 3851da177e4SLinus Torvalds #define PLAYBACK_VOLUME2 0x6a /* Playback Analog volume per channel. Does not effect AC3 output */ 3861da177e4SLinus Torvalds /* Similar to register 0x66, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */ 3871da177e4SLinus Torvalds #define UNKNOWN6b 0x6b /* Unknown. Readonly. Default 00400000 00400000 00400000 00400000 */ 3888a5afd29SJames Courtier-Dutton #define MIDI_UART_A_DATA 0x6c /* Midi Uart A Data */ 3898a5afd29SJames Courtier-Dutton #define MIDI_UART_A_CMD 0x6d /* Midi Uart A Command/Status */ 3908a5afd29SJames Courtier-Dutton #define MIDI_UART_B_DATA 0x6e /* Midi Uart B Data (currently unused) */ 3918a5afd29SJames Courtier-Dutton #define MIDI_UART_B_CMD 0x6f /* Midi Uart B Command/Status (currently unused) */ 3928a5afd29SJames Courtier-Dutton 3938a5afd29SJames Courtier-Dutton /* unique channel identifier for midi->channel */ 3948a5afd29SJames Courtier-Dutton 3958a5afd29SJames Courtier-Dutton #define CA0106_MIDI_CHAN_A 0x1 3968a5afd29SJames Courtier-Dutton #define CA0106_MIDI_CHAN_B 0x2 3978a5afd29SJames Courtier-Dutton 3988a5afd29SJames Courtier-Dutton /* from mpu401 */ 3998a5afd29SJames Courtier-Dutton 4008a5afd29SJames Courtier-Dutton #define CA0106_MIDI_INPUT_AVAIL 0x80 4018a5afd29SJames Courtier-Dutton #define CA0106_MIDI_OUTPUT_READY 0x40 4028a5afd29SJames Courtier-Dutton #define CA0106_MPU401_RESET 0xff 4038a5afd29SJames Courtier-Dutton #define CA0106_MPU401_ENTER_UART 0x3f 4048a5afd29SJames Courtier-Dutton #define CA0106_MPU401_ACK 0xfe 4058a5afd29SJames Courtier-Dutton 4061da177e4SLinus Torvalds #define SAMPLE_RATE_TRACKER_STATUS 0x70 /* Readonly. Default 00108000 00108000 00500000 00500000 */ 4071da177e4SLinus Torvalds /* Estimated sample rate [19:0] Relative to 48kHz. 0x8000 = 1.0 4081da177e4SLinus Torvalds * Rate Locked [20] 4091da177e4SLinus Torvalds * SPDIF Locked [21] For SPDIF channel only. 4101da177e4SLinus Torvalds * Valid Audio [22] For SPDIF channel only. 4111da177e4SLinus Torvalds */ 4121da177e4SLinus Torvalds #define CAPTURE_CONTROL 0x71 /* Some sort of routing. default = 40c81000 30303030 30300000 00700000 */ 4131da177e4SLinus Torvalds /* Channel_id 0: 0x40c81000 must be changed to 0x40c80000 for SPDIF AC3 input or output. */ 4141da177e4SLinus Torvalds /* Channel_id 1: 0xffffffff(mute) 0x30303030(max) controls CAPTURE feedback into PLAYBACK. */ 4151da177e4SLinus Torvalds /* Sample rate output control register Channel=0 4161da177e4SLinus Torvalds * Sample output rate [1:0] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz) 4171da177e4SLinus Torvalds * Sample input rate [3:2] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz) 4181da177e4SLinus Torvalds * SRC input source select [4] 0=Audio from digital mixer, 1=Audio from analog source. 4191da177e4SLinus Torvalds * Record rate [9:8] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz) 4201da177e4SLinus Torvalds * Record mixer output enable [12:10] 4211da177e4SLinus Torvalds * I2S input rate master mode [15:14] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz) 4221da177e4SLinus Torvalds * I2S output rate [17:16] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz) 4231da177e4SLinus Torvalds * I2S output source select [18] (0=Audio from host, 1=Audio from SRC) 4241da177e4SLinus Torvalds * Record mixer I2S enable [20:19] (enable/disable i2sin1 and i2sin0) 4251da177e4SLinus Torvalds * I2S output master clock select [21] (0=256*I2S output rate, 1=512*I2S output rate.) 4261da177e4SLinus Torvalds * I2S input master clock select [22] (0=256*I2S input rate, 1=512*I2S input rate.) 4271da177e4SLinus Torvalds * I2S input mode [23] (0=Slave, 1=Master) 4281da177e4SLinus Torvalds * SPDIF output rate [25:24] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz) 4291da177e4SLinus Torvalds * SPDIF output source select [26] (0=host, 1=SRC) 4301da177e4SLinus Torvalds * Not used [27] 4311da177e4SLinus Torvalds * Record Source 0 input [29:28] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM) 4321da177e4SLinus Torvalds * Record Source 1 input [31:30] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM) 4331da177e4SLinus Torvalds */ 4341da177e4SLinus Torvalds /* Sample rate output control register Channel=1 4351da177e4SLinus Torvalds * I2S Input 0 volume Right [7:0] 4361da177e4SLinus Torvalds * I2S Input 0 volume Left [15:8] 4371da177e4SLinus Torvalds * I2S Input 1 volume Right [23:16] 4381da177e4SLinus Torvalds * I2S Input 1 volume Left [31:24] 4391da177e4SLinus Torvalds */ 4401da177e4SLinus Torvalds /* Sample rate output control register Channel=2 4411da177e4SLinus Torvalds * SPDIF Input volume Right [23:16] 4421da177e4SLinus Torvalds * SPDIF Input volume Left [31:24] 4431da177e4SLinus Torvalds */ 4441da177e4SLinus Torvalds /* Sample rate output control register Channel=3 4451da177e4SLinus Torvalds * No used 4461da177e4SLinus Torvalds */ 4471da177e4SLinus Torvalds #define SPDIF_SELECT2 0x72 /* Some sort of routing. Channel_id 0 only. default = 0x0f0f003f. Analog 0x000b0000, Digital 0x0b000000 */ 4481da177e4SLinus Torvalds #define ROUTING2_FRONT_MASK 0x00010000 /* Enable for Front speakers. */ 4491da177e4SLinus Torvalds #define ROUTING2_CENTER_LFE_MASK 0x00020000 /* Enable for Center/LFE speakers. */ 4501da177e4SLinus Torvalds #define ROUTING2_REAR_MASK 0x00080000 /* Enable for Rear speakers. */ 4511da177e4SLinus Torvalds /* Audio output control 4521da177e4SLinus Torvalds * AC97 output enable [5:0] 4531da177e4SLinus Torvalds * I2S output enable [19:16] 4541da177e4SLinus Torvalds * SPDIF output enable [27:24] 4551da177e4SLinus Torvalds */ 4561da177e4SLinus Torvalds #define UNKNOWN73 0x73 /* Unknown. Readonly. Default 0x0 */ 4571da177e4SLinus Torvalds #define CHIP_VERSION 0x74 /* P17 Chip version. Channel_id 0 only. Default 00000071 */ 4581da177e4SLinus Torvalds #define EXTENDED_INT_MASK 0x75 /* Used by both playback and capture interrupt handler */ 4591da177e4SLinus Torvalds /* Sets which Interrupts are enabled. */ 4601da177e4SLinus Torvalds /* 0x00000001 = Half period. Playback. 4611da177e4SLinus Torvalds * 0x00000010 = Full period. Playback. 4621da177e4SLinus Torvalds * 0x00000100 = Half buffer. Playback. 4631da177e4SLinus Torvalds * 0x00001000 = Full buffer. Playback. 4641da177e4SLinus Torvalds * 0x00010000 = Half buffer. Capture. 4651da177e4SLinus Torvalds * 0x00100000 = Full buffer. Capture. 4661da177e4SLinus Torvalds * Capture can only do 2 periods. 4671da177e4SLinus Torvalds * 0x01000000 = End audio. Playback. 4681da177e4SLinus Torvalds * 0x40000000 = Half buffer Playback,Caputre xrun. 4691da177e4SLinus Torvalds * 0x80000000 = Full buffer Playback,Caputre xrun. 4701da177e4SLinus Torvalds */ 4711da177e4SLinus Torvalds #define EXTENDED_INT 0x76 /* Used by both playback and capture interrupt handler */ 4721da177e4SLinus Torvalds /* Shows which interrupts are active at the moment. */ 4731da177e4SLinus Torvalds /* Same bit layout as EXTENDED_INT_MASK */ 4741da177e4SLinus Torvalds #define COUNTER77 0x77 /* Counter range 0 to 0x3fffff, 192000 counts per second. */ 4751da177e4SLinus Torvalds #define COUNTER78 0x78 /* Counter range 0 to 0x3fffff, 44100 counts per second. */ 4761da177e4SLinus Torvalds #define EXTENDED_INT_TIMER 0x79 /* Channel_id 0 only. Used by both playback and capture interrupt handler */ 4771da177e4SLinus Torvalds /* Causes interrupts based on timer intervals. */ 4781da177e4SLinus Torvalds #define SPI 0x7a /* SPI: Serial Interface Register */ 4791da177e4SLinus Torvalds #define I2C_A 0x7b /* I2C Address. 32 bit */ 4807199acdcSJames Courtier-Dutton #define I2C_D0 0x7c /* I2C Data Port 0. 32 bit */ 4817199acdcSJames Courtier-Dutton #define I2C_D1 0x7d /* I2C Data Port 1. 32 bit */ 4827199acdcSJames Courtier-Dutton //I2C values 4837199acdcSJames Courtier-Dutton #define I2C_A_ADC_ADD_MASK 0x000000fe //The address is a 7 bit address 4847199acdcSJames Courtier-Dutton #define I2C_A_ADC_RW_MASK 0x00000001 //bit mask for R/W 4857199acdcSJames Courtier-Dutton #define I2C_A_ADC_TRANS_MASK 0x00000010 //Bit mask for I2c address DAC value 4867199acdcSJames Courtier-Dutton #define I2C_A_ADC_ABORT_MASK 0x00000020 //Bit mask for I2C transaction abort flag 4877199acdcSJames Courtier-Dutton #define I2C_A_ADC_LAST_MASK 0x00000040 //Bit mask for Last word transaction 4887199acdcSJames Courtier-Dutton #define I2C_A_ADC_BYTE_MASK 0x00000080 //Bit mask for Byte Mode 4891da177e4SLinus Torvalds 4907199acdcSJames Courtier-Dutton #define I2C_A_ADC_ADD 0x00000034 //This is the Device address for ADC 4917199acdcSJames Courtier-Dutton #define I2C_A_ADC_READ 0x00000001 //To perform a read operation 4927199acdcSJames Courtier-Dutton #define I2C_A_ADC_START 0x00000100 //Start I2C transaction 4937199acdcSJames Courtier-Dutton #define I2C_A_ADC_ABORT 0x00000200 //I2C transaction abort 4947199acdcSJames Courtier-Dutton #define I2C_A_ADC_LAST 0x00000400 //I2C last transaction 4957199acdcSJames Courtier-Dutton #define I2C_A_ADC_BYTE 0x00000800 //I2C one byte mode 4967199acdcSJames Courtier-Dutton 4977199acdcSJames Courtier-Dutton #define I2C_D_ADC_REG_MASK 0xfe000000 //ADC address register 4987199acdcSJames Courtier-Dutton #define I2C_D_ADC_DAT_MASK 0x01ff0000 //ADC data register 4997199acdcSJames Courtier-Dutton 5007199acdcSJames Courtier-Dutton #define ADC_TIMEOUT 0x00000007 //ADC Timeout Clock Disable 5017199acdcSJames Courtier-Dutton #define ADC_IFC_CTRL 0x0000000b //ADC Interface Control 5027199acdcSJames Courtier-Dutton #define ADC_MASTER 0x0000000c //ADC Master Mode Control 5037199acdcSJames Courtier-Dutton #define ADC_POWER 0x0000000d //ADC PowerDown Control 5047199acdcSJames Courtier-Dutton #define ADC_ATTEN_ADCL 0x0000000e //ADC Attenuation ADCL 5057199acdcSJames Courtier-Dutton #define ADC_ATTEN_ADCR 0x0000000f //ADC Attenuation ADCR 5067199acdcSJames Courtier-Dutton #define ADC_ALC_CTRL1 0x00000010 //ADC ALC Control 1 5077199acdcSJames Courtier-Dutton #define ADC_ALC_CTRL2 0x00000011 //ADC ALC Control 2 5087199acdcSJames Courtier-Dutton #define ADC_ALC_CTRL3 0x00000012 //ADC ALC Control 3 5097199acdcSJames Courtier-Dutton #define ADC_NOISE_CTRL 0x00000013 //ADC Noise Gate Control 5107199acdcSJames Courtier-Dutton #define ADC_LIMIT_CTRL 0x00000014 //ADC Limiter Control 5117199acdcSJames Courtier-Dutton #define ADC_MUX 0x00000015 //ADC Mux offset 5127199acdcSJames Courtier-Dutton 5137199acdcSJames Courtier-Dutton #if 0 5147199acdcSJames Courtier-Dutton /* FIXME: Not tested yet. */ 5157199acdcSJames Courtier-Dutton #define ADC_GAIN_MASK 0x000000ff //Mask for ADC Gain 5167199acdcSJames Courtier-Dutton #define ADC_ZERODB 0x000000cf //Value to set ADC to 0dB 5177199acdcSJames Courtier-Dutton #define ADC_MUTE_MASK 0x000000c0 //Mask for ADC mute 5187199acdcSJames Courtier-Dutton #define ADC_MUTE 0x000000c0 //Value to mute ADC 5197199acdcSJames Courtier-Dutton #define ADC_OSR 0x00000008 //Mask for ADC oversample rate select 5207199acdcSJames Courtier-Dutton #define ADC_TIMEOUT_DISABLE 0x00000008 //Value and mask to disable Timeout clock 5217199acdcSJames Courtier-Dutton #define ADC_HPF_DISABLE 0x00000100 //Value and mask to disable High pass filter 5227199acdcSJames Courtier-Dutton #define ADC_TRANWIN_MASK 0x00000070 //Mask for Length of Transient Window 5237199acdcSJames Courtier-Dutton #endif 5247199acdcSJames Courtier-Dutton 5257199acdcSJames Courtier-Dutton #define ADC_MUX_MASK 0x0000000f //Mask for ADC Mux 5266129daaaSJames Courtier-Dutton #define ADC_MUX_PHONE 0x00000001 //Value to select TAD at ADC Mux (Not used) 5277199acdcSJames Courtier-Dutton #define ADC_MUX_MIC 0x00000002 //Value to select Mic at ADC Mux 5287199acdcSJames Courtier-Dutton #define ADC_MUX_LINEIN 0x00000004 //Value to select LineIn at ADC Mux 5297199acdcSJames Courtier-Dutton #define ADC_MUX_AUX 0x00000008 //Value to select Aux at ADC Mux 5301da177e4SLinus Torvalds 5311da177e4SLinus Torvalds #define SET_CHANNEL 0 /* Testing channel outputs 0=Front, 1=Center/LFE, 2=Unknown, 3=Rear */ 5321da177e4SLinus Torvalds #define PCM_FRONT_CHANNEL 0 5331da177e4SLinus Torvalds #define PCM_REAR_CHANNEL 1 5341da177e4SLinus Torvalds #define PCM_CENTER_LFE_CHANNEL 2 5351da177e4SLinus Torvalds #define PCM_UNKNOWN_CHANNEL 3 5361da177e4SLinus Torvalds #define CONTROL_FRONT_CHANNEL 0 5371da177e4SLinus Torvalds #define CONTROL_REAR_CHANNEL 3 5381da177e4SLinus Torvalds #define CONTROL_CENTER_LFE_CHANNEL 1 5391da177e4SLinus Torvalds #define CONTROL_UNKNOWN_CHANNEL 2 5401da177e4SLinus Torvalds 541b18cd538STrent Piepho 542b18cd538STrent Piepho /* Based on WM8768 Datasheet Rev 4.2 page 32 */ 543b18cd538STrent Piepho #define SPI_REG_MASK 0x1ff /* 16-bit SPI writes have a 7-bit address */ 544b18cd538STrent Piepho #define SPI_REG_SHIFT 9 /* followed by 9 bits of data */ 545b18cd538STrent Piepho 54618b5d32fSTrent Piepho #define SPI_LDA1_REG 0 /* digital attenuation */ 54718b5d32fSTrent Piepho #define SPI_RDA1_REG 1 54818b5d32fSTrent Piepho #define SPI_LDA2_REG 4 54918b5d32fSTrent Piepho #define SPI_RDA2_REG 5 55018b5d32fSTrent Piepho #define SPI_LDA3_REG 6 55118b5d32fSTrent Piepho #define SPI_RDA3_REG 7 55218b5d32fSTrent Piepho #define SPI_LDA4_REG 13 55318b5d32fSTrent Piepho #define SPI_RDA4_REG 14 55418b5d32fSTrent Piepho #define SPI_MASTDA_REG 8 55518b5d32fSTrent Piepho 55618b5d32fSTrent Piepho #define SPI_DA_BIT_UPDATE (1<<8) /* update attenuation values */ 55718b5d32fSTrent Piepho #define SPI_DA_BIT_0dB 0xff /* 0 dB */ 55818b5d32fSTrent Piepho #define SPI_DA_BIT_infdB 0x00 /* inf dB attenuation (mute) */ 55918b5d32fSTrent Piepho 56018b5d32fSTrent Piepho #define SPI_PL_REG 2 56118b5d32fSTrent Piepho #define SPI_PL_BIT_L_M (0<<5) /* left channel = mute */ 56218b5d32fSTrent Piepho #define SPI_PL_BIT_L_L (1<<5) /* left channel = left */ 56318b5d32fSTrent Piepho #define SPI_PL_BIT_L_R (2<<5) /* left channel = right */ 56418b5d32fSTrent Piepho #define SPI_PL_BIT_L_C (3<<5) /* left channel = (L+R)/2 */ 56518b5d32fSTrent Piepho #define SPI_PL_BIT_R_M (0<<7) /* right channel = mute */ 56618b5d32fSTrent Piepho #define SPI_PL_BIT_R_L (1<<7) /* right channel = left */ 56718b5d32fSTrent Piepho #define SPI_PL_BIT_R_R (2<<7) /* right channel = right */ 56818b5d32fSTrent Piepho #define SPI_PL_BIT_R_C (3<<7) /* right channel = (L+R)/2 */ 56918b5d32fSTrent Piepho #define SPI_IZD_REG 2 570ac237c28SAlex Stanoev #define SPI_IZD_BIT (0<<4) /* infinite zero detect */ 57118b5d32fSTrent Piepho 57218b5d32fSTrent Piepho #define SPI_FMT_REG 3 57318b5d32fSTrent Piepho #define SPI_FMT_BIT_RJ (0<<0) /* right justified mode */ 57418b5d32fSTrent Piepho #define SPI_FMT_BIT_LJ (1<<0) /* left justified mode */ 57518b5d32fSTrent Piepho #define SPI_FMT_BIT_I2S (2<<0) /* I2S mode */ 57618b5d32fSTrent Piepho #define SPI_FMT_BIT_DSP (3<<0) /* DSP Modes A or B */ 57718b5d32fSTrent Piepho #define SPI_LRP_REG 3 57818b5d32fSTrent Piepho #define SPI_LRP_BIT (1<<2) /* invert LRCLK polarity */ 57918b5d32fSTrent Piepho #define SPI_BCP_REG 3 58018b5d32fSTrent Piepho #define SPI_BCP_BIT (1<<3) /* invert BCLK polarity */ 58118b5d32fSTrent Piepho #define SPI_IWL_REG 3 58218b5d32fSTrent Piepho #define SPI_IWL_BIT_16 (0<<4) /* 16-bit world length */ 58318b5d32fSTrent Piepho #define SPI_IWL_BIT_20 (1<<4) /* 20-bit world length */ 58418b5d32fSTrent Piepho #define SPI_IWL_BIT_24 (2<<4) /* 24-bit world length */ 58518b5d32fSTrent Piepho #define SPI_IWL_BIT_32 (3<<4) /* 32-bit world length */ 58618b5d32fSTrent Piepho 58718b5d32fSTrent Piepho #define SPI_MS_REG 10 58818b5d32fSTrent Piepho #define SPI_MS_BIT (1<<5) /* master mode */ 58918b5d32fSTrent Piepho #define SPI_RATE_REG 10 /* only applies in master mode */ 59018b5d32fSTrent Piepho #define SPI_RATE_BIT_128 (0<<6) /* MCLK = LRCLK * 128 */ 59118b5d32fSTrent Piepho #define SPI_RATE_BIT_192 (1<<6) 59218b5d32fSTrent Piepho #define SPI_RATE_BIT_256 (2<<6) 59318b5d32fSTrent Piepho #define SPI_RATE_BIT_384 (3<<6) 59418b5d32fSTrent Piepho #define SPI_RATE_BIT_512 (4<<6) 59518b5d32fSTrent Piepho #define SPI_RATE_BIT_768 (5<<6) 59618b5d32fSTrent Piepho 597b18cd538STrent Piepho /* They really do label the bit for the 4th channel "4" and not "3" */ 598b18cd538STrent Piepho #define SPI_DMUTE0_REG 9 599b18cd538STrent Piepho #define SPI_DMUTE1_REG 9 600b18cd538STrent Piepho #define SPI_DMUTE2_REG 9 601b18cd538STrent Piepho #define SPI_DMUTE4_REG 15 60218b5d32fSTrent Piepho #define SPI_DMUTE0_BIT (1<<3) 60318b5d32fSTrent Piepho #define SPI_DMUTE1_BIT (1<<4) 60418b5d32fSTrent Piepho #define SPI_DMUTE2_BIT (1<<5) 60518b5d32fSTrent Piepho #define SPI_DMUTE4_BIT (1<<2) 606b18cd538STrent Piepho 607b18cd538STrent Piepho #define SPI_PHASE0_REG 3 608b18cd538STrent Piepho #define SPI_PHASE1_REG 3 609b18cd538STrent Piepho #define SPI_PHASE2_REG 3 610b18cd538STrent Piepho #define SPI_PHASE4_REG 15 61118b5d32fSTrent Piepho #define SPI_PHASE0_BIT (1<<6) 61218b5d32fSTrent Piepho #define SPI_PHASE1_BIT (1<<7) 61318b5d32fSTrent Piepho #define SPI_PHASE2_BIT (1<<8) 61418b5d32fSTrent Piepho #define SPI_PHASE4_BIT (1<<3) 615b18cd538STrent Piepho 616b18cd538STrent Piepho #define SPI_PDWN_REG 2 /* power down all DACs */ 61718b5d32fSTrent Piepho #define SPI_PDWN_BIT (1<<2) 618b18cd538STrent Piepho #define SPI_DACD0_REG 10 /* power down individual DACs */ 619b18cd538STrent Piepho #define SPI_DACD1_REG 10 620b18cd538STrent Piepho #define SPI_DACD2_REG 10 621b18cd538STrent Piepho #define SPI_DACD4_REG 15 62218b5d32fSTrent Piepho #define SPI_DACD0_BIT (1<<1) 62318b5d32fSTrent Piepho #define SPI_DACD1_BIT (1<<2) 62418b5d32fSTrent Piepho #define SPI_DACD2_BIT (1<<3) 62518b5d32fSTrent Piepho #define SPI_DACD4_BIT (1<<0) /* datasheet error says it's 1 */ 626b18cd538STrent Piepho 627b18cd538STrent Piepho #define SPI_PWRDNALL_REG 10 /* power down everything */ 62818b5d32fSTrent Piepho #define SPI_PWRDNALL_BIT (1<<4) 629b18cd538STrent Piepho 6308a5afd29SJames Courtier-Dutton #include "ca_midi.h" 6318a5afd29SJames Courtier-Dutton 632e4a3d145STakashi Iwai struct snd_ca0106; 6331da177e4SLinus Torvalds 6341da177e4SLinus Torvalds struct snd_ca0106_channel { 635e4a3d145STakashi Iwai struct snd_ca0106 *emu; 6361da177e4SLinus Torvalds int number; 6371da177e4SLinus Torvalds int use; 638e4a3d145STakashi Iwai void (*interrupt)(struct snd_ca0106 *emu, struct snd_ca0106_channel *channel); 639e4a3d145STakashi Iwai struct snd_ca0106_pcm *epcm; 6401da177e4SLinus Torvalds }; 6411da177e4SLinus Torvalds 6421da177e4SLinus Torvalds struct snd_ca0106_pcm { 643e4a3d145STakashi Iwai struct snd_ca0106 *emu; 644e4a3d145STakashi Iwai struct snd_pcm_substream *substream; 6451da177e4SLinus Torvalds int channel_id; 6461da177e4SLinus Torvalds unsigned short running; 6471da177e4SLinus Torvalds }; 6481da177e4SLinus Torvalds 649e4a3d145STakashi Iwai struct snd_ca0106_details { 6501baa705bSJames Courtier-Dutton u32 serial; 6511baa705bSJames Courtier-Dutton char * name; 652f649a714SBen Stanley int ac97; /* ac97 = 0 -> Select MIC, Line in, TAD in, AUX in. 653f649a714SBen Stanley ac97 = 1 -> Default to AC97 in. */ 654f649a714SBen Stanley int gpio_type; /* gpio_type = 1 -> shared mic-in/line-in 655f649a714SBen Stanley gpio_type = 2 -> shared side-out/line-in. */ 656f649a714SBen Stanley int i2c_adc; /* with i2c_adc=1, the driver adds some capture volume 657f649a714SBen Stanley controls, phone, mic, line-in and aux. */ 6586fef153aSAndy Owen u16 spi_dac; /* spi_dac = 0 -> no spi interface for DACs 6596fef153aSAndy Owen spi_dac = 0x<front><rear><center-lfe><side> 6606fef153aSAndy Owen -> specifies DAC id for each channel pair. */ 661e4a3d145STakashi Iwai }; 6621baa705bSJames Courtier-Dutton 6631da177e4SLinus Torvalds // definition of the chip-specific record 6641da177e4SLinus Torvalds struct snd_ca0106 { 665e4a3d145STakashi Iwai struct snd_card *card; 666dc6ffaf8STakashi Iwai const struct snd_ca0106_details *details; 6671da177e4SLinus Torvalds struct pci_dev *pci; 6681da177e4SLinus Torvalds 6691da177e4SLinus Torvalds unsigned long port; 6701da177e4SLinus Torvalds int irq; 6711da177e4SLinus Torvalds 6721da177e4SLinus Torvalds unsigned int serial; /* serial number */ 6731da177e4SLinus Torvalds unsigned short model; /* subsystem id */ 6741da177e4SLinus Torvalds 6751da177e4SLinus Torvalds spinlock_t emu_lock; 6761da177e4SLinus Torvalds 677e4a3d145STakashi Iwai struct snd_ac97 *ac97; 6785da95273STakashi Iwai struct snd_pcm *pcm[4]; 6791da177e4SLinus Torvalds 680e4a3d145STakashi Iwai struct snd_ca0106_channel playback_channels[4]; 681e4a3d145STakashi Iwai struct snd_ca0106_channel capture_channels[4]; 6823d475829STakashi Iwai u32 spdif_bits[4]; /* s/pdif out default setup */ 6833d475829STakashi Iwai u32 spdif_str_bits[4]; /* s/pdif out per-stream setup */ 6841da177e4SLinus Torvalds int spdif_enable; 6851da177e4SLinus Torvalds int capture_source; 6866129daaaSJames Courtier-Dutton int i2c_capture_source; 6876129daaaSJames Courtier-Dutton u8 i2c_capture_volume[4][2]; 688ed144f3cSJames Courtier-Dutton int capture_mic_line_in; 6891da177e4SLinus Torvalds 6901656fa6eSTakashi Iwai struct snd_dma_buffer *buffer; 6918a5afd29SJames Courtier-Dutton 692e4a3d145STakashi Iwai struct snd_ca_midi midi; 693e4a3d145STakashi Iwai struct snd_ca_midi midi2; 694b18cd538STrent Piepho 695b18cd538STrent Piepho u16 spi_dac_reg[16]; 6965da95273STakashi Iwai 697c7561cd8STakashi Iwai #ifdef CONFIG_PM_SLEEP 6985da95273STakashi Iwai #define NUM_SAVED_VOLUMES 9 6995da95273STakashi Iwai unsigned int saved_vol[NUM_SAVED_VOLUMES]; 7005da95273STakashi Iwai #endif 7011da177e4SLinus Torvalds }; 7021da177e4SLinus Torvalds 703e4a3d145STakashi Iwai int snd_ca0106_mixer(struct snd_ca0106 *emu); 704e4a3d145STakashi Iwai int snd_ca0106_proc_init(struct snd_ca0106 * emu); 7051da177e4SLinus Torvalds 706e4a3d145STakashi Iwai unsigned int snd_ca0106_ptr_read(struct snd_ca0106 * emu, 7071da177e4SLinus Torvalds unsigned int reg, 7081da177e4SLinus Torvalds unsigned int chn); 7091da177e4SLinus Torvalds 710e4a3d145STakashi Iwai void snd_ca0106_ptr_write(struct snd_ca0106 *emu, 7111da177e4SLinus Torvalds unsigned int reg, 7121da177e4SLinus Torvalds unsigned int chn, 7131da177e4SLinus Torvalds unsigned int data); 7141da177e4SLinus Torvalds 715e4a3d145STakashi Iwai int snd_ca0106_i2c_write(struct snd_ca0106 *emu, u32 reg, u32 value); 7167199acdcSJames Courtier-Dutton 717b18cd538STrent Piepho int snd_ca0106_spi_write(struct snd_ca0106 * emu, 718b18cd538STrent Piepho unsigned int data); 7195da95273STakashi Iwai 720c7561cd8STakashi Iwai #ifdef CONFIG_PM_SLEEP 7215da95273STakashi Iwai void snd_ca0106_mixer_suspend(struct snd_ca0106 *chip); 7225da95273STakashi Iwai void snd_ca0106_mixer_resume(struct snd_ca0106 *chip); 7235da95273STakashi Iwai #else 7245da95273STakashi Iwai #define snd_ca0106_mixer_suspend(chip) do { } while (0) 7255da95273STakashi Iwai #define snd_ca0106_mixer_resume(chip) do { } while (0) 7265da95273STakashi Iwai #endif 727