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/openbmc/linux/drivers/char/xillybus/
H A Dxillybus_core.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/dma-mapping.h>
52 #define XILLYMSG_OPCODE_RELEASEBUF 1
75 * register_mutex is endpoint-specific, and is held when non-atomic
87 * wr_mutex -> rd_mutex -> register_mutex -> wr_spinlock -> rd_spinlock
96 msg_dir = buf[0] & 1; in malformed_message()
97 msg_channel = (buf[0] >> 1) & 0x7ff; in malformed_message()
99 msg_data = buf[1] & 0xfffffff; in malformed_message()
101 dev_warn(endpoint->dev, in malformed_message()
102 "Malformed message (skipping): opcode=%d, channel=%03x, dir=%d, bufno=%03x, data=%07x\n", in malformed_message()
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/openbmc/linux/drivers/hsi/controllers/
H A Domap_ssi_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
19 # define SSI_AUTOIDLE (1 << 0)
20 # define SSI_SOFTRESET (1 << 1)
22 # define SSI_SIDLEMODE_NO (1 << 3)
23 # define SSI_SIDLEMODE_SMART (1 << 4)
26 # define SSI_MIDLEMODE_NO (1 << 12)
27 # define SSI_MIDLEMODE_SMART (1 << 13)
30 # define SSI_RESETDONE 1
33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
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/openbmc/linux/drivers/media/platform/allegro-dvt/
H A Dallegro-core.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/xlnx-vcu.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-event.h>
29 #include <media/v4l2-ioctl.h>
30 #include <media/v4l2-mem2mem.h>
31 #include <media/videobuf2-dma-contig.h>
32 #include <media/videobuf2-v4l2.h>
34 #include "allegro-mail.h"
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/openbmc/linux/sound/soc/codecs/
H A Dtas5086.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * - implement DAPM and input muxing
9 * - implement modulation limit
10 * - implement non-default PWM start
13 * because the registers are of unequal size, and multi-byte registers
18 * it doesn't matter because the entire map can be accessed as 8-bit
21 * routines have to be open-coded.
58 #define TAS5086_CLOCK_SCLK_RATIO_48 (1 << 1)
59 #define TAS5086_CLOCK_VALID (1 << 0)
66 #define TAS5086_SYS_CONTROL_1 0x03 /* System control register 1 */
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/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/
H A Dnl-All2 # Created from http://radio-tv-nederland.nl/TV 1.251978e-312nderlijst%20Nederland.xls
3 # and http://radio-tv-nederland.nl/dvbt/dvbt-lokaal.html
4 [CHANNEL]
8 CODE_RATE_HP = 1/2
12 GUARD_INTERVAL = 1/4
16 [CHANNEL]
24 GUARD_INTERVAL = 1/4
28 [CHANNEL]
32 CODE_RATE_HP = 1/2
36 GUARD_INTERVAL = 1/4
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H A Dcz-All2 # Created from http://www.ctu.cz/cs/download/plan-vyuziti-radioveho-spektra/rok_2012/pv-p_10-08_201…
4 [CHANNEL]
12 GUARD_INTERVAL = 1/8
16 [CHANNEL]
24 GUARD_INTERVAL = 1/8
28 [CHANNEL]
36 GUARD_INTERVAL = 1/8
40 [CHANNEL]
48 GUARD_INTERVAL = 1/8
52 [CHANNEL]
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H A Dit-All1 # This file lists all frequencies used in Western Europe for DVB-T.
16 ### VHF - Band III ###
18 [CHANNEL]
26 GUARD_INTERVAL = 1/32
31 [CHANNEL]
39 GUARD_INTERVAL = 1/32
44 [CHANNEL]
52 GUARD_INTERVAL = 1/32
57 [CHANNEL]
65 GUARD_INTERVAL = 1/32
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H A Dat-All1 # Austria, all DVB-T transmitters run by ORS
3 # http://www.ors.at/fileadmin/user_upload/downloads/DVB-T_Kanalbezeichnungen_und_Mittenfrequenzen.p…
4 [CHANNEL]
12 GUARD_INTERVAL = 1/4
16 [CHANNEL]
24 GUARD_INTERVAL = 1/4
28 [CHANNEL]
36 GUARD_INTERVAL = 1/4
40 [CHANNEL]
48 GUARD_INTERVAL = 1/4
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H A Dch-Citycable1 # Lausanne - Switzerland (DVB-T on CityCable cable network)
2 [CHANNEL]
10 GUARD_INTERVAL = 1/32
14 [CHANNEL]
22 GUARD_INTERVAL = 1/32
26 [CHANNEL]
34 GUARD_INTERVAL = 1/32
38 [CHANNEL]
46 GUARD_INTERVAL = 1/32
50 [CHANNEL]
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/openbmc/u-boot/board/micronas/vct/
H A Dscc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
12 #define DMA_WRITE 1 /* SCC write DMA */
15 #define DMA_CYCLIC 1 /* DMA cyclic buffer access method */
17 #define DMA_START 0 /* DMA command - start DMA */
18 #define DMA_STOP 1 /* DMA command - stop DMA */
19 #define DMA_START_FH_RESET 2 /* DMA command - start DMA reset FH */
20 #define DMA_TAKEOVER 15 /* DMA command - commit the DMA conf */
23 #define AGU_BYPASS 1 /* set AGU to bypass mode */
26 #define USE_FH 1 /* order the DMA to work with FH*/
31 #define SCC_TO_IMMEDIATE 1 /* takeover command issued immediately*/
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/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddma.txt4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
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/openbmc/linux/drivers/ptp/
H A Dptp_clockmatrix.c1 // SPDX-License-Identifier: GPL-2.0+
27 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
33 * over-rides any automatic selection
41 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm);
49 return regmap_bulk_read(idtcm->regmap, module + regaddr, buf, count); in idtcm_read()
58 return regmap_bulk_write(idtcm->regmap, module + regaddr, buf, count); in idtcm_write()
64 struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data; in contains_full_configuration()
65 u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH); in contains_full_configuration()
73 full_count = (scratch - GPIO_USER_CONTROL) - in contains_full_configuration()
74 ((scratch >> 7) - (GPIO_USER_CONTROL >> 7)) * 4; in contains_full_configuration()
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/openbmc/phosphor-host-ipmid/user_channel/
H A Dchannel_layer.hpp8 // http://www.apache.org/licenses/LICENSE-2.0
36 extern const std::array<std::string, PRIVILEGE_OEM + 1> privList;
39 * @enum Channel Protocol Type (refer spec sec 6.4)
57 * @enum Channel Medium Type (refer spec sec 6.5)
79 * @enum Channel Session Type (refer spec sec 22.24 -
85 single = 1,
91 * @enum Channel Access Mode (refer spec sec 6.6)
96 preboot = 1,
102 * @enum Authentication Types (refer spec sec 13.6 - IPMI
107 none = (1 << 0x0),
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/openbmc/ipmitool/lib/
H A Dipmi_channel.c1 /* -*-mode: C; indent-tabs-mode: t; -*-
22 * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED.
60 /* _ipmi_get_channel_access - Get Channel Access for given channel. Results are
63 * @intf - IPMI interface
64 * @channel_access - ptr to channel_access_t with Channel set.
65 * @get_volatile_settings - get volatile if != 0, else non-volatile settings.
67 * returns - negative number means error, positive is a ccode.
79 return (-3); in _ipmi_get_channel_access()
81 data[0] = channel_access->channel & 0x0F; in _ipmi_get_channel_access()
82 /* volatile - 0x80; non-volatile - 0x40 */ in _ipmi_get_channel_access()
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/openbmc/linux/drivers/iio/adc/
H A Dad7476.c1 // SPDX-License-Identifier: GPL-2.0
4 * TI ADC081S/ADC101S/ADC121S 8/10/12-bit SPI ADC driver
31 struct iio_chan_spec channel[2]; member
80 if (!st->convst_gpio) in ad7091_convst()
83 gpiod_set_value(st->convst_gpio, 0); in ad7091_convst()
84 udelay(1); /* CONVST pulse width: 10 ns min */ in ad7091_convst()
85 gpiod_set_value(st->convst_gpio, 1); in ad7091_convst()
86 udelay(1); /* Conversion time: 650 ns max */ in ad7091_convst()
92 struct iio_dev *indio_dev = pf->indio_dev; in ad7476_trigger_handler()
98 b_sent = spi_sync(st->spi, &st->msg); in ad7476_trigger_handler()
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/openbmc/u-boot/arch/x86/cpu/quark/
H A Dmrc_util.c1 // SPDX-License-Identifier: Intel
58 /* 1000 MHz clock has 1ns period --> no conversion required */ in delay_n()
70 /* 64-bit math is not an option, just use loops */ in delay_u()
71 while (ms--) in delay_u()
116 /* Send DRAM wake command using special MCU side-band WAKE opcode */
126 void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane) in training_message() argument
129 DPF(D_INFO, "CH%01X RK%01X BL%01X\n", channel, rank, byte_lane); in training_message()
137 void set_rcvn(uint8_t channel, uint8_t rank, in set_rcvn() argument
147 channel, rank, byte_lane, pi_count); in set_rcvn()
150 * RDPTR (1/2 MCLK, 64 PIs) in set_rcvn()
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/openbmc/u-boot/include/
H A Dw83c553f.h1 /* SPDX-License-Identifier: GPL-2.0+ */
9 /* from the winbond data sheet -
10 The W83C553F SIO controller with PCI arbiter is a multi-function PCI device.
11 Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller.
34 #define WINBOND_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/
38 #define WINDOND_IDECSR 0x40 /*IDE Control/Status Register, Function 1*/
81 #define W83C553F_DMA1 CONFIG_SYS_ISA_IO + 0x000 /* channel 0 - 3 */
82 #define W83C553F_DMA2 CONFIG_SYS_ISA_IO + 0x0C0 /* channel 4 - 7 */
86 #define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */
87 #define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */
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/openbmc/linux/Documentation/devicetree/bindings/iio/dac/
H A Dadi,ad5770r.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandru Tachici <alexandru.tachici@analog.com>
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD5770R.pdf
21 - adi,ad5770r
24 maxItems: 1
26 avdd-supply:
31 iovdd-supply:
35 vref-supply:
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/openbmc/linux/drivers/dma/sh/
H A Drz-dmac.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on imx-dma.c
9 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
13 #include <linux/dma-mapping.h>
29 #include "../virt-dma.h"
108 * -----------------------------------------------------------------------------
135 #define CHCTRL_CLREN BIT(1)
153 #define CHCFG_FILL_LVL(a) (((a) & BIT(1)) << 5)
159 #define DCTRL_LVINT BIT(1)
171 * -----------------------------------------------------------------------------
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/openbmc/linux/drivers/usb/musb/
H A Dmusbhsdma.c1 // SPDX-License-Identifier: GPL-2.0
3 * MUSB OTG driver - support for Mentor's DMA controller
6 * Copyright (C) 2005-2007 by Texas Instruments
35 /* control register (16-bit): */
37 #define MUSB_HSDMA_TRANSMIT_SHIFT 1
45 #define MUSB_HSDMA_BURSTMODE_INCR4 1
54 struct dma_channel channel; member
66 struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS]; member
74 static void dma_channel_release(struct dma_channel *channel);
78 struct musb *musb = controller->private_data; in dma_controller_stop()
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/openbmc/linux/drivers/firmware/arm_scmi/
H A Doptee.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2021 Linaro Ltd.
23 * PTA_SCMI_CMD_CAPABILITIES - Get channel capabilities
31 * PTA_SCMI_CMD_PROCESS_SMT_CHANNEL - Process SCMI message in SMT buffer
33 * [in] value[0].a: Channel handle
36 * already identified and bound to channel handle in both SCMI agent
37 * and SCMI server (OP-TEE) parts.
38 * The memory uses SMT header to carry SCMI meta-data (protocol ID and
41 PTA_SCMI_CMD_PROCESS_SMT_CHANNEL = 1,
44 * PTA_SCMI_CMD_PROCESS_SMT_CHANNEL_MESSAGE - Process SMT/SCMI message
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/openbmc/u-boot/drivers/dma/
H A Dapbh_dma.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <asm/arch/imx-regs.h>
21 #include <asm/mach-imx/dma.h>
22 #include <asm/mach-imx/regs-apbh.h>
27 * Test is the DMA channel is valid channel
29 int mxs_dma_validate_chan(int channel) in mxs_dma_validate_chan() argument
33 if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) in mxs_dma_validate_chan()
34 return -EINVAL; in mxs_dma_validate_chan()
36 pchan = mxs_dma_channels + channel; in mxs_dma_validate_chan()
37 if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) in mxs_dma_validate_chan()
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/openbmc/linux/drivers/net/ethernet/sfc/
H A Defx_channels.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * 0 => MSI-X
25 * 1 => MSI
30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
62 netif_warn(efx, probe, efx->net_dev, in count_online_cores()
64 return 1; in count_online_cores()
70 cpumask_of_pcibus(efx->pci_dev->bus)); in count_online_cores()
98 netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn, in efx_wanted_parallelism()
108 if (efx->type->sriov_wanted) { in efx_wanted_parallelism()
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/openbmc/linux/drivers/net/ethernet/sfc/siena/
H A Defx_channels.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * 0 => MSI-X
25 * 1 => MSI
30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
62 netif_warn(efx, probe, efx->net_dev, in count_online_cores()
64 return 1; in count_online_cores()
70 cpumask_of_pcibus(efx->pci_dev->bus)); in count_online_cores()
98 netif_cond_dbg(efx, probe, efx->net_dev, !efx_siena_rss_cpus, in efx_wanted_parallelism()
109 if (efx->type->sriov_wanted) { in efx_wanted_parallelism()
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/openbmc/linux/sound/core/oss/
H A Drate.c2 * Rate conversion Plug-In
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #define BITS (1<<SHIFT)
29 #define R_MASK (BITS-1)
55 unsigned int channel; in rate_init() local
56 struct rate_priv *data = (struct rate_priv *)plugin->extra_data; in rate_init()
57 data->pos = 0; in rate_init()
58 for (channel = 0; channel < plugin->src_format.channels; channel++) { in rate_init()
59 data->channels[channel].last_S1 = 0; in rate_init()
60 data->channels[channel].last_S2 = 0; in rate_init()
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