Lines Matching +full:channel +full:- +full:1
1 /* SPDX-License-Identifier: GPL-2.0+ */
12 #define DMA_WRITE 1 /* SCC write DMA */
15 #define DMA_CYCLIC 1 /* DMA cyclic buffer access method */
17 #define DMA_START 0 /* DMA command - start DMA */
18 #define DMA_STOP 1 /* DMA command - stop DMA */
19 #define DMA_START_FH_RESET 2 /* DMA command - start DMA reset FH */
20 #define DMA_TAKEOVER 15 /* DMA command - commit the DMA conf */
23 #define AGU_BYPASS 1 /* set AGU to bypass mode */
26 #define USE_FH 1 /* order the DMA to work with FH*/
31 #define SCC_TO_IMMEDIATE 1 /* takeover command issued immediately*/
35 #define DMA_CMD_SETUP 1
40 #define DMA_STATE_SETUP 1
45 #define STRM_D 1
62 u32 p_mci_id; /* memory channel ID */
94 u32 drs:1; /* DMA Register Set */
105 u32 agu_mode:1; /* AGU Mode */
106 u32 res2:1; /* reserved */
107 u32 fh_mode:1; /* Fifo Handler */
108 u32 buffer_type:1; /* Defines type of mem buffers */
109 u32 mci_cfg_id:1; /* MCI_CFG register selector */
110 u32 packet_cfg_id:1; /* PACKET_CFG register selector */
128 u32 clock_status:1; /* clock on/off */
129 u32 packet_select:1; /* active SCC packet id */
130 u32 enable_status:1; /* enabled [1/0] */
131 u32 active_status:1; /* 1=active 0=reset */
136 * System on Chip Channel ID
139 SCC_NULL = -1, /* illegal SCC identifier */
140 SCC_FE_3DCOMB_WR, /* SCC_FE_3DCOMB Write channel */
141 SCC_FE_3DCOMB_RD, /* SCC_FE_3DCOMB Read channel */
142 SCC_DI_TNR_WR, /* SCC_DI_TNR Write channel */
143 SCC_DI_TNR_FIELD_RD, /* SCC_DI_TNR_FIELD Read channel */
144 SCC_DI_TNR_FRAME_RD, /* SCC_DI_TNR_FRAME Read channel */
145 SCC_DI_MVAL_WR, /* SCC_DI_MVAL Write channel */
146 SCC_DI_MVAL_RD, /* SCC_DI_MVAL Read channel */
147 SCC_RC_FRAME_WR, /* SCC_RC_FRAME Write channel */
148 SCC_RC_FRAME0_RD, /* SCC_RC_FRAME0 Read channel */
149 SCC_OPT_FIELD0_RD, /* SCC_OPT_FIELD0 Read channel */
150 SCC_OPT_FIELD1_RD, /* SCC_OPT_FIELD1 Read channel */
151 SCC_OPT_FIELD2_RD, /* SCC_OPT_FIELD2 Read channel */
152 SCC_PIP_FRAME_WR, /* SCC_PIP_FRAME Write channel */
153 SCC_PIP_FRAME_RD, /* SCC_PIP_FRAME Read channel */
154 SCC_DP_AGPU_RD, /* SCC_DP_AGPU Read channel */
155 SCC_EWARP_RW, /* SCC_EWARP Read/Write channel */
156 SCC_DP_OSD_RD, /* SCC_DP_OSD Read channel */
157 SCC_DP_GRAPHIC_RD, /* SCC_DP_GRAPHIC Read channel */
158 SCC_DVP_OSD_RD, /* SCC_DVP_OSD Read channel */
159 SCC_DVP_VBI_RD, /* SCC_DVP_VBI Read channel */
160 SCC_TSIO_WR, /* SCC_TSIO Write channel */
161 SCC_TSIO_RD, /* SCC_TSIO Read channel */
162 SCC_TSD_WR, /* SCC_TSD Write channel */
163 SCC_VD_UD_ST_RW, /* SCC_VD_UD_ST Read/Write channel */
164 SCC_VD_FRR_RD, /* SCC_VD_FRR Read channel */
165 SCC_VD_FRW_DISP_WR, /* SCC_VD_FRW_DISP Write channel */
166 SCC_MR_VD_M_Y_RD, /* SCC_MR_VD_M_Y Read channel */
167 SCC_MR_VD_M_C_RD, /* SCC_MR_VD_M_C Read channel */
168 SCC_MR_VD_S_Y_RD, /* SCC_MR_VD_S_Y Read channel */
169 SCC_MR_VD_S_C_RD, /* SCC_MR_VD_S_C Read channel */
170 SCC_GA_WR, /* SCC_GA Write channel */
171 SCC_GA_SRC1_RD, /* SCC_GA_SRC1 Read channel */
172 SCC_GA_SRC2_RD, /* SCC_GA_SRC2 Read channel */
173 SCC_AD_RD, /* SCC_AD Read channel */
174 SCC_AD_WR, /* SCC_AD Write channel */
175 SCC_ABP_RD, /* SCC_ABP Read channel */
176 SCC_ABP_WR, /* SCC_ABP Write channel */
177 SCC_EBI_RW, /* SCC_EBI Read/Write channel */
178 SCC_USB_RW, /* SCC_USB Read/Write channel */
179 SCC_CPU1_SPDMA_RW, /* SCC_CPU1_SPDMA Read/Write channel */
180 SCC_CPU1_BRIDGE_RW, /* SCC_CPU1_BRIDGE Read/Write channel */