Lines Matching +full:channel +full:- +full:1
1 // SPDX-License-Identifier: Intel
58 /* 1000 MHz clock has 1ns period --> no conversion required */ in delay_n()
70 /* 64-bit math is not an option, just use loops */ in delay_u()
71 while (ms--) in delay_u()
116 /* Send DRAM wake command using special MCU side-band WAKE opcode */
126 void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane) in training_message() argument
129 DPF(D_INFO, "CH%01X RK%01X BL%01X\n", channel, rank, byte_lane); in training_message()
137 void set_rcvn(uint8_t channel, uint8_t rank, in set_rcvn() argument
147 channel, rank, byte_lane, pi_count); in set_rcvn()
150 * RDPTR (1/2 MCLK, 64 PIs) in set_rcvn()
151 * BL0 -> B01PTRCTL0[11:08] (0x0-0xF) in set_rcvn()
152 * BL1 -> B01PTRCTL0[23:20] (0x0-0xF) in set_rcvn()
154 reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_rcvn()
155 channel * DDRIODQ_CH_OFFSET; in set_rcvn()
156 msk = (byte_lane & 1) ? 0xf00000 : 0xf00; in set_rcvn()
157 temp = (byte_lane & 1) ? (pi_count / HALF_CLK) << 20 : in set_rcvn()
162 pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; in set_rcvn()
165 * PI (1/64 MCLK, 1 PIs) in set_rcvn()
166 * BL0 -> B0DLLPICODER0[29:24] (0x00-0x3F) in set_rcvn()
167 * BL1 -> B1DLLPICODER0[29:24] (0x00-0x3F) in set_rcvn()
169 reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; in set_rcvn()
170 reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_rcvn()
171 channel * DDRIODQ_CH_OFFSET); in set_rcvn()
178 * BL0/1 -> B01DBCTL1[08/11] (+1 select) in set_rcvn()
179 * BL0/1 -> B01DBCTL1[02/05] (enable) in set_rcvn()
181 reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_rcvn()
182 channel * DDRIODQ_CH_OFFSET; in set_rcvn()
187 msk |= (byte_lane & 1) ? (1 << 5) : (1 << 2); in set_rcvn()
192 msk |= (byte_lane & 1) ? (1 << 11) : (1 << 8); in set_rcvn()
200 training_message(channel, rank, byte_lane); in set_rcvn()
209 * channel, rank, byte_lane as an absolute PI count.
213 uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane) in get_rcvn() argument
222 * RDPTR (1/2 MCLK, 64 PIs) in get_rcvn()
223 * BL0 -> B01PTRCTL0[11:08] (0x0-0xF) in get_rcvn()
224 * BL1 -> B01PTRCTL0[23:20] (0x0-0xF) in get_rcvn()
226 reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in get_rcvn()
227 channel * DDRIODQ_CH_OFFSET; in get_rcvn()
229 temp >>= (byte_lane & 1) ? 20 : 8; in get_rcvn()
236 * PI (1/64 MCLK, 1 PIs) in get_rcvn()
237 * BL0 -> B0DLLPICODER0[29:24] (0x00-0x3F) in get_rcvn()
238 * BL1 -> B1DLLPICODER0[29:24] (0x00-0x3F) in get_rcvn()
240 reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; in get_rcvn()
241 reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + in get_rcvn()
242 channel * DDRIODQ_CH_OFFSET); in get_rcvn()
261 void set_rdqs(uint8_t channel, uint8_t rank, in set_rdqs() argument
270 channel, rank, byte_lane, pi_count); in set_rdqs()
273 * PI (1/128 MCLK) in set_rdqs()
274 * BL0 -> B0RXDQSPICODE[06:00] (0x00-0x47) in set_rdqs()
275 * BL1 -> B1RXDQSPICODE[06:00] (0x00-0x47) in set_rdqs()
277 reg = (byte_lane & 1) ? B1RXDQSPICODE : B0RXDQSPICODE; in set_rdqs()
278 reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_rdqs()
279 channel * DDRIODQ_CH_OFFSET); in set_rdqs()
286 training_message(channel, rank, byte_lane); in set_rdqs()
295 * channel, rank, byte_lane as an absolute PI count.
299 uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane) in get_rdqs() argument
308 * PI (1/128 MCLK) in get_rdqs()
309 * BL0 -> B0RXDQSPICODE[06:00] (0x00-0x47) in get_rdqs()
310 * BL1 -> B1RXDQSPICODE[06:00] (0x00-0x47) in get_rdqs()
312 reg = (byte_lane & 1) ? B1RXDQSPICODE : B0RXDQSPICODE; in get_rdqs()
313 reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + in get_rdqs()
314 channel * DDRIODQ_CH_OFFSET); in get_rdqs()
331 void set_wdqs(uint8_t channel, uint8_t rank, in set_wdqs() argument
341 channel, rank, byte_lane, pi_count); in set_wdqs()
344 * RDPTR (1/2 MCLK, 64 PIs) in set_wdqs()
345 * BL0 -> B01PTRCTL0[07:04] (0x0-0xF) in set_wdqs()
346 * BL1 -> B01PTRCTL0[19:16] (0x0-0xF) in set_wdqs()
348 reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_wdqs()
349 channel * DDRIODQ_CH_OFFSET; in set_wdqs()
350 msk = (byte_lane & 1) ? 0xf0000 : 0xf0; in set_wdqs()
352 temp <<= (byte_lane & 1) ? 16 : 4; in set_wdqs()
356 pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; in set_wdqs()
359 * PI (1/64 MCLK, 1 PIs) in set_wdqs()
360 * BL0 -> B0DLLPICODER0[21:16] (0x00-0x3F) in set_wdqs()
361 * BL1 -> B1DLLPICODER0[21:16] (0x00-0x3F) in set_wdqs()
363 reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; in set_wdqs()
364 reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_wdqs()
365 channel * DDRIODQ_CH_OFFSET); in set_wdqs()
372 * BL0/1 -> B01DBCTL1[07/10] (+1 select) in set_wdqs()
373 * BL0/1 -> B01DBCTL1[01/04] (enable) in set_wdqs()
375 reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_wdqs()
376 channel * DDRIODQ_CH_OFFSET; in set_wdqs()
381 msk |= (byte_lane & 1) ? (1 << 4) : (1 << 1); in set_wdqs()
386 msk |= (byte_lane & 1) ? (1 << 10) : (1 << 7); in set_wdqs()
394 training_message(channel, rank, byte_lane); in set_wdqs()
403 * channel, rank, byte_lane as an absolute PI count.
407 uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane) in get_wdqs() argument
416 * RDPTR (1/2 MCLK, 64 PIs) in get_wdqs()
417 * BL0 -> B01PTRCTL0[07:04] (0x0-0xF) in get_wdqs()
418 * BL1 -> B01PTRCTL0[19:16] (0x0-0xF) in get_wdqs()
420 reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in get_wdqs()
421 channel * DDRIODQ_CH_OFFSET; in get_wdqs()
423 temp >>= (byte_lane & 1) ? 16 : 4; in get_wdqs()
430 * PI (1/64 MCLK, 1 PIs) in get_wdqs()
431 * BL0 -> B0DLLPICODER0[21:16] (0x00-0x3F) in get_wdqs()
432 * BL1 -> B1DLLPICODER0[21:16] (0x00-0x3F) in get_wdqs()
434 reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; in get_wdqs()
435 reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + in get_wdqs()
436 channel * DDRIODQ_CH_OFFSET); in get_wdqs()
455 void set_wdq(uint8_t channel, uint8_t rank, in set_wdq() argument
465 channel, rank, byte_lane, pi_count); in set_wdq()
468 * RDPTR (1/2 MCLK, 64 PIs) in set_wdq()
469 * BL0 -> B01PTRCTL0[03:00] (0x0-0xF) in set_wdq()
470 * BL1 -> B01PTRCTL0[15:12] (0x0-0xF) in set_wdq()
472 reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_wdq()
473 channel * DDRIODQ_CH_OFFSET; in set_wdq()
474 msk = (byte_lane & 1) ? 0xf000 : 0xf; in set_wdq()
476 temp <<= (byte_lane & 1) ? 12 : 0; in set_wdq()
480 pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; in set_wdq()
483 * PI (1/64 MCLK, 1 PIs) in set_wdq()
484 * BL0 -> B0DLLPICODER0[13:08] (0x00-0x3F) in set_wdq()
485 * BL1 -> B1DLLPICODER0[13:08] (0x00-0x3F) in set_wdq()
487 reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; in set_wdq()
488 reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_wdq()
489 channel * DDRIODQ_CH_OFFSET); in set_wdq()
496 * BL0/1 -> B01DBCTL1[06/09] (+1 select) in set_wdq()
497 * BL0/1 -> B01DBCTL1[00/03] (enable) in set_wdq()
499 reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_wdq()
500 channel * DDRIODQ_CH_OFFSET; in set_wdq()
505 msk |= (byte_lane & 1) ? (1 << 3) : (1 << 0); in set_wdq()
510 msk |= (byte_lane & 1) ? (1 << 9) : (1 << 6); in set_wdq()
518 training_message(channel, rank, byte_lane); in set_wdq()
527 * channel, rank, byte_lane as an absolute PI count.
531 uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane) in get_wdq() argument
540 * RDPTR (1/2 MCLK, 64 PIs) in get_wdq()
541 * BL0 -> B01PTRCTL0[03:00] (0x0-0xF) in get_wdq()
542 * BL1 -> B01PTRCTL0[15:12] (0x0-0xF) in get_wdq()
544 reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in get_wdq()
545 channel * DDRIODQ_CH_OFFSET; in get_wdq()
547 temp >>= (byte_lane & 1) ? 12 : 0; in get_wdq()
554 * PI (1/64 MCLK, 1 PIs) in get_wdq()
555 * BL0 -> B0DLLPICODER0[13:08] (0x00-0x3F) in get_wdq()
556 * BL1 -> B1DLLPICODER0[13:08] (0x00-0x3F) in get_wdq()
558 reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; in get_wdq()
559 reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + in get_wdq()
560 channel * DDRIODQ_CH_OFFSET); in get_wdq()
577 void set_wcmd(uint8_t channel, uint32_t pi_count) in set_wcmd() argument
586 * RDPTR (1/2 MCLK, 64 PIs) in set_wcmd()
587 * CMDPTRREG[11:08] (0x0-0xF) in set_wcmd()
589 reg = CMDPTRREG + channel * DDRIOCCC_CH_OFFSET; in set_wcmd()
596 pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; in set_wcmd()
599 * PI (1/64 MCLK, 1 PIs) in set_wcmd()
600 * CMDDLLPICODER0[29:24] -> CMDSLICE R3 (unused) in set_wcmd()
601 * CMDDLLPICODER0[21:16] -> CMDSLICE L3 (unused) in set_wcmd()
602 * CMDDLLPICODER0[13:08] -> CMDSLICE R2 (unused) in set_wcmd()
603 * CMDDLLPICODER0[05:00] -> CMDSLICE L2 (unused) in set_wcmd()
604 * CMDDLLPICODER1[29:24] -> CMDSLICE R1 (unused) in set_wcmd()
605 * CMDDLLPICODER1[21:16] -> CMDSLICE L1 (0x00-0x3F) in set_wcmd()
606 * CMDDLLPICODER1[13:08] -> CMDSLICE R0 (unused) in set_wcmd()
607 * CMDDLLPICODER1[05:00] -> CMDSLICE L0 (unused) in set_wcmd()
609 reg = CMDDLLPICODER1 + channel * DDRIOCCC_CH_OFFSET; in set_wcmd()
615 reg = CMDDLLPICODER0 + channel * DDRIOCCC_CH_OFFSET; /* PO */ in set_wcmd()
620 * CMDCFGREG0[17] (+1 select) in set_wcmd()
623 reg = CMDCFGREG0 + channel * DDRIOCCC_CH_OFFSET; in set_wcmd()
628 msk |= (1 << 16); in set_wcmd()
633 msk |= (1 << 17); in set_wcmd()
648 * channel as an absolute PI count.
650 uint32_t get_wcmd(uint8_t channel) in get_wcmd() argument
659 * RDPTR (1/2 MCLK, 64 PIs) in get_wcmd()
660 * CMDPTRREG[11:08] (0x0-0xF) in get_wcmd()
662 reg = CMDPTRREG + channel * DDRIOCCC_CH_OFFSET; in get_wcmd()
671 * PI (1/64 MCLK, 1 PIs) in get_wcmd()
672 * CMDDLLPICODER0[29:24] -> CMDSLICE R3 (unused) in get_wcmd()
673 * CMDDLLPICODER0[21:16] -> CMDSLICE L3 (unused) in get_wcmd()
674 * CMDDLLPICODER0[13:08] -> CMDSLICE R2 (unused) in get_wcmd()
675 * CMDDLLPICODER0[05:00] -> CMDSLICE L2 (unused) in get_wcmd()
676 * CMDDLLPICODER1[29:24] -> CMDSLICE R1 (unused) in get_wcmd()
677 * CMDDLLPICODER1[21:16] -> CMDSLICE L1 (0x00-0x3F) in get_wcmd()
678 * CMDDLLPICODER1[13:08] -> CMDSLICE R0 (unused) in get_wcmd()
679 * CMDDLLPICODER1[05:00] -> CMDSLICE L0 (unused) in get_wcmd()
681 reg = CMDDLLPICODER1 + channel * DDRIOCCC_CH_OFFSET; in get_wcmd()
698 void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count) in set_wclk() argument
707 * RDPTR (1/2 MCLK, 64 PIs) in set_wclk()
708 * CCPTRREG[15:12] -> CLK1 (0x0-0xF) in set_wclk()
709 * CCPTRREG[11:08] -> CLK0 (0x0-0xF) in set_wclk()
711 reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET; in set_wclk()
717 pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; in set_wclk()
720 * PI (1/64 MCLK, 1 PIs) in set_wclk()
721 * ECCB1DLLPICODER0[13:08] -> CLK0 (0x00-0x3F) in set_wclk()
722 * ECCB1DLLPICODER0[21:16] -> CLK1 (0x00-0x3F) in set_wclk()
725 reg += (channel * DDRIOCCC_CH_OFFSET); in set_wclk()
731 reg += (channel * DDRIOCCC_CH_OFFSET); in set_wclk()
735 reg += (channel * DDRIOCCC_CH_OFFSET); in set_wclk()
739 reg += (channel * DDRIOCCC_CH_OFFSET); in set_wclk()
744 * CCCFGREG1[11:08] (+1 select) in set_wclk()
747 reg = CCCFGREG1 + channel * DDRIOCCC_CH_OFFSET; in set_wclk()
772 * channel, rank as an absolute PI count.
774 uint32_t get_wclk(uint8_t channel, uint8_t rank) in get_wclk() argument
783 * RDPTR (1/2 MCLK, 64 PIs) in get_wclk()
784 * CCPTRREG[15:12] -> CLK1 (0x0-0xF) in get_wclk()
785 * CCPTRREG[11:08] -> CLK0 (0x0-0xF) in get_wclk()
787 reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET; in get_wclk()
796 * PI (1/64 MCLK, 1 PIs) in get_wclk()
797 * ECCB1DLLPICODER0[13:08] -> CLK0 (0x00-0x3F) in get_wclk()
798 * ECCB1DLLPICODER0[21:16] -> CLK1 (0x00-0x3F) in get_wclk()
801 reg += (channel * DDRIOCCC_CH_OFFSET); in get_wclk()
819 void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count) in set_wctl() argument
828 * RDPTR (1/2 MCLK, 64 PIs) in set_wctl()
829 * CCPTRREG[31:28] (0x0-0xF) in set_wctl()
830 * CCPTRREG[27:24] (0x0-0xF) in set_wctl()
832 reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET; in set_wctl()
838 pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; in set_wctl()
841 * PI (1/64 MCLK, 1 PIs) in set_wctl()
842 * ECCB1DLLPICODER?[29:24] (0x00-0x3F) in set_wctl()
843 * ECCB1DLLPICODER?[29:24] (0x00-0x3F) in set_wctl()
845 reg = ECCB1DLLPICODER0 + channel * DDRIOCCC_CH_OFFSET; in set_wctl()
850 reg = ECCB1DLLPICODER1 + channel * DDRIOCCC_CH_OFFSET; in set_wctl()
853 reg = ECCB1DLLPICODER2 + channel * DDRIOCCC_CH_OFFSET; in set_wctl()
856 reg = ECCB1DLLPICODER3 + channel * DDRIOCCC_CH_OFFSET; in set_wctl()
861 * CCCFGREG1[13:12] (+1 select) in set_wctl()
864 reg = CCCFGREG1 + channel * DDRIOCCC_CH_OFFSET; in set_wctl()
889 * channel, rank as an absolute PI count.
893 uint32_t get_wctl(uint8_t channel, uint8_t rank) in get_wctl() argument
902 * RDPTR (1/2 MCLK, 64 PIs) in get_wctl()
903 * CCPTRREG[31:28] (0x0-0xF) in get_wctl()
904 * CCPTRREG[27:24] (0x0-0xF) in get_wctl()
906 reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET; in get_wctl()
915 * PI (1/64 MCLK, 1 PIs) in get_wctl()
916 * ECCB1DLLPICODER?[29:24] (0x00-0x3F) in get_wctl()
917 * ECCB1DLLPICODER?[29:24] (0x00-0x3F) in get_wctl()
919 reg = ECCB1DLLPICODER0 + channel * DDRIOCCC_CH_OFFSET; in get_wctl()
934 * byte lane in a given channel.
936 void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting) in set_vref() argument
943 channel, byte_lane, setting); in set_vref()
945 mrc_alt_write_mask(DDRPHY, reg + channel * DDRIODQ_CH_OFFSET + in set_vref()
946 (byte_lane >> 1) * DDRIODQ_BL_OFFSET, in set_vref()
962 * channel, byte_lane.
964 uint32_t get_vref(uint8_t channel, uint8_t byte_lane) in get_vref() argument
973 temp = msg_port_alt_read(DDRPHY, reg + channel * DDRIODQ_CH_OFFSET + in get_vref()
974 (byte_lane >> 1) * DDRIODQ_BL_OFFSET); in get_vref()
991 * This function will return a 32-bit address in the desired
992 * channel and rank.
994 uint32_t get_addr(uint8_t channel, uint8_t rank) in get_addr() argument
999 if (channel > 0) { in get_addr()
1000 DPF(D_ERROR, "ILLEGAL CHANNEL\n"); in get_addr()
1004 if (rank > 1) { in get_addr()
1017 * channel/rank SAMPLE_SIZE times looking for a valid '0' or '1'.
1019 * It will return an encoded 32-bit date in which each bit corresponds to
1022 uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel, in sample_dqs() argument
1029 uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1; in sample_dqs()
1034 uint32_t num_1s; /* tracks the number of '1' samples */ in sample_dqs()
1036 uint32_t address = get_addr(channel, rank); in sample_dqs()
1039 msk[0] = rcvn ? (1 << 1) : (1 << 9); /* BL0 */ in sample_dqs()
1040 msk[1] = rcvn ? (1 << 0) : (1 << 8); /* BL1 */ in sample_dqs()
1046 hte_mem_op(address, mrc_params->first_run, in sample_dqs()
1047 rcvn ? 0 : 1); in sample_dqs()
1048 mrc_params->first_run = 0; in sample_dqs()
1057 channel * DDRIODQ_CH_OFFSET); in sample_dqs()
1061 * look for a majority value (SAMPLE_SIZE / 2) + 1 in sample_dqs()
1067 num_1s = 0x00; /* reset '1' tracker for byte lane */ in sample_dqs()
1075 ret_val |= (1 << (bl + bl_grp * 2)); in sample_dqs()
1081 * "ret_val.1" contains the status of BL1 in sample_dqs()
1090 uint8_t channel, uint8_t rank, bool rcvn) in find_rising_edge() argument
1097 uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1; in find_rising_edge()
1106 mrc_params->first_run = 1; in find_rising_edge()
1114 set_rcvn(channel, rank, bl, in find_rising_edge()
1117 set_wdqs(channel, rank, bl, in find_rising_edge()
1124 channel, rank, rcvn); in find_rising_edge()
1128 rcvn ? "RCVN" : "WDQS", channel, rank, sample, in find_rising_edge()
1137 /* build transition_pattern (MSB is 1st sample) */ in find_rising_edge()
1141 ((sample_result[sample] & (1 << bl)) >> bl) << in find_rising_edge()
1142 (SAMPLE_CNT - 1 - sample); in find_rising_edge()
1152 case 0: /* sampled 0->0->0 */ in find_rising_edge()
1153 /* move forward from T3 looking for 0->1 */ in find_rising_edge()
1157 case 1: /* sampled 0->0->1 */ in find_rising_edge()
1158 case 5: /* sampled 1->0->1 (bad duty cycle) *HSD#237503* */ in find_rising_edge()
1159 /* move forward from T2 looking for 0->1 */ in find_rising_edge()
1160 delay[bl] += 1 * SAMPLE_DLY; in find_rising_edge()
1163 case 2: /* sampled 0->1->0 (bad duty cycle) *HSD#237503* */ in find_rising_edge()
1164 case 3: /* sampled 0->1->1 */ in find_rising_edge()
1165 /* move forward from T1 looking for 0->1 */ in find_rising_edge()
1169 case 4: /* sampled 1->0->0 (assumes BL8, HSD#234975) */ in find_rising_edge()
1170 /* move forward from T3 looking for 0->1 */ in find_rising_edge()
1174 case 6: /* sampled 1->1->0 */ in find_rising_edge()
1175 case 7: /* sampled 1->1->1 */ in find_rising_edge()
1176 /* move backward from T1 looking for 1->0 */ in find_rising_edge()
1187 set_rcvn(channel, rank, bl, delay[bl]); in find_rising_edge()
1189 set_wdqs(channel, rank, bl, delay[bl]); in find_rising_edge()
1199 temp = sample_dqs(mrc_params, channel, rank, rcvn); in find_rising_edge()
1202 if (temp & (1 << bl)) { in find_rising_edge()
1203 /* sampled "1" */ in find_rising_edge()
1210 delay[bl] -= 1; in find_rising_edge()
1212 set_rcvn(channel, rank, in find_rising_edge()
1215 set_wdqs(channel, rank, in find_rising_edge()
1227 delay[bl] += 1; in find_rising_edge()
1229 set_rcvn(channel, rank, in find_rising_edge()
1232 set_wdqs(channel, rank, in find_rising_edge()
1244 delay[0], delay[1], delay[2], delay[3]); in find_rising_edge()
1265 ret_val |= (1 << ((j / NUM_BYTE_LANES) * NUM_BYTE_LANES)); in byte_lane_mask()
1269 * need to adjust the mask for 16-bit mode in byte_lane_mask()
1271 if (mrc_params->channel_width == X16) in byte_lane_mask()
1287 if (mrc_params->hte_setup) { in check_rw_coarse()
1288 mrc_params->hte_setup = 0; in check_rw_coarse()
1289 first_run = 1; in check_rw_coarse()
1311 if (mrc_params->hte_setup) { in check_bls_ex()
1312 mrc_params->hte_setup = 0; in check_bls_ex()
1313 first_run = 1; in check_bls_ex()
1325 * 32-bit LFSR with characteristic polynomial: X^32 + X^22 +X^2 + X^1
1339 bit = 1 ^ (lfsr & 1); in lfsr32()
1340 bit = bit ^ ((lfsr & 2) >> 1); in lfsr32()
1344 lfsr = ((lfsr >> 1) | (bit << 31)); in lfsr32()
1350 /* Clear the pointers in a given byte lane in a given channel */
1353 uint8_t channel; in clear_pointers() local
1358 for (channel = 0; channel < NUM_CHANNELS; channel++) { in clear_pointers()
1362 channel * DDRIODQ_CH_OFFSET + in clear_pointers()
1363 (bl >> 1) * DDRIODQ_BL_OFFSET, in clear_pointers()
1364 ~(1 << 8), (1 << 8)); in clear_pointers()
1368 channel * DDRIODQ_CH_OFFSET + in clear_pointers()
1369 (bl >> 1) * DDRIODQ_BL_OFFSET, in clear_pointers()
1370 (1 << 8), (1 << 8)); in clear_pointers()
1377 static void print_timings_internal(uint8_t algo, uint8_t channel, uint8_t rank, in print_timings_internal() argument
1384 DPF(D_INFO, "\nRCVN[%02d:%02d]", channel, rank); in print_timings_internal()
1387 DPF(D_INFO, "\nWDQS[%02d:%02d]", channel, rank); in print_timings_internal()
1390 DPF(D_INFO, "\nWDQx[%02d:%02d]", channel, rank); in print_timings_internal()
1393 DPF(D_INFO, "\nRDQS[%02d:%02d]", channel, rank); in print_timings_internal()
1396 DPF(D_INFO, "\nVREF[%02d:%02d]", channel, rank); in print_timings_internal()
1399 DPF(D_INFO, "\nWCMD[%02d:%02d]", channel, rank); in print_timings_internal()
1402 DPF(D_INFO, "\nWCTL[%02d:%02d]", channel, rank); in print_timings_internal()
1405 DPF(D_INFO, "\nWCLK[%02d:%02d]", channel, rank); in print_timings_internal()
1414 DPF(D_INFO, " %03d", get_rcvn(channel, rank, bl)); in print_timings_internal()
1417 DPF(D_INFO, " %03d", get_wdqs(channel, rank, bl)); in print_timings_internal()
1420 DPF(D_INFO, " %03d", get_wdq(channel, rank, bl)); in print_timings_internal()
1423 DPF(D_INFO, " %03d", get_rdqs(channel, rank, bl)); in print_timings_internal()
1426 DPF(D_INFO, " %03d", get_vref(channel, bl)); in print_timings_internal()
1429 DPF(D_INFO, " %03d", get_wcmd(channel)); in print_timings_internal()
1432 DPF(D_INFO, " %03d", get_wctl(channel, rank)); in print_timings_internal()
1435 DPF(D_INFO, " %03d", get_wclk(channel, rank)); in print_timings_internal()
1446 uint8_t channel; in print_timings() local
1448 uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1; in print_timings()
1450 DPF(D_INFO, "\n---------------------------"); in print_timings()
1455 for (channel = 0; channel < NUM_CHANNELS; channel++) { in print_timings()
1456 if (mrc_params->channel_enables & (1 << channel)) { in print_timings()
1458 if (mrc_params->rank_enables & in print_timings()
1459 (1 << rank)) { in print_timings()
1461 channel, rank, in print_timings()
1469 DPF(D_INFO, "\n---------------------------"); in print_timings()