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/openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	memory.json	115 …1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", 124 …he prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 133 …on": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 142 …nd data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 151 …xclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 160 …p (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied … 169 … prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 178 …pt PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 187 … "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", 196 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … [all …]
H A D	cache.json	377 …l(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", 467 …l(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", 477 … cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket… 486 …refetches that resulted in a snoop hit a modified line in another core's caches which forwarded th… 495 …d line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket whe… 504 …d line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket whe… 513 …demand data reads that hit in the L3 or were snooped from another core's caches on the same socket… 522 …ata reads that resulted in a snoop hit a modified line in another core's caches which forwarded th… 540 …"Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded th… 549 …e on a remote socket where a snoop hit a modified line in another core's caches which forwarded th… [all …]
H A D	other.json	30 …as found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single s… 38 …m this core's caches, after the data is forwarded back to the requestor, and indicating the data w… 46 …his core's caches without being forwarded back to the requestor. The line was in Forward, Shared o… 54 … to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop re… 308 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 317 …writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 335 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that ha… 344 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 353 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 362 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	cache.json	432 …l(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", 520 …l(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", 545 … cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket… 554 …refetches that resulted in a snoop hit a modified line in another core's caches which forwarded th… 563 …d line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket whe… 572 …d line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket whe… 581 …demand data reads that hit in the L3 or were snooped from another core's caches on the same socket… 590 …ata reads that resulted in a snoop hit a modified line in another core's caches which forwarded th… 608 …"Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded th… 617 …e on a remote socket where a snoop hit a modified line in another core's caches which forwarded th… [all …]
H A D	memory.json	159 …1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", 168 …on": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 177 …xclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 186 … "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", 195 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 204 …demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's … 213 …demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's … 222 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that mi… 231 …BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.", 240 …eaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline …
H A D	other.json	188 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 206 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that ha… 215 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 224 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 233 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 242 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 251 …demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's … 260 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 269 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 278 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A D	l2_cache.json	4 …ata and instruction accesses. Accesses are for misses in the first level caches or translation res… 8 …or data and instruction accesses. Accesses are for misses in the level 1 caches or translation res… 20 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 24 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 28 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 32 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res…
H A D	l1d_cache.json	`8 …om any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic opera… 16 …from any load operation. Atomic load operations that resolve in the CPUs caches counts as both a w… 20 …al address) instruction. Near atomic operations that resolve in the CPUs caches count as a write a… 32 …: "Counts level 1 data cache refills where the cache line data came from caches inside the immedia…`
/openbmc/qemu/hw/virtio/
H A D	virtio.c	112 VRingMemoryRegionCaches caches; member 209 static void virtio_free_region_cache(VRingMemoryRegionCaches caches) in virtio_free_region_cache() argument 211 assert(caches != NULL); in virtio_free_region_cache() 212 address_space_cache_destroy(&caches->desc); in virtio_free_region_cache() 213 address_space_cache_destroy(&caches->avail); in virtio_free_region_cache() 214 address_space_cache_destroy(&caches->used); in virtio_free_region_cache() 215 g_free(caches); in virtio_free_region_cache() 220 VRingMemoryRegionCaches *caches; in virtio_virtqueue_reset_region_cache() local 222 caches = qatomic_read(&vq->vring.caches); in virtio_virtqueue_reset_region_cache() 223 qatomic_rcu_set(&vq->vring.caches, NULL); in virtio_virtqueue_reset_region_cache() [all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
H A D	l2_cache.json	4 …ata and instruction accesses. Accesses are for misses in the first level caches or translation res… 8 …or data and instruction accesses. Accesses are for misses in the level 1 caches or translation res… 20 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 24 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 28 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 32 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res…
H A D	l1d_cache.json	`8 …om any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic opera… 20 …from any load operation. Atomic load operations that resolve in the CPUs caches count as both a wr… 24 …al address) instruction. Near atomic operations that resolve in the CPUs caches count as a write a… 36 …: "Counts level 1 data cache refills where the cache line data came from caches inside the immedia…`
/openbmc/linux/Documentation/block/
H A D	writeback_cache_control.rst	`9 write back caches. That means the devices signal I/O completion to the 60 devices with volatile caches need to implement the support for these 67 For devices that do not support volatile write caches there is no driver 70 requests that have a payload. For devices with volatile write caches the 71 driver needs to tell the block layer that it supports flushing caches by`
/openbmc/linux/Documentation/filesystems/
H A D	9p.rst	`80 cache=mode specifies a caching policy. By default, no caches are used. 86 0b00000000 all caches disabled, mmap disabled 87 0b00000001 file caches enabled 88 0b00000010 meta-data caches enabled 90 0b00001000 loose caches (no explicit consistency with server) 100 loose 0b00001111 (non-coherent file and meta-data caches) 108 IMPORTANT: loose caches (and by extension at the moment fscache) 184 /sys/fs/9p/caches. (applies only to cache=fscache)`
/openbmc/linux/arch/sparc/include/asm/
H A D	viking.h	27 * and never caches them internally (or so states the docs). Therefore 38 * on chip split I/D caches of the GNU/Viking. 45 * caches will snoop regardless of whether they are enabled, this 46 * takes care of the case where the I or D or both caches are turned 58 * caches, they may be cached by the GNU/MXCC if present and enabled. 72 * caches during that cycle. If disabled, all stores operations 78 * These bits enable the on-cpu GNU/Viking split I/D caches. Note, 79 * as mentioned above, these caches will snoop the bus in GNU/MBUS
/openbmc/linux/Documentation/filesystems/nfs/
H A D	rpc-cache.rst	`9 Caches subtitle 13 a wide variety of values to be caches. 15 There are a number of caches that are similar in structure though 17 of common code for managing these caches. 19 Examples of caches that are likely to be needed are: 105 includes it on a list of caches that will be regularly`
/openbmc/linux/arch/openrisc/
H A D	Kconfig	`84 bool "Have write through data caches" 87 Select this if your implementation features write through data caches. 89 caches at relevant times. Most OpenRISC implementations support write- 90 through data caches.`
/openbmc/linux/include/linux/
H A D	kvm_types.h	`84 * Memory caches are used to preallocate memory ahead of various MMU flows, 87 * holding MMU locks. Note, these caches act more like prefetch buffers than 88 * classical caches, i.e. objects are not returned to the cache on being freed.`
/openbmc/linux/arch/mips/mm/
H A D	c-r4k.c	75 * separate caches). in r4k_op_needs_ipi() 387 * These caches are inclusive caches, that is, if something in local_r4k___flush_cache_all() 389 * in one of the primary caches. in local_r4k___flush_cache_all() 468 * whole caches when vma is executable. 508 * only flush the primary caches but R1x000 behave sane ... in local_r4k_flush_cache_mm() 510 * caches, so we can bail out early. in local_r4k_flush_cache_mm() 770 * Either no secondary cache or the available caches don't have the in r4k_dma_cache_wback_inv() 771 * subset property so we have to flush the primary caches in r4k_dma_cache_wback_inv() 874 * Aliases only affect the primary caches so don't bother with in local_r4k_flush_kernel_vmap_range_index() 875 * S-caches or T-caches. in local_r4k_flush_kernel_vmap_range_index() [all …]
/openbmc/qemu/docs/
H A D	qcow2-cache.txt	`11 The QEMU qcow2 driver has two caches that can improve the I/O 16 caches, and how to configure them. 83 caches (in bytes) is: 121 "cache-size": maximum size of both caches combined 125 - Both caches must have a size that is a multiple of the cluster size 155 L2 cache size. This resulted in unnecessarily large caches, so now the`
/openbmc/qemu/qapi/
H A D	machine-common.json	`67 # Caches a system may have. The enumeration value here is the 107 # @caches: the list of SmpCacheProperties. 112 'data': { 'caches': ['SmpCacheProperties'] } }`
/openbmc/linux/arch/arm64/kernel/
H A D	cacheinfo.c	`51 /* Separate instruction and data caches / in detect_cache_level() 86 some external caches not specified in CLIDR_EL1 in init_cache_level() 88 * only unified external caches are considered here in init_cache_level()`
/openbmc/linux/arch/mips/kernel/
H A D	bmips_5xxx_init.S	`300 * Description: Enable I and D caches, initialize I and D-caches, also set 323 * Description: Enable I and D caches, and initialize I and D-caches 344 /* Enable Caches before Clearing. If the caches are disabled 715 * Description: Enable I and D caches, and initialize I and D-caches`
/openbmc/linux/arch/mips/include/asm/
H A D	io.h	497 * The caches on some architectures aren't dma-coherent and have need to 501 * - dma_cache_wback_inv(start, size) makes caches and coherent by 502 * writing the content of the caches back to memory, if necessary. 503 * The function also invalidates the affected part of the caches as 505 * - dma_cache_wback(start, size) makes caches and coherent by 506 * writing the content of the caches back to memory, if necessary. 507 * The function also invalidates the affected part of the caches as 510 * caches. Dirty lines of the caches may be written back or simply
/openbmc/u-boot/arch/x86/include/asm/
H A D	cache.h	`29 /* Enable caches and write buffer / 32 / Disable caches and write buffer */`
/openbmc/linux/tools/cgroup/
H A D	memcg_slabinfo.py	`184 caches = {} 203 caches[addr] = cache 215 for addr in caches: 217 cache_show(caches[addr], cfg, stats[addr])`

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