1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 23620f860SAnton Staaf /* 33620f860SAnton Staaf * Copyright (c) 2011 The Chromium OS Authors. 43620f860SAnton Staaf */ 53620f860SAnton Staaf 63620f860SAnton Staaf #ifndef __X86_CACHE_H__ 73620f860SAnton Staaf #define __X86_CACHE_H__ 83620f860SAnton Staaf 93620f860SAnton Staaf /* 103620f860SAnton Staaf * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise 113620f860SAnton Staaf * use 64-bytes, a safe default for x86. 123620f860SAnton Staaf */ 13bf4ea7edSStefan Roese #ifndef CONFIG_SYS_CACHELINE_SIZE 14bf4ea7edSStefan Roese #define CONFIG_SYS_CACHELINE_SIZE 64 153620f860SAnton Staaf #endif 163620f860SAnton Staaf 17bf4ea7edSStefan Roese #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 18bf4ea7edSStefan Roese wbinvd(void)19095593c0SStefan Reinauerstatic inline void wbinvd(void) 20095593c0SStefan Reinauer { 21095593c0SStefan Reinauer asm volatile ("wbinvd" : : : "memory"); 22095593c0SStefan Reinauer } 23095593c0SStefan Reinauer invd(void)24095593c0SStefan Reinauerstatic inline void invd(void) 25095593c0SStefan Reinauer { 26095593c0SStefan Reinauer asm volatile("invd" : : : "memory"); 27095593c0SStefan Reinauer } 28095593c0SStefan Reinauer 29095593c0SStefan Reinauer /* Enable caches and write buffer */ 30095593c0SStefan Reinauer void enable_caches(void); 31095593c0SStefan Reinauer 32095593c0SStefan Reinauer /* Disable caches and write buffer */ 33095593c0SStefan Reinauer void disable_caches(void); 34095593c0SStefan Reinauer 353620f860SAnton Staaf #endif /* __X86_CACHE_H__ */ 36