1b2441318SGreg Kroah-Hartman# SPDX-License-Identifier: GPL-2.0 2f8c4a270SJonas Bonn# 3f8c4a270SJonas Bonn# For a description of the syntax of this configuration file, 4cd238effSMauro Carvalho Chehab# see Documentation/kbuild/kconfig-language.rst. 5f8c4a270SJonas Bonn# 6f8c4a270SJonas Bonn 7f8c4a270SJonas Bonnconfig OPENRISC 8f8c4a270SJonas Bonn def_bool y 9942fa985SYury Norov select ARCH_32BIT_OFF_T 10a4a4d11aSChristoph Hellwig select ARCH_HAS_DMA_SET_UNCACHED 11a4a4d11aSChristoph Hellwig select ARCH_HAS_DMA_CLEAR_UNCACHED 125600779eSChristoph Hellwig select ARCH_HAS_SYNC_DMA_FOR_DEVICE 137f435e42SStafford Horne select COMMON_CLK 14f8c4a270SJonas Bonn select OF 15f8c4a270SJonas Bonn select OF_EARLY_FLATTREE 16b4c4c6eeSJonas Bonn select IRQ_DOMAIN 178636f344SLinus Walleij select GPIOLIB 18f8c4a270SJonas Bonn select HAVE_ARCH_TRACEHOOK 19c0fcaf55SJonas Bonn select SPARSE_IRQ 20f8c4a270SJonas Bonn select GENERIC_IRQ_CHIP 21f8c4a270SJonas Bonn select GENERIC_IRQ_PROBE 22f8c4a270SJonas Bonn select GENERIC_IRQ_SHOW 23ded2ee36SStafford Horne select GENERIC_PCI_IOMAP 24*9b994429SBaoquan He select GENERIC_IOREMAP 259f13a1fdSBen Hutchings select GENERIC_CPU_DEVICES 26ded2ee36SStafford Horne select HAVE_PCI 2704ea1e91SAndrew Morton select HAVE_UID16 280662d33aSRichard Weinberger select GENERIC_ATOMIC64 298e6d08e0SStefan Kristiansson select GENERIC_CLOCKEVENTS_BROADCAST 308e6d08e0SStefan Kristiansson select GENERIC_SMP_IDLE_THREAD 31786d35d4SDavid Howells select MODULES_USE_ELF_RELA 32d1a1dc0bSDave Hansen select HAVE_DEBUG_STACKOVERFLOW 334db8e6d2SStefan Kristiansson select OR1K_PIC 34fff7fb0bSZhaoxiu Zeng select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 35b5f82176SStafford Horne select ARCH_USE_QUEUED_RWLOCKS 369b54470aSStafford Horne select OMPIC if SMP 37ded2ee36SStafford Horne select PCI_DOMAINS_GENERIC if PCI 38ded2ee36SStafford Horne select PCI_MSI if PCI 39eecac38bSStafford Horne select ARCH_WANT_FRAME_POINTERS 40c5ca4560SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 416137fed0SPeter Zijlstra select MMU_GATHER_NO_RANGE if MMU 424aae683fSMasahiro Yamada select TRACE_IRQFLAGS_SUPPORT 43f8c4a270SJonas Bonn 444c97a0c8SBabu Mogerconfig CPU_BIG_ENDIAN 454c97a0c8SBabu Moger def_bool y 464c97a0c8SBabu Moger 47f8c4a270SJonas Bonnconfig MMU 48f8c4a270SJonas Bonn def_bool y 49f8c4a270SJonas Bonn 50f8c4a270SJonas Bonnconfig GENERIC_HWEIGHT 51f8c4a270SJonas Bonn def_bool y 52f8c4a270SJonas Bonn 53ce816fa8SUwe Kleine-Königconfig NO_IOPORT_MAP 54f8c4a270SJonas Bonn def_bool y 55f8c4a270SJonas Bonn 56f8c4a270SJonas Bonn# For now, use generic checksum functions 57f8c4a270SJonas Bonn#These can be reimplemented in assembly later if so inclined 58f8c4a270SJonas Bonnconfig GENERIC_CSUM 59f8c4a270SJonas Bonn def_bool y 60f8c4a270SJonas Bonn 61eecac38bSStafford Horneconfig STACKTRACE_SUPPORT 62eecac38bSStafford Horne def_bool y 63eecac38bSStafford Horne 6478cdfb5cSStafford Horneconfig LOCKDEP_SUPPORT 6578cdfb5cSStafford Horne def_bool y 6678cdfb5cSStafford Horne 67f8c4a270SJonas Bonnmenu "Processor type and features" 68f8c4a270SJonas Bonn 69f8c4a270SJonas Bonnchoice 70f8c4a270SJonas Bonn prompt "Subarchitecture" 71f8c4a270SJonas Bonn default OR1K_1200 72f8c4a270SJonas Bonn 73f8c4a270SJonas Bonnconfig OR1K_1200 74f8c4a270SJonas Bonn bool "OR1200" 75f8c4a270SJonas Bonn help 76f8c4a270SJonas Bonn Generic OpenRISC 1200 architecture 77f8c4a270SJonas Bonn 78f8c4a270SJonas Bonnendchoice 79f8c4a270SJonas Bonn 804ee93d80SJan Henrik Weinstockconfig DCACHE_WRITETHROUGH 814ee93d80SJan Henrik Weinstock bool "Have write through data caches" 824ee93d80SJan Henrik Weinstock default n 834ee93d80SJan Henrik Weinstock help 844ee93d80SJan Henrik Weinstock Select this if your implementation features write through data caches. 854ee93d80SJan Henrik Weinstock Selecting 'N' here will allow the kernel to force flushing of data 864ee93d80SJan Henrik Weinstock caches at relevant times. Most OpenRISC implementations support write- 874ee93d80SJan Henrik Weinstock through data caches. 884ee93d80SJan Henrik Weinstock 894ee93d80SJan Henrik Weinstock If unsure say N here 904ee93d80SJan Henrik Weinstock 91f8c4a270SJonas Bonnconfig OPENRISC_BUILTIN_DTB 92f8c4a270SJonas Bonn string "Builtin DTB" 93f8c4a270SJonas Bonn default "" 94f8c4a270SJonas Bonn 95f8c4a270SJonas Bonnmenu "Class II Instructions" 96f8c4a270SJonas Bonn 97f8c4a270SJonas Bonnconfig OPENRISC_HAVE_INST_FF1 98f8c4a270SJonas Bonn bool "Have instruction l.ff1" 99f8c4a270SJonas Bonn default y 100f8c4a270SJonas Bonn help 101f8c4a270SJonas Bonn Select this if your implementation has the Class II instruction l.ff1 102f8c4a270SJonas Bonn 103f8c4a270SJonas Bonnconfig OPENRISC_HAVE_INST_FL1 104f8c4a270SJonas Bonn bool "Have instruction l.fl1" 105f8c4a270SJonas Bonn default y 106f8c4a270SJonas Bonn help 107f8c4a270SJonas Bonn Select this if your implementation has the Class II instruction l.fl1 108f8c4a270SJonas Bonn 109f8c4a270SJonas Bonnconfig OPENRISC_HAVE_INST_MUL 110f8c4a270SJonas Bonn bool "Have instruction l.mul for hardware multiply" 111f8c4a270SJonas Bonn default y 112f8c4a270SJonas Bonn help 113f8c4a270SJonas Bonn Select this if your implementation has a hardware multiply instruction 114f8c4a270SJonas Bonn 115f8c4a270SJonas Bonnconfig OPENRISC_HAVE_INST_DIV 116f8c4a270SJonas Bonn bool "Have instruction l.div for hardware divide" 117f8c4a270SJonas Bonn default y 118f8c4a270SJonas Bonn help 119f8c4a270SJonas Bonn Select this if your implementation has a hardware divide instruction 12087e387acSStafford Horne 12187e387acSStafford Horneconfig OPENRISC_HAVE_INST_CMOV 12287e387acSStafford Horne bool "Have instruction l.cmov for conditional move" 12387e387acSStafford Horne default n 12487e387acSStafford Horne help 12587e387acSStafford Horne This config enables gcc to generate l.cmov instructions when compiling 12687e387acSStafford Horne the kernel which in general will improve performance and reduce the 12787e387acSStafford Horne binary size. 12887e387acSStafford Horne 12987e387acSStafford Horne Select this if your implementation has support for the Class II 13087e387acSStafford Horne l.cmov conistional move instruction. 13187e387acSStafford Horne 13287e387acSStafford Horne Say N if you are unsure. 13387e387acSStafford Horne 13487e387acSStafford Horneconfig OPENRISC_HAVE_INST_ROR 13587e387acSStafford Horne bool "Have instruction l.ror for rotate right" 13687e387acSStafford Horne default n 13787e387acSStafford Horne help 13887e387acSStafford Horne This config enables gcc to generate l.ror instructions when compiling 13987e387acSStafford Horne the kernel which in general will improve performance and reduce the 14087e387acSStafford Horne binary size. 14187e387acSStafford Horne 14287e387acSStafford Horne Select this if your implementation has support for the Class II 14387e387acSStafford Horne l.ror rotate right instruction. 14487e387acSStafford Horne 14587e387acSStafford Horne Say N if you are unsure. 14687e387acSStafford Horne 14787e387acSStafford Horneconfig OPENRISC_HAVE_INST_RORI 14887e387acSStafford Horne bool "Have instruction l.rori for rotate right with immediate" 14987e387acSStafford Horne default n 15087e387acSStafford Horne help 15187e387acSStafford Horne This config enables gcc to generate l.rori instructions when compiling 15287e387acSStafford Horne the kernel which in general will improve performance and reduce the 15387e387acSStafford Horne binary size. 15487e387acSStafford Horne 15587e387acSStafford Horne Select this if your implementation has support for the Class II 15687e387acSStafford Horne l.rori rotate right with immediate instruction. 15787e387acSStafford Horne 15887e387acSStafford Horne Say N if you are unsure. 15987e387acSStafford Horne 16087e387acSStafford Horneconfig OPENRISC_HAVE_INST_SEXT 16187e387acSStafford Horne bool "Have instructions l.ext* for sign extension" 16287e387acSStafford Horne default n 16387e387acSStafford Horne help 16487e387acSStafford Horne This config enables gcc to generate l.ext* instructions when compiling 16587e387acSStafford Horne the kernel which in general will improve performance and reduce the 16687e387acSStafford Horne binary size. 16787e387acSStafford Horne 16887e387acSStafford Horne Select this if your implementation has support for the Class II 16987e387acSStafford Horne l.exths, l.extbs, l.exthz and l.extbz size extend instructions. 17087e387acSStafford Horne 17187e387acSStafford Horne Say N if you are unsure. 17287e387acSStafford Horne 173f8c4a270SJonas Bonnendmenu 174f8c4a270SJonas Bonn 17534bbdcdcSStafford Horneconfig NR_CPUS 1768e6d08e0SStefan Kristiansson int "Maximum number of CPUs (2-32)" 1778e6d08e0SStefan Kristiansson range 2 32 1788e6d08e0SStefan Kristiansson depends on SMP 1798e6d08e0SStefan Kristiansson default "2" 1808e6d08e0SStefan Kristiansson 1818e6d08e0SStefan Kristianssonconfig SMP 1828e6d08e0SStefan Kristiansson bool "Symmetric Multi-Processing support" 1838e6d08e0SStefan Kristiansson help 1848e6d08e0SStefan Kristiansson This enables support for systems with more than one CPU. If you have 1858e6d08e0SStefan Kristiansson a system with only one CPU, say N. If you have a system with more 1868e6d08e0SStefan Kristiansson than one CPU, say Y. 1878e6d08e0SStefan Kristiansson 1888e6d08e0SStefan Kristiansson If you don't know what to do here, say N. 189f8c4a270SJonas Bonn 1908636a1f9SMasahiro Yamadasource "kernel/Kconfig.hz" 191f8c4a270SJonas Bonn 192f8c4a270SJonas Bonnconfig OPENRISC_NO_SPR_SR_DSX 193f8c4a270SJonas Bonn bool "use SPR_SR_DSX software emulation" if OR1K_1200 194f8c4a270SJonas Bonn default y 195f8c4a270SJonas Bonn help 196f8c4a270SJonas Bonn SPR_SR_DSX bit is status register bit indicating whether 197f8c4a270SJonas Bonn the last exception has happened in delay slot. 198f8c4a270SJonas Bonn 199f8c4a270SJonas Bonn OpenRISC architecture makes it optional to have it implemented 200f8c4a270SJonas Bonn in hardware and the OR1200 does not have it. 201f8c4a270SJonas Bonn 202f8c4a270SJonas Bonn Say N here if you know that your OpenRISC processor has 203f8c4a270SJonas Bonn SPR_SR_DSX bit implemented. Say Y if you are unsure. 204f8c4a270SJonas Bonn 20591993c8cSStefan Kristianssonconfig OPENRISC_HAVE_SHADOW_GPRS 20691993c8cSStefan Kristiansson bool "Support for shadow gpr files" if !SMP 20791993c8cSStefan Kristiansson default y if SMP 20891993c8cSStefan Kristiansson help 20991993c8cSStefan Kristiansson Say Y here if your OpenRISC processor features shadowed 21091993c8cSStefan Kristiansson register files. They will in such case be used as a 21191993c8cSStefan Kristiansson scratch reg storage on exception entry. 21291993c8cSStefan Kristiansson 21391993c8cSStefan Kristiansson On SMP systems, this feature is mandatory. 21491993c8cSStefan Kristiansson On a unicore system it's safe to say N here if you are unsure. 21591993c8cSStefan Kristiansson 216f8c4a270SJonas Bonnconfig CMDLINE 217f8c4a270SJonas Bonn string "Default kernel command string" 218f8c4a270SJonas Bonn default "" 219f8c4a270SJonas Bonn help 220f8c4a270SJonas Bonn On some architectures there is currently no way for the boot loader 221f8c4a270SJonas Bonn to pass arguments to the kernel. For these architectures, you should 222f8c4a270SJonas Bonn supply some command-line options at build time by entering them 223f8c4a270SJonas Bonn here. 224f8c4a270SJonas Bonn 225f8c4a270SJonas Bonnmenu "Debugging options" 226f8c4a270SJonas Bonn 227f8c4a270SJonas Bonnconfig JUMP_UPON_UNHANDLED_EXCEPTION 228f8c4a270SJonas Bonn bool "Try to die gracefully" 229f8c4a270SJonas Bonn default y 230f8c4a270SJonas Bonn help 231f8c4a270SJonas Bonn Now this puts kernel into infinite loop after first oops. Till 232f8c4a270SJonas Bonn your kernel crashes this doesn't have any influence. 233f8c4a270SJonas Bonn 234f8c4a270SJonas Bonn Say Y if you are unsure. 235f8c4a270SJonas Bonn 236f8c4a270SJonas Bonnconfig OPENRISC_ESR_EXCEPTION_BUG_CHECK 237f8c4a270SJonas Bonn bool "Check for possible ESR exception bug" 238f8c4a270SJonas Bonn default n 239f8c4a270SJonas Bonn help 240f8c4a270SJonas Bonn This option enables some checks that might expose some problems 241f8c4a270SJonas Bonn in kernel. 242f8c4a270SJonas Bonn 243f8c4a270SJonas Bonn Say N if you are unsure. 244f8c4a270SJonas Bonn 245f8c4a270SJonas Bonnendmenu 246f8c4a270SJonas Bonn 247f8c4a270SJonas Bonnendmenu 248