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/openbmc/qemu/include/qemu/
H A Dthrottle-options.h7 * See the COPYING file in the top-level directory for details.
13 #define QEMU_OPT_IOPS_TOTAL "iops-total"
14 #define QEMU_OPT_IOPS_TOTAL_MAX "iops-total-max"
15 #define QEMU_OPT_IOPS_TOTAL_MAX_LENGTH "iops-total-max-length"
16 #define QEMU_OPT_IOPS_READ "iops-read"
17 #define QEMU_OPT_IOPS_READ_MAX "iops-read-max"
18 #define QEMU_OPT_IOPS_READ_MAX_LENGTH "iops-read-max-length"
19 #define QEMU_OPT_IOPS_WRITE "iops-write"
20 #define QEMU_OPT_IOPS_WRITE_MAX "iops-write-max"
21 #define QEMU_OPT_IOPS_WRITE_MAX_LENGTH "iops-write-max-length"
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/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dqcom_hidma_mgmt.txt14 instance can use like maximum read/write request and number of bytes to
15 read/write in a single burst.
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
31 - max-write-transactions: This value is how many times a write burst is
34 - max-read-transactions: This value is how many times a read burst is
36 - channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
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H A Drenesas,nbpfaxi.txt1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
7 - compatible: must be one of
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
26 - max-burst-mem-read: limit burst size for memory reads
28 than using the maximum burst size allowed by the hardware's buffer size.
29 - max-burst-mem-write: limit burst size for memory writes
31 than using the maximum burst size allowed by the hardware's buffer size.
32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
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H A Dintel,ldma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
21 - intel,lgm-dma1rx
22 - intel,lgm-dma1tx
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/openbmc/u-boot/drivers/sysreset/
H A Dsysreset_mpc83xx.h1 /* SPDX-License-Identifier: GPL-2.0+ */
62 "TDM-DMAC"
70 "Address-only, Clean Block",
71 "Address-only, lwarx reservation set",
72 "Single-beat or Burst write",
74 "Address-only, Flush Block",
76 "Burst write",
78 "Address-only, sync",
79 "Address-only, tlbsync",
80 "Single-beat or Burst read",
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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/openbmc/linux/include/linux/platform_data/
H A Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
37 u32 cs_wr_off; /* Write deassertion time */
42 u32 adv_wr_off; /* Write deassertion time */
45 u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */
59 u32 access; /* Start-cycle to first data valid delay */
61 u32 wr_cycle; /* Total write cycle time */
97 u32 t_cez_w; /* write CS deassertion to high Z */
100 u32 t_wpl; /* write assertion time */
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/openbmc/qemu/hw/ssi/
H A Dimx_spi.c4 * Copyright (c) 2016 Jean-Christophe Dubois <jcd@tribudubois.net>
7 * See the COPYING file in the top-level directory.
76 fifo32_reset(&s->tx_fifo); in imx_spi_txfifo_reset()
77 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE; in imx_spi_txfifo_reset()
78 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF; in imx_spi_txfifo_reset()
83 fifo32_reset(&s->rx_fifo); in imx_spi_rxfifo_reset()
84 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR; in imx_spi_rxfifo_reset()
85 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF; in imx_spi_rxfifo_reset()
86 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RO; in imx_spi_rxfifo_reset()
93 if (fifo32_is_empty(&s->rx_fifo)) { in imx_spi_update_irq()
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/openbmc/linux/drivers/dma/qcom/
H A Dhidma_mgmt.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
22 #include <linux/dma-mapping.h>
50 "maximum write burst (default: ACPI/DT value)");
55 "maximum read burst (default: ACPI/DT value)");
60 "maximum number of write transactions (default: ACPI/DT value)");
72 if (!is_power_of_2(mgmtdev->max_write_request) || in hidma_mgmt_setup()
73 (mgmtdev->max_write_request < 128) || in hidma_mgmt_setup()
74 (mgmtdev->max_write_request > 1024)) { in hidma_mgmt_setup()
75 dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n", in hidma_mgmt_setup()
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/openbmc/linux/include/linux/iio/imu/
H A Dadis.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
26 * struct adis_timeouts - ADIS chip variant timeouts
27 * @reset_ms - Wait time after rst pin goes inactive
28 * @sw_reset_ms - Wait time after sw reset command
29 * @self_test_ms - Wait time after self test command
38 * struct adis_data - ADIS chip variant specific data
40 * @write_delay: SPI delay for write operations in us
47 * @self_test_mask: Bitmask of supported self-test operations
49 * @self_test_no_autoclear: True if device's self-test needs clear of ctrl reg
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/openbmc/linux/drivers/misc/
H A Ddw-xdata-pcie.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pci-epf.h>
20 #define DW_XDATA_DRIVER_NAME "dw-xdata-pcie"
75 return dw->rg_region.vaddr; in __dw_regs()
80 u32 burst; in dw_xdata_stop() local
82 mutex_lock(&dw->mutex); in dw_xdata_stop()
84 burst = readl(&(__dw_regs(dw)->burst_cnt)); in dw_xdata_stop()
86 if (burst & BURST_REPEAT) { in dw_xdata_stop()
87 burst &= ~(u32)BURST_REPEAT; in dw_xdata_stop()
88 writel(burst, &(__dw_regs(dw)->burst_cnt)); in dw_xdata_stop()
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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-gta04a5one.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@goldelico.com>
6 #include "omap3-gta04a5.dts"
13 gpmc_pins: gpmc-pins {
14 pinctrl-single,pins = <
45 pinctrl-names = "default";
46 pinctrl-0 = <&gpmc_pins>;
48 /delete-node/ nand@0,0;
52 #address-cells = <1>;
53 #size-cells = <1>;
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/openbmc/linux/drivers/dma/dw-edma/
H A Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
17 #include <linux/dma-mapping.h>
19 #include "dw-edma-core.h"
20 #include "dw-edma-v0-core.h"
21 #include "dw-hdma-v0-core.h"
23 #include "../virt-dma.h"
28 return &dchan->dev->device; in dchan2dev()
34 return &chan->vc.chan.dev->device; in chan2dev()
46 struct dw_edma_chip *chip = chan->dw->chip; in dw_edma_get_pci_address()
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/openbmc/linux/drivers/char/tpm/
H A Dtpm_tis_i2c_cr50.c1 // SPDX-License-Identifier: GPL-2.0
10 * - Use an interrupt for transaction status instead of hardcoded delays.
11 * - Must use write+wait+read read protocol.
12 * - All 4 bytes of status register must be read/written at once.
13 * - Burst count max is 63 bytes, and burst count behaves slightly differently
15 * - When reading from FIFO the full burstcnt must be read instead of just
45 * struct tpm_i2c_cr50_priv_data - Driver private data.
60 * tpm_cr50_i2c_int_handler() - cr50 interrupt handler.
74 struct tpm_i2c_cr50_priv_data *priv = dev_get_drvdata(&chip->dev); in tpm_cr50_i2c_int_handler()
76 complete(&priv->tpm_ready); in tpm_cr50_i2c_int_handler()
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/openbmc/linux/include/linux/mtd/
H A Dhyperbus.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
18 #define HYPERBUS_BT 0x20 /* Burst Type */
28 * struct hyperbus_device - struct representing HyperBus slave device
47 * struct hyperbus_ops - struct representing custom HyperBus operations
48 * @read16: read 16 bit of data from flash in a single burst. Used to read
50 * @write16: write 16 bit of data to flash in a single burst. Used to
51 * send cmd to flash or write single 16 bit word at a time.
69 * struct hyperbus_ctlr - struct representing HyperBus controller
82 * hyperbus_register_device - probe and register a HyperBus slave memory device
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/openbmc/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
23 /* Enable bit for Host Burst Access */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
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/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dexynos_mipi_dsi.txt1 Exynos MIPI-DSIM Controller
6 compatible: should be "samsung,exynos-mipi-dsi"
7 reg: Base address of MIPI-DSIM IP.
10 samsung,dsim-config-e-interface: interface to be used (RGB interface
12 samsung,dsim-config-e-virtual-ch: virtual channel number that main
14 samsung,dsim-config-e-pixel-format: pixel stream format for main
16 samsung,dsim-config-e-burst-mode: selects Burst mode in Video mode.
17 in Non-burst mode, RGB data area is filled with RGB data and
19 samsung,dsim-config-e-no-data-lane: data lane count used by Master.
20 samsung,dsim-config-e-byte-clk: select byte clock source.
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/openbmc/qemu/hw/sh4/
H A Dsh7750_regs.h2 * SH-7750 memory-mapped registers
6 * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
55 /* Page Table Entry High register - PTEH */
64 /* Page Table Entry Low register - PTEL */
70 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
73 #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */
74 #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */
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/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dsnps,dwc-qos-ethernet.txt10 - compatible: One of:
11 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
12 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
13 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
15 - "snps,dwc-qos-ethernet-4.10"
17 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
19 - reg: Address and length of the register set for the device
20 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
21 same order. See ../clock/clock-bindings.txt.
22 - clock-names: May contain any/all of the following depending on the IP
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
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/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dcpu_init.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
12 #include <usb/ehci-ci.h>
211 clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val); in cpu_init_f()
213 clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val); in cpu_init_f()
215 clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val); in cpu_init_f()
217 /* RSR - Reset Status Register - clear all status (4.6.1.3) */ in cpu_init_f()
218 gd->arch.reset_status = __raw_readl(&im->reset.rsr); in cpu_init_f()
219 __raw_writel(~(RSR_RES), &im->reset.rsr); in cpu_init_f()
221 /* AER - Arbiter Event Register - store status */ in cpu_init_f()
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/openbmc/qemu/util/
H A Dthrottle.c4 * Copyright (C) Nodalink, EURL. 2013-2014
41 leak = (bkt->avg * (double) delta_ns) / NANOSECONDS_PER_SECOND; in throttle_leak_bucket()
44 bkt->level = MAX(bkt->level - leak, 0); in throttle_leak_bucket()
47 * keep track of bkt->burst_level so the bkt->max goal per second in throttle_leak_bucket()
49 if (bkt->burst_length > 1) { in throttle_leak_bucket()
50 leak = (bkt->max * (double) delta_ns) / NANOSECONDS_PER_SECOND; in throttle_leak_bucket()
51 bkt->burst_level = MAX(bkt->burst_level - leak, 0); in throttle_leak_bucket()
62 int64_t delta_ns = now - ts->previous_leak; in throttle_do_leak()
65 ts->previous_leak = now; in throttle_do_leak()
73 throttle_leak_bucket(&ts->cfg.buckets[i], delta_ns); in throttle_do_leak()
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/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg1 # SPDX-License-Identifier: GPL-2.0+
9 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 # Refer doc/README.kwbimage for more details about how-to configure
22 # Configure RGMII-0 interface pad voltage to 1.8V
27 # bit13-0: 0xc30, 3120 DDR2 clks refresh rate
28 # bit23-14: 0 required
31 # bit29-26: 0 required
32 # bit31-30: 0b01 required
35 # bit3-0: 0 required
39 # bit11-7: 0 required
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/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0: 0 required
41 # bit11-7: 0 required
45 # bit17-15: 0 required
[all …]
H A Dkwbimage-lsxhl.cfg1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0: 0 required
41 # bit11-7: 0 required
45 # bit17-15: 0 required
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