Lines Matching +full:burst +full:- +full:write
4 * Copyright (c) 2016 Jean-Christophe Dubois <jcd@tribudubois.net>
7 * See the COPYING file in the top-level directory.
76 fifo32_reset(&s->tx_fifo); in imx_spi_txfifo_reset()
77 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE; in imx_spi_txfifo_reset()
78 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF; in imx_spi_txfifo_reset()
83 fifo32_reset(&s->rx_fifo); in imx_spi_rxfifo_reset()
84 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR; in imx_spi_rxfifo_reset()
85 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF; in imx_spi_rxfifo_reset()
86 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RO; in imx_spi_rxfifo_reset()
93 if (fifo32_is_empty(&s->rx_fifo)) { in imx_spi_update_irq()
94 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR; in imx_spi_update_irq()
96 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RR; in imx_spi_update_irq()
99 if (fifo32_is_full(&s->rx_fifo)) { in imx_spi_update_irq()
100 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RF; in imx_spi_update_irq()
102 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF; in imx_spi_update_irq()
105 if (fifo32_is_empty(&s->tx_fifo)) { in imx_spi_update_irq()
106 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE; in imx_spi_update_irq()
108 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TE; in imx_spi_update_irq()
111 if (fifo32_is_full(&s->tx_fifo)) { in imx_spi_update_irq()
112 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TF; in imx_spi_update_irq()
114 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF; in imx_spi_update_irq()
117 level = s->regs[ECSPI_STATREG] & s->regs[ECSPI_INTREG] ? 1 : 0; in imx_spi_update_irq()
119 qemu_set_irq(s->irq, level); in imx_spi_update_irq()
126 return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_SELECT); in imx_spi_selected_channel()
131 uint32_t burst; in imx_spi_burst_length() local
133 burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; in imx_spi_burst_length()
134 if (burst % 8) { in imx_spi_burst_length()
135 burst = ROUND_UP(burst, 8); in imx_spi_burst_length()
138 return burst; in imx_spi_burst_length()
143 return s->regs[ECSPI_CONREG] & ECSPI_CONREG_EN; in imx_spi_is_enabled()
148 uint8_t mode = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_MODE); in imx_spi_channel_is_master()
155 uint8_t wave = EXTRACT(s->regs[ECSPI_CONFIGREG], ECSPI_CONFIGREG_SS_CTL); in imx_spi_is_multiple_master_burst()
158 !(s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC) && in imx_spi_is_multiple_master_burst()
168 fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo)); in imx_spi_flush_txfifo()
170 while (!fifo32_is_empty(&s->tx_fifo)) { in imx_spi_flush_txfifo()
173 if (s->burst_length <= 0) { in imx_spi_flush_txfifo()
174 s->burst_length = imx_spi_burst_length(s); in imx_spi_flush_txfifo()
176 DPRINTF("Burst length = %d\n", s->burst_length); in imx_spi_flush_txfifo()
179 s->regs[ECSPI_CONREG] |= ECSPI_CONREG_XCH; in imx_spi_flush_txfifo()
183 tx = fifo32_pop(&s->tx_fifo); in imx_spi_flush_txfifo()
187 tx_burst = (s->burst_length % 32) ? : 32; in imx_spi_flush_txfifo()
192 uint8_t byte = tx >> (tx_burst - 8); in imx_spi_flush_txfifo()
196 /* We need to write one byte at a time */ in imx_spi_flush_txfifo()
197 byte = ssi_transfer(s->bus, byte); in imx_spi_flush_txfifo()
203 /* Remove 8 bits from the actual burst */ in imx_spi_flush_txfifo()
204 tx_burst -= 8; in imx_spi_flush_txfifo()
205 s->burst_length -= 8; in imx_spi_flush_txfifo()
210 if (fifo32_is_full(&s->rx_fifo)) { in imx_spi_flush_txfifo()
211 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RO; in imx_spi_flush_txfifo()
213 fifo32_push(&s->rx_fifo, rx); in imx_spi_flush_txfifo()
216 if (s->burst_length <= 0) { in imx_spi_flush_txfifo()
218 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC; in imx_spi_flush_txfifo()
224 if (fifo32_is_empty(&s->tx_fifo)) { in imx_spi_flush_txfifo()
225 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC; in imx_spi_flush_txfifo()
226 s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH; in imx_spi_flush_txfifo()
232 fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo)); in imx_spi_flush_txfifo()
239 for (i = 0; i < ARRAY_SIZE(s->regs); i++) { in imx_spi_common_reset()
245 s->regs[i] = 0x00000003; in imx_spi_common_reset()
248 s->regs[i] = 0; in imx_spi_common_reset()
256 s->burst_length = 0; in imx_spi_common_reset()
268 qemu_set_irq(s->cs_lines[i], 1); in imx_spi_soft_reset()
277 s->regs[ECSPI_CONREG] = 0; in imx_spi_reset()
292 value = s->regs[index]; in imx_spi_read()
297 if (fifo32_is_empty(&s->rx_fifo)) { in imx_spi_read()
302 value = fifo32_pop(&s->rx_fifo); in imx_spi_read()
335 uint32_t burst; in imx_spi_write() local
354 change_mask = s->regs[index] ^ value; in imx_spi_write()
358 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to write to RX FIFO\n", in imx_spi_write()
362 if (fifo32_is_full(&s->tx_fifo)) { in imx_spi_write()
367 fifo32_push(&s->tx_fifo, (uint32_t)value); in imx_spi_write()
370 (s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC)) { in imx_spi_write()
380 /* the RO and TC bits are write-one-to-clear */ in imx_spi_write()
382 s->regs[ECSPI_STATREG] &= ~value; in imx_spi_write()
386 s->regs[ECSPI_CONREG] = value; in imx_spi_write()
388 burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; in imx_spi_write()
389 if (burst % 8) { in imx_spi_write()
391 … "[%s]%s: burst length %d not supported: rounding up to next multiple of 8\n", in imx_spi_write()
392 TYPE_IMX_SPI, __func__, burst); in imx_spi_write()
408 qemu_set_irq(s->cs_lines[i], in imx_spi_write()
413 !fifo32_is_empty(&s->tx_fifo)) { in imx_spi_write()
429 "[%s]%s: Trying to write to MSGDATA, ignoring\n", in imx_spi_write()
433 s->regs[index] = value; in imx_spi_write()
443 .write = imx_spi_write,
463 s->bus = ssi_create_bus(dev, "spi"); in imx_spi_realize()
465 memory_region_init_io(&s->iomem, OBJECT(dev), &imx_spi_ops, s, in imx_spi_realize()
467 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); in imx_spi_realize()
468 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); in imx_spi_realize()
471 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); in imx_spi_realize()
474 fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE); in imx_spi_realize()
475 fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE); in imx_spi_realize()
482 dc->realize = imx_spi_realize; in imx_spi_class_init()
483 dc->vmsd = &vmstate_imx_spi; in imx_spi_class_init()
485 dc->desc = "i.MX SPI Controller"; in imx_spi_class_init()