buffalo/lsxl/kwbimage-lschl.cfg

1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0:  0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0:   0 required
41 # bit11-7:  0 required
45 # bit17-15: 0 required
48 # bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
49 # bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
50 # bit30-28: 3 required
55 # bit3-0:   0xf, 16 cycle tRAS (tRAS[3-0])
56 # bit7-4:   4, 5 cycle tRCD
57 # bit11-8:  4, 5 cyle tRP
58 # bit15-12: 4, 5 cyle tWR
59 # bit19-16: 2, 3 cyle tWTR
61 # bit23-21: 0 required
62 # bit27-24: 3, 4 cycle tRRD
63 # bit31-28: 3, 4 cyle tRTP
67 # bit6-0:   0x23, 35 cycle tRFC
68 # bit8-7:   0, 1 cycle tR2R
69 # bit10-9:  0, 1 cyle tR2W
70 # bit12-11: 1, 2 cylce tW2W
71 # bit31-13: 0 required
75 # bit1-0:   1, Cs0width=x16
76 # bit3-2:   2, Cs0size=512Mbit
77 # bit5-4:   0, Cs1width=nonexistent
78 # bit7-6:   0, Cs1size=nonexistent
79 # bit9-8:   0, Cs2width=nonexistent
80 # bit11-10: 0, Cs2size=nonexistent
81 # bit13-12: 0, Cs3width=nonexistent
82 # bit15-14: 0, Cs3size=nonexistent
87 # bit31-20: 0 required
92 # bit31-1: 0 required
96 # bit3-0:   0, Cmd=Normal SDRAM Mode
97 # bit31-4:  0 required
101 # bit2-0:   2, Burst Length (2 required)
102 # bit3:     0, Burst Type (0 required)
103 # bit6-4:   5, CAS Latency (CL) 5
106 # bit11-9:  3, Write recovery for auto-precharge (3 required)
108 # bit31-13: 0 required
115 # bit5-3:   0 required
117 # bit9-7:   0 required
121 # bit31-13: 0 required
125 # bit2-0:   0x7 required
126 # bit3:     1, MBUS Burst Chop disabled
127 # bit6-4:   0x7 required
132 # bit11:    0, 1/4 clock cycle skew disabled for write mesh
133 # bit15-12: 0xf required
134 # bit31-16: 0 required
138 # bit3-0:   0 required
139 # bit7-4:   2, 2 cycles from read command to assertion of M_ODT signal
140 # bit11-8:  5, 5 cycles from read command to de-assertion of M_ODT signal
141 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
143 # bit31-20: 0 required
145 # DDR2 ODT Write Timing (default values)
147 # bit3-0:   2, 2 cycles from write comand to assertion of M_ODT signal
148 # bit7-4:   5, 5 cycles from write command to de-assertion of M_ODT signal
149 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
151 # bit31-16: 0 required
160 # bit1:     0, Write Protect disabled
161 # bit3-2:   0x0, CS0 hit selected
162 # bit23-4:  0xfffff required
163 # bit31-24: 0x03, Size (i.e. 64MB)
179 # bit3-0:   0b0000, (read) M_ODT[0] is not asserted during read from DRAM
180 # bit7-4:   0b0000, (read) M_ODT[1] is not asserted during read from DRAM
181 # bit15-8:  0 required
182 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
183 # bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1
184 # bit31-24: 0 required
188 # bit1-0:   0, M_ODT[0] assertion is controlled by ODT Control Low register
189 # bit3-2:   0, M_ODT[1] assertion is controlled by ODT Control Low register
190 # bit31-4   0 required
194 # bit3-0:   0b1111, internal ODT is asserted during read from DRAM bank 0-3
195 # bit7-4:   0b0000, internal ODT is not asserted during write to DRAM bank 0-3
196 # bit9-8:   0, Internal ODT assertion is controlled by fiels
197 # bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
198 # bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
201 # bit20-16: 0, Pad N channel driving strength for ODT
202 # bit25-21: 0, Pad P channel driving strength for ODT
203 # bit31-26: 0 required
207 # bit0:     1, enable DDR init upon this register write
208 # bit31-1:  0, required