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Searched +full:bias +full:- +full:ctrl +full:- +full:value (Results 1 – 11 of 11) sorted by relevance

/openbmc/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rockchip-core.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include "pinctrl-rockchip.h"
22 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_verify_config() local
24 if (bank >= ctrl->nr_banks) { in rockchip_verify_config()
25 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); in rockchip_verify_config()
26 return -EINVAL; in rockchip_verify_config()
32 return -EINVAL; in rockchip_verify_config()
41 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_get_recalced_mux()
42 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_get_recalced_mux() local
46 for (i = 0; i < ctrl->niomux_recalced; i++) { in rockchip_get_recalced_mux()
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/openbmc/u-boot/drivers/usb/host/
H A Dehci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (c) 2009-2015 NVIDIA Corporation
12 #include <asm-generic/gpio.h>
14 #include <asm/arch-tegra/usb.h>
15 #include <asm/arch-tegra/clk_rst.h>
39 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */
40 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */
41 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */
42 PARAM_STABLE_COUNT, /* PLL-U STABLE count */
43 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */
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H A Dxhci-exynos5.c1 // SPDX-License-Identifier: GPL-2.0+
11 * This file is a conglomeration for DWC3-init sequence and further
12 * exynos5 specific PHY-init sequence.
24 #include <asm/arch/xhci-exynos.h>
47 struct xhci_ctrl ctrl; member
56 const void *blob = gd->fdt_blob; in xhci_usb_ofdata_to_platdata()
63 plat->hcd_base = devfdt_get_addr(dev); in xhci_usb_ofdata_to_platdata()
64 if (plat->hcd_base == FDT_ADDR_T_NONE) { in xhci_usb_ofdata_to_platdata()
66 return -ENXIO; in xhci_usb_ofdata_to_platdata()
73 debug("XHCI: Can't get device node for usb3-phy controller\n"); in xhci_usb_ofdata_to_platdata()
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/openbmc/u-boot/drivers/video/
H A Dam335x-fb.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at>
4 * B&R Industrial Automation GmbH - http://www.br-automation.com
7 * Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
9 * - supporting 16/24/32bit RGB/TFT raster Mode (not using palette)
10 * - sets up LCD controller as in 'am335x_lcdpanel' struct given
11 * - starts output DMA from gd->fb_base buffer
20 #include "am335x-fb.h"
23 #error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
43 #define LCD_HBPLSB(x) ((((x)-1) & 0xFF) << 24)
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H A Dda8xx-fb.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Porting to u-boot:
8 * Copyright (C) 2008-2009 MontaVista Software Inc.
9 * Copyright (C) 2008-2009 Texas Instruments Inc
26 #include "da8xx-fb.h"
101 u32 ctrl; member
193 .height = -1,
194 .width = -1,
195 .pixclock = 46666, /* 46us - AUO display */
224 &da8xx_fb_reg_base->clk_reset); in lcd_enable_raster()
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/openbmc/u-boot/arch/arm/dts/
H A Dam335x-rut.dts6 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
12 /dts-v1/;
15 #include <dt-bindings/input/input.h>
19 compatible = "ti,am335x-evm", "ti,am33xx";
22 compatible = "pwm-beeper";
27 stdout-path = &uart0;
28 tick-timer = &timer2;
33 cpu0-supply = <&dcdc2_reg>;
37 gpio_keys: powerfail-keys {
38 compatible = "gpio-keys";
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H A Dam335x-evmsk.dts2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
14 /dts-v1/;
17 #include <dt-bindings/pwm/pwm.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
21 model = "TI AM335x EVM-SK";
22 compatible = "ti,am335x-evmsk", "ti,am33xx";
25 stdout-path = &uart0;
26 tick-timer = &timer2;
31 cpu0-supply = <&vdd1_reg>;
41 compatible = "regulator-fixed";
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H A Dam335x-evm.dts2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
15 compatible = "ti,am335x-evm", "ti,am33xx";
18 stdout-path = &uart0;
19 tick-timer = &timer2;
24 cpu0-supply = <&vdd1_reg>;
34 compatible = "regulator-fixed";
35 regulator-name = "vbat";
36 regulator-min-microvolt = <5000000>;
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/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dsoc.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/dma.h>
18 #include <asm/mach-imx/hab.h>
33 u32 ctrl; member
63 return readl(&scu->config) & 3; in get_nr_cpus()
69 u32 reg = readl(&anatop->digprog_sololite); in get_cpu_rev()
74 reg = readl(&anatop->digprog); in get_cpu_rev()
76 cfg = readl(&scu->config) & 3; in get_cpu_rev()
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/openbmc/u-boot/drivers/mmc/
H A Domap_hsmmc.c4 * Sukumar Ghorai <s-ghorai@ti.com>
22 * MA 02111-1307 USA
166 return dev_get_priv(mmc->dev); in omap_hsmmc_get_data()
168 return (struct omap_hsmmc_data *)mmc->priv; in omap_hsmmc_get_data()
174 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev); in omap_hsmmc_get_cfg()
175 return &plat->cfg; in omap_hsmmc_get_cfg()
177 return &((struct omap_hsmmc_data *)mmc->priv)->cfg; in omap_hsmmc_get_cfg()
188 return -1; in omap_mmc_setup_gpio_in()
213 pbias_lite = readl(&t2_base->pbias_lite); in mmc_board_init()
216 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */ in mmc_board_init()
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/openbmc/u-boot/arch/x86/cpu/quark/
H A Dsmc.c1 // SPDX-License-Identifier: Intel
82 tck = t_ck[mrc_params->ddr_speed]; /* Clock in picoseconds */ in prog_ddr_timing_control()
83 tcl = mrc_params->params.cl; /* CAS latency in clocks */ in prog_ddr_timing_control()
86 tras = MCEIL(mrc_params->params.ras, tck); in prog_ddr_timing_control()
88 /* Per JEDEC: tWR=15000ps DDR2/3 from 800-1600 */ in prog_ddr_timing_control()
91 twtr = MCEIL(mrc_params->params.wtr, tck); in prog_ddr_timing_control()
92 trrd = MCEIL(mrc_params->params.rrd, tck); in prog_ddr_timing_control()
94 tfaw = MCEIL(mrc_params->params.faw, tck); in prog_ddr_timing_control()
96 wl = 5 + mrc_params->ddr_speed; in prog_ddr_timing_control()
99 dtr0 |= mrc_params->ddr_speed; in prog_ddr_timing_control()
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