1 // SPDX-License-Identifier: GPL-2.0+
11  * This file is a conglomeration for DWC3-init sequence and further
12  * exynos5 specific PHY-init sequence.
24 #include <asm/arch/xhci-exynos.h>
47 	struct xhci_ctrl ctrl;  member
56 	const void *blob = gd->fdt_blob;  in xhci_usb_ofdata_to_platdata()
63 	plat->hcd_base = devfdt_get_addr(dev);  in xhci_usb_ofdata_to_platdata()
64 	if (plat->hcd_base == FDT_ADDR_T_NONE) {  in xhci_usb_ofdata_to_platdata()
66 		return -ENXIO;  in xhci_usb_ofdata_to_platdata()
73 		debug("XHCI: Can't get device node for usb3-phy controller\n");  in xhci_usb_ofdata_to_platdata()
74 		return -ENODEV;  in xhci_usb_ofdata_to_platdata()
80 	plat->phy_base = fdtdec_get_addr(blob, node, "reg");  in xhci_usb_ofdata_to_platdata()
81 	if (plat->phy_base == FDT_ADDR_T_NONE) {  in xhci_usb_ofdata_to_platdata()
83 		return -ENXIO;  in xhci_usb_ofdata_to_platdata()
87 	gpio_request_by_name(dev, "samsung,vbus-gpio", 0,  in xhci_usb_ofdata_to_platdata()
88 			     &plat->vbus_gpio, GPIOD_IS_OUT);  in xhci_usb_ofdata_to_platdata()
101 	writel(0x0, &phy->phy_reg0);  in exynos5_usb3_phy_init()
103 	clrbits_le32(&phy->phy_param0,  in exynos5_usb3_phy_init()
106 			/* Set Loss-of-Signal Detector sensitivity */  in exynos5_usb3_phy_init()
108 	setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL);  in exynos5_usb3_phy_init()
110 	writel(0x0, &phy->phy_resume);  in exynos5_usb3_phy_init()
113 	 * Setting the Frame length Adj value[6:1] to default 0x20  in exynos5_usb3_phy_init()
116 	setbits_le32(&phy->link_system,  in exynos5_usb3_phy_init()
120 	/* Set Tx De-Emphasis level */  in exynos5_usb3_phy_init()
121 	clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK);  in exynos5_usb3_phy_init()
122 	setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH);  in exynos5_usb3_phy_init()
124 	setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL);  in exynos5_usb3_phy_init()
127 	clrbits_le32(&phy->phy_test,  in exynos5_usb3_phy_init()
132 	writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi);  in exynos5_usb3_phy_init()
148 		/* Power down HS Bias and PLL blocks in suspend mode */  in exynos5_usb3_phy_init()
151 	writel(reg, &phy->phy_clk_rst);  in exynos5_usb3_phy_init()
157 	writel(reg, &phy->phy_clk_rst);  in exynos5_usb3_phy_init()
162 	setbits_le32(&phy->phy_utmi,  in exynos5_usb3_phy_exit()
167 	clrbits_le32(&phy->phy_clk_rst,  in exynos5_usb3_phy_exit()
173 	setbits_le32(&phy->phy_test,  in exynos5_usb3_phy_exit()
185 	exynos5_usb3_phy_init(exynos->usb3_phy);  in exynos_xhci_core_init()
187 	ret = dwc3_core_init(exynos->dwc3_reg);  in exynos_xhci_core_init()
190 		return -EINVAL;  in exynos_xhci_core_init()
193 	/* We are hard-coding DWC3 core to Host Mode */  in exynos_xhci_core_init()
194 	dwc3_set_mode(exynos->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);  in exynos_xhci_core_init()
201 	exynos5_usb3_phy_exit(exynos->usb3_phy);  in exynos_xhci_core_exit()
211 	ctx->hcd = (struct xhci_hccr *)plat->hcd_base;  in xhci_usb_probe()
212 	ctx->usb3_phy = (struct exynos_usb3_phy *)plat->phy_base;  in xhci_usb_probe()
213 	ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);  in xhci_usb_probe()
214 	hcor = (struct xhci_hcor *)((uint32_t)ctx->hcd +  in xhci_usb_probe()
215 			HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));  in xhci_usb_probe()
218 	if (dm_gpio_is_valid(&plat->vbus_gpio))  in xhci_usb_probe()
219 		dm_gpio_set_value(&plat->vbus_gpio, 1);  in xhci_usb_probe()
224 		return -EINVAL;  in xhci_usb_probe()
227 	return xhci_register(dev, ctx->hcd, hcor);  in xhci_usb_probe()
244 	{ .compatible = "samsung,exynos5250-xhci" },