1f5fbb83fSMauro Carvalho Chehab // SPDX-License-Identifier: GPL-2.0
2ad85094bSMauro Carvalho Chehab /*
3ad85094bSMauro Carvalho Chehab  * Support for GalaxyCore GC0310 VGA camera sensor.
4ad85094bSMauro Carvalho Chehab  *
5ad85094bSMauro Carvalho Chehab  * Copyright (c) 2013 Intel Corporation. All Rights Reserved.
62ec5bfe0SHans de Goede  * Copyright (c) 2023 Hans de Goede <hdegoede@redhat.com>
7ad85094bSMauro Carvalho Chehab  *
8ad85094bSMauro Carvalho Chehab  * This program is free software; you can redistribute it and/or
9ad85094bSMauro Carvalho Chehab  * modify it under the terms of the GNU General Public License version
10ad85094bSMauro Carvalho Chehab  * 2 as published by the Free Software Foundation.
11ad85094bSMauro Carvalho Chehab  *
12ad85094bSMauro Carvalho Chehab  * This program is distributed in the hope that it will be useful,
13ad85094bSMauro Carvalho Chehab  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14ad85094bSMauro Carvalho Chehab  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15ad85094bSMauro Carvalho Chehab  * GNU General Public License for more details.
16ad85094bSMauro Carvalho Chehab  *
17ad85094bSMauro Carvalho Chehab  */
18ad85094bSMauro Carvalho Chehab 
19ad85094bSMauro Carvalho Chehab #include <linux/delay.h>
2063558464SHans de Goede #include <linux/errno.h>
212ec5bfe0SHans de Goede #include <linux/gpio/consumer.h>
22ad85094bSMauro Carvalho Chehab #include <linux/i2c.h>
2363558464SHans de Goede #include <linux/kernel.h>
2463558464SHans de Goede #include <linux/module.h>
252726c899SHans de Goede #include <linux/pm_runtime.h>
2663558464SHans de Goede #include <linux/string.h>
2763558464SHans de Goede #include <linux/types.h>
28ad85094bSMauro Carvalho Chehab 
291bb2a551SHans de Goede #include <media/v4l2-ctrls.h>
3063558464SHans de Goede #include <media/v4l2-device.h>
3163558464SHans de Goede 
321bb2a551SHans de Goede #define GC0310_NATIVE_WIDTH			656
331bb2a551SHans de Goede #define GC0310_NATIVE_HEIGHT			496
341bb2a551SHans de Goede 
351bb2a551SHans de Goede #define GC0310_FPS				30
361bb2a551SHans de Goede #define GC0310_SKIP_FRAMES			3
371bb2a551SHans de Goede 
381bb2a551SHans de Goede #define GC0310_FOCAL_LENGTH_NUM			278 /* 2.78mm */
391bb2a551SHans de Goede 
401bb2a551SHans de Goede #define GC0310_ID				0xa310
411bb2a551SHans de Goede 
421bb2a551SHans de Goede #define GC0310_RESET_RELATED			0xFE
431bb2a551SHans de Goede #define GC0310_REGISTER_PAGE_0			0x0
441bb2a551SHans de Goede #define GC0310_REGISTER_PAGE_3			0x3
451bb2a551SHans de Goede 
461bb2a551SHans de Goede /*
471bb2a551SHans de Goede  * GC0310 System control registers
481bb2a551SHans de Goede  */
491bb2a551SHans de Goede #define GC0310_SW_STREAM			0x10
501bb2a551SHans de Goede 
511bb2a551SHans de Goede #define GC0310_SC_CMMN_CHIP_ID_H		0xf0
521bb2a551SHans de Goede #define GC0310_SC_CMMN_CHIP_ID_L		0xf1
531bb2a551SHans de Goede 
541bb2a551SHans de Goede #define GC0310_AEC_PK_EXPO_H			0x03
551bb2a551SHans de Goede #define GC0310_AEC_PK_EXPO_L			0x04
561bb2a551SHans de Goede #define GC0310_AGC_ADJ				0x48
571bb2a551SHans de Goede #define GC0310_DGC_ADJ				0x71
581bb2a551SHans de Goede #define GC0310_GROUP_ACCESS			0x3208
591bb2a551SHans de Goede 
601bb2a551SHans de Goede #define GC0310_H_CROP_START_H			0x09
611bb2a551SHans de Goede #define GC0310_H_CROP_START_L			0x0A
621bb2a551SHans de Goede #define GC0310_V_CROP_START_H			0x0B
631bb2a551SHans de Goede #define GC0310_V_CROP_START_L			0x0C
641bb2a551SHans de Goede #define GC0310_H_OUTSIZE_H			0x0F
651bb2a551SHans de Goede #define GC0310_H_OUTSIZE_L			0x10
661bb2a551SHans de Goede #define GC0310_V_OUTSIZE_H			0x0D
671bb2a551SHans de Goede #define GC0310_V_OUTSIZE_L			0x0E
681bb2a551SHans de Goede #define GC0310_H_BLANKING_H			0x05
691bb2a551SHans de Goede #define GC0310_H_BLANKING_L			0x06
701bb2a551SHans de Goede #define GC0310_V_BLANKING_H			0x07
711bb2a551SHans de Goede #define GC0310_V_BLANKING_L			0x08
721bb2a551SHans de Goede #define GC0310_SH_DELAY				0x11
731bb2a551SHans de Goede 
741bb2a551SHans de Goede #define GC0310_START_STREAMING			0x94 /* 8-bit enable */
751bb2a551SHans de Goede #define GC0310_STOP_STREAMING			0x0 /* 8-bit disable */
761bb2a551SHans de Goede 
771bb2a551SHans de Goede #define to_gc0310_sensor(x) container_of(x, struct gc0310_device, sd)
781bb2a551SHans de Goede 
791bb2a551SHans de Goede struct gc0310_device {
801bb2a551SHans de Goede 	struct v4l2_subdev sd;
811bb2a551SHans de Goede 	struct media_pad pad;
821bb2a551SHans de Goede 	/* Protect against concurrent changes to controls */
831bb2a551SHans de Goede 	struct mutex input_lock;
841bb2a551SHans de Goede 	bool is_streaming;
851bb2a551SHans de Goede 
86*1aace3daSHans de Goede 	struct fwnode_handle *ep_fwnode;
871bb2a551SHans de Goede 	struct gpio_desc *reset;
881bb2a551SHans de Goede 	struct gpio_desc *powerdown;
891bb2a551SHans de Goede 
901bb2a551SHans de Goede 	struct gc0310_mode {
911bb2a551SHans de Goede 		struct v4l2_mbus_framefmt fmt;
921bb2a551SHans de Goede 	} mode;
931bb2a551SHans de Goede 
941bb2a551SHans de Goede 	struct gc0310_ctrls {
951bb2a551SHans de Goede 		struct v4l2_ctrl_handler handler;
961bb2a551SHans de Goede 		struct v4l2_ctrl *exposure;
971bb2a551SHans de Goede 		struct v4l2_ctrl *gain;
981bb2a551SHans de Goede 	} ctrls;
991bb2a551SHans de Goede };
1001bb2a551SHans de Goede 
1011bb2a551SHans de Goede struct gc0310_reg {
1021bb2a551SHans de Goede 	u8 reg;
1031bb2a551SHans de Goede 	u8 val;
1041bb2a551SHans de Goede };
1051bb2a551SHans de Goede 
1061bb2a551SHans de Goede static const struct gc0310_reg gc0310_reset_register[] = {
1071bb2a551SHans de Goede 	/* System registers */
1081bb2a551SHans de Goede 	{ 0xfe, 0xf0 },
1091bb2a551SHans de Goede 	{ 0xfe, 0xf0 },
1101bb2a551SHans de Goede 	{ 0xfe, 0x00 },
1111bb2a551SHans de Goede 
1121bb2a551SHans de Goede 	{ 0xfc, 0x0e }, /* 4e */
1131bb2a551SHans de Goede 	{ 0xfc, 0x0e }, /* 16//4e // [0]apwd [6]regf_clk_gate */
1141bb2a551SHans de Goede 	{ 0xf2, 0x80 }, /* sync output */
1151bb2a551SHans de Goede 	{ 0xf3, 0x00 }, /* 1f//01 data output */
1161bb2a551SHans de Goede 	{ 0xf7, 0x33 }, /* f9 */
1171bb2a551SHans de Goede 	{ 0xf8, 0x05 }, /* 00 */
1181bb2a551SHans de Goede 	{ 0xf9, 0x0e }, /* 0x8e //0f */
1191bb2a551SHans de Goede 	{ 0xfa, 0x11 },
1201bb2a551SHans de Goede 
1211bb2a551SHans de Goede 	/* MIPI */
1221bb2a551SHans de Goede 	{ 0xfe, 0x03 },
1231bb2a551SHans de Goede 	{ 0x01, 0x03 }, /* mipi 1lane */
1241bb2a551SHans de Goede 	{ 0x02, 0x22 }, /* 0x33 */
1251bb2a551SHans de Goede 	{ 0x03, 0x94 },
1261bb2a551SHans de Goede 	{ 0x04, 0x01 }, /* fifo_prog */
1271bb2a551SHans de Goede 	{ 0x05, 0x00 }, /* fifo_prog */
1281bb2a551SHans de Goede 	{ 0x06, 0x80 }, /* b0  //YUV ISP data */
1291bb2a551SHans de Goede 	{ 0x11, 0x2a }, /* 1e //LDI set YUV422 */
1301bb2a551SHans de Goede 	{ 0x12, 0x90 }, /* 00 //04 //00 //04//00 //LWC[7:0] */
1311bb2a551SHans de Goede 	{ 0x13, 0x02 }, /* 05 //05 //LWC[15:8] */
1321bb2a551SHans de Goede 	{ 0x15, 0x12 }, /* 0x10 //DPHYY_MODE read_ready */
1331bb2a551SHans de Goede 	{ 0x17, 0x01 },
1341bb2a551SHans de Goede 	{ 0x40, 0x08 },
1351bb2a551SHans de Goede 	{ 0x41, 0x00 },
1361bb2a551SHans de Goede 	{ 0x42, 0x00 },
1371bb2a551SHans de Goede 	{ 0x43, 0x00 },
1381bb2a551SHans de Goede 	{ 0x21, 0x02 }, /* 0x01 */
1391bb2a551SHans de Goede 	{ 0x22, 0x02 }, /* 0x01 */
1401bb2a551SHans de Goede 	{ 0x23, 0x01 }, /* 0x05 //Nor:0x05 DOU:0x06 */
1411bb2a551SHans de Goede 	{ 0x29, 0x00 },
1421bb2a551SHans de Goede 	{ 0x2A, 0x25 }, /* 0x05 //data zero 0x7a de */
1431bb2a551SHans de Goede 	{ 0x2B, 0x02 },
1441bb2a551SHans de Goede 
1451bb2a551SHans de Goede 	{ 0xfe, 0x00 },
1461bb2a551SHans de Goede 
1471bb2a551SHans de Goede 	/* CISCTL */
1481bb2a551SHans de Goede 	{ 0x00, 0x2f }, /* 2f//0f//02//01 */
1491bb2a551SHans de Goede 	{ 0x01, 0x0f }, /* 06 */
1501bb2a551SHans de Goede 	{ 0x02, 0x04 },
1511bb2a551SHans de Goede 	{ 0x4f, 0x00 }, /* AEC 0FF */
1521bb2a551SHans de Goede 	{ 0x03, 0x01 }, /* 0x03 //04 */
1531bb2a551SHans de Goede 	{ 0x04, 0xc0 }, /* 0xe8 //58 */
1541bb2a551SHans de Goede 	{ 0x05, 0x00 },
1551bb2a551SHans de Goede 	{ 0x06, 0xb2 }, /* 0x0a //HB */
1561bb2a551SHans de Goede 	{ 0x07, 0x00 },
1571bb2a551SHans de Goede 	{ 0x08, 0x0c }, /* 0x89 //VB */
1581bb2a551SHans de Goede 	{ 0x09, 0x00 }, /* row start */
1591bb2a551SHans de Goede 	{ 0x0a, 0x00 },
1601bb2a551SHans de Goede 	{ 0x0b, 0x00 }, /* col start */
1611bb2a551SHans de Goede 	{ 0x0c, 0x00 },
1621bb2a551SHans de Goede 	{ 0x0d, 0x01 }, /* height */
1631bb2a551SHans de Goede 	{ 0x0e, 0xf2 }, /* 0xf7 //height */
1641bb2a551SHans de Goede 	{ 0x0f, 0x02 }, /* width */
1651bb2a551SHans de Goede 	{ 0x10, 0x94 }, /* 0xa0 //height */
1661bb2a551SHans de Goede 	{ 0x17, 0x14 },
1671bb2a551SHans de Goede 	{ 0x18, 0x1a }, /* 0a//[4]double reset */
1681bb2a551SHans de Goede 	{ 0x19, 0x14 }, /* AD pipeline */
1691bb2a551SHans de Goede 	{ 0x1b, 0x48 },
1701bb2a551SHans de Goede 	{ 0x1e, 0x6b }, /* 3b//col bias */
1711bb2a551SHans de Goede 	{ 0x1f, 0x28 }, /* 20//00//08//txlow */
1721bb2a551SHans de Goede 	{ 0x20, 0x89 }, /* 88//0c//[3:2]DA15 */
1731bb2a551SHans de Goede 	{ 0x21, 0x49 }, /* 48//[3] txhigh */
1741bb2a551SHans de Goede 	{ 0x22, 0xb0 },
1751bb2a551SHans de Goede 	{ 0x23, 0x04 }, /* [1:0]vcm_r */
1761bb2a551SHans de Goede 	{ 0x24, 0x16 }, /* 15 */
1771bb2a551SHans de Goede 	{ 0x34, 0x20 }, /* [6:4] rsg high//range */
1781bb2a551SHans de Goede 
1791bb2a551SHans de Goede 	/* BLK */
1801bb2a551SHans de Goede 	{ 0x26, 0x23 }, /* [1]dark_current_en [0]offset_en */
1811bb2a551SHans de Goede 	{ 0x28, 0xff }, /* BLK_limie_value */
1821bb2a551SHans de Goede 	{ 0x29, 0x00 }, /* global offset */
1831bb2a551SHans de Goede 	{ 0x33, 0x18 }, /* offset_ratio */
1841bb2a551SHans de Goede 	{ 0x37, 0x20 }, /* dark_current_ratio */
1851bb2a551SHans de Goede 	{ 0x2a, 0x00 },
1861bb2a551SHans de Goede 	{ 0x2b, 0x00 },
1871bb2a551SHans de Goede 	{ 0x2c, 0x00 },
1881bb2a551SHans de Goede 	{ 0x2d, 0x00 },
1891bb2a551SHans de Goede 	{ 0x2e, 0x00 },
1901bb2a551SHans de Goede 	{ 0x2f, 0x00 },
1911bb2a551SHans de Goede 	{ 0x30, 0x00 },
1921bb2a551SHans de Goede 	{ 0x31, 0x00 },
1931bb2a551SHans de Goede 	{ 0x47, 0x80 }, /* a7 */
1941bb2a551SHans de Goede 	{ 0x4e, 0x66 }, /* select_row */
1951bb2a551SHans de Goede 	{ 0xa8, 0x02 }, /* win_width_dark, same with crop_win_width */
1961bb2a551SHans de Goede 	{ 0xa9, 0x80 },
1971bb2a551SHans de Goede 
1981bb2a551SHans de Goede 	/* ISP */
1991bb2a551SHans de Goede 	{ 0x40, 0x06 }, /* 0xff //ff //48 */
2001bb2a551SHans de Goede 	{ 0x41, 0x00 }, /* 0x21 //00//[0]curve_en */
2011bb2a551SHans de Goede 	{ 0x42, 0x04 }, /* 0xcf //0a//[1]awn_en */
2021bb2a551SHans de Goede 	{ 0x44, 0x18 }, /* 0x18 //02 */
2031bb2a551SHans de Goede 	{ 0x46, 0x02 }, /* 0x03 //sync */
2041bb2a551SHans de Goede 	{ 0x49, 0x03 },
2051bb2a551SHans de Goede 	{ 0x4c, 0x20 }, /* 00[5]pretect exp */
2061bb2a551SHans de Goede 	{ 0x50, 0x01 }, /* crop enable */
2071bb2a551SHans de Goede 	{ 0x51, 0x00 },
2081bb2a551SHans de Goede 	{ 0x52, 0x00 },
2091bb2a551SHans de Goede 	{ 0x53, 0x00 },
2101bb2a551SHans de Goede 	{ 0x54, 0x01 },
2111bb2a551SHans de Goede 	{ 0x55, 0x01 }, /* crop window height */
2121bb2a551SHans de Goede 	{ 0x56, 0xf0 },
2131bb2a551SHans de Goede 	{ 0x57, 0x02 }, /* crop window width */
2141bb2a551SHans de Goede 	{ 0x58, 0x90 },
2151bb2a551SHans de Goede 
2161bb2a551SHans de Goede 	/* Gain */
2171bb2a551SHans de Goede 	{ 0x70, 0x70 }, /* 70 //80//global gain */
2181bb2a551SHans de Goede 	{ 0x71, 0x20 }, /* pregain gain */
2191bb2a551SHans de Goede 	{ 0x72, 0x40 }, /* post gain */
2201bb2a551SHans de Goede 	{ 0x5a, 0x84 }, /* 84//analog gain 0  */
2211bb2a551SHans de Goede 	{ 0x5b, 0xc9 }, /* c9 */
2221bb2a551SHans de Goede 	{ 0x5c, 0xed }, /* ed//not use pga gain highest level */
2231bb2a551SHans de Goede 	{ 0x77, 0x40 }, /* R gain 0x74 //awb gain */
2241bb2a551SHans de Goede 	{ 0x78, 0x40 }, /* G gain */
2251bb2a551SHans de Goede 	{ 0x79, 0x40 }, /* B gain 0x5f */
2261bb2a551SHans de Goede 
2271bb2a551SHans de Goede 	{ 0x48, 0x00 },
2281bb2a551SHans de Goede 	{ 0xfe, 0x01 },
2291bb2a551SHans de Goede 	{ 0x0a, 0x45 }, /* [7]col gain mode */
2301bb2a551SHans de Goede 
2311bb2a551SHans de Goede 	{ 0x3e, 0x40 },
2321bb2a551SHans de Goede 	{ 0x3f, 0x5c },
2331bb2a551SHans de Goede 	{ 0x40, 0x7b },
2341bb2a551SHans de Goede 	{ 0x41, 0xbd },
2351bb2a551SHans de Goede 	{ 0x42, 0xf6 },
2361bb2a551SHans de Goede 	{ 0x43, 0x63 },
2371bb2a551SHans de Goede 	{ 0x03, 0x60 },
2381bb2a551SHans de Goede 	{ 0x44, 0x03 },
2391bb2a551SHans de Goede 
2401bb2a551SHans de Goede 	/* Dark / Sun mode related */
2411bb2a551SHans de Goede 	{ 0xfe, 0x01 },
2421bb2a551SHans de Goede 	{ 0x45, 0xa4 }, /* 0xf7 */
2431bb2a551SHans de Goede 	{ 0x46, 0xf0 }, /* 0xff //f0//sun value th */
2441bb2a551SHans de Goede 	{ 0x48, 0x03 }, /* sun mode */
2451bb2a551SHans de Goede 	{ 0x4f, 0x60 }, /* sun_clamp */
2461bb2a551SHans de Goede 	{ 0xfe, 0x00 },
2471bb2a551SHans de Goede };
2481bb2a551SHans de Goede 
2491bb2a551SHans de Goede static const struct gc0310_reg gc0310_VGA_30fps[] = {
2501bb2a551SHans de Goede 	{ 0xfe, 0x00 },
2511bb2a551SHans de Goede 	{ 0x0d, 0x01 }, /* height */
2521bb2a551SHans de Goede 	{ 0x0e, 0xf2 }, /* 0xf7 //height */
2531bb2a551SHans de Goede 	{ 0x0f, 0x02 }, /* width */
2541bb2a551SHans de Goede 	{ 0x10, 0x94 }, /* 0xa0 //height */
2551bb2a551SHans de Goede 
2561bb2a551SHans de Goede 	{ 0x50, 0x01 }, /* crop enable */
2571bb2a551SHans de Goede 	{ 0x51, 0x00 },
2581bb2a551SHans de Goede 	{ 0x52, 0x00 },
2591bb2a551SHans de Goede 	{ 0x53, 0x00 },
2601bb2a551SHans de Goede 	{ 0x54, 0x01 },
2611bb2a551SHans de Goede 	{ 0x55, 0x01 }, /* crop window height */
2621bb2a551SHans de Goede 	{ 0x56, 0xf0 },
2631bb2a551SHans de Goede 	{ 0x57, 0x02 }, /* crop window width */
2641bb2a551SHans de Goede 	{ 0x58, 0x90 },
2651bb2a551SHans de Goede 
2661bb2a551SHans de Goede 	{ 0xfe, 0x03 },
2671bb2a551SHans de Goede 	{ 0x12, 0x90 }, /* 00 //04 //00 //04//00 //LWC[7:0]  */
2681bb2a551SHans de Goede 	{ 0x13, 0x02 }, /* 05 //05 //LWC[15:8] */
2691bb2a551SHans de Goede 
2701bb2a551SHans de Goede 	{ 0xfe, 0x00 },
2711bb2a551SHans de Goede };
272ad85094bSMauro Carvalho Chehab 
273ad85094bSMauro Carvalho Chehab /*
274ad85094bSMauro Carvalho Chehab  * gc0310_write_reg_array - Initializes a list of GC0310 registers
275ad85094bSMauro Carvalho Chehab  * @client: i2c driver client structure
276ad85094bSMauro Carvalho Chehab  * @reglist: list of registers to be written
277bfe06aeeSHans de Goede  * @count: number of register, value pairs in the list
278ad85094bSMauro Carvalho Chehab  */
gc0310_write_reg_array(struct i2c_client * client,const struct gc0310_reg * reglist,int count)279ad85094bSMauro Carvalho Chehab static int gc0310_write_reg_array(struct i2c_client *client,
280bfe06aeeSHans de Goede 				  const struct gc0310_reg *reglist, int count)
281ad85094bSMauro Carvalho Chehab {
282bfe06aeeSHans de Goede 	int i, err;
283ad85094bSMauro Carvalho Chehab 
284bfe06aeeSHans de Goede 	for (i = 0; i < count; i++) {
28565e5ef2fSHans de Goede 		err = i2c_smbus_write_byte_data(client, reglist[i].reg, reglist[i].val);
28665e5ef2fSHans de Goede 		if (err) {
28765e5ef2fSHans de Goede 			dev_err(&client->dev, "write error: wrote 0x%x to offset 0x%x error %d",
28865e5ef2fSHans de Goede 				reglist[i].val, reglist[i].reg, err);
289ad85094bSMauro Carvalho Chehab 			return err;
290ad85094bSMauro Carvalho Chehab 		}
29165e5ef2fSHans de Goede 	}
292ad85094bSMauro Carvalho Chehab 
293e1a4b3a7SHans de Goede 	return 0;
294ad85094bSMauro Carvalho Chehab }
295bdfe0bebSMauro Carvalho Chehab 
gc0310_exposure_set(struct gc0310_device * dev,u32 exp)296ef5fb5d4SHans de Goede static int gc0310_exposure_set(struct gc0310_device *dev, u32 exp)
297ef5fb5d4SHans de Goede {
298ef5fb5d4SHans de Goede 	struct i2c_client *client = v4l2_get_subdevdata(&dev->sd);
299ef5fb5d4SHans de Goede 
300ef5fb5d4SHans de Goede 	return i2c_smbus_write_word_swapped(client, GC0310_AEC_PK_EXPO_H, exp);
301ef5fb5d4SHans de Goede }
302ef5fb5d4SHans de Goede 
gc0310_gain_set(struct gc0310_device * dev,u32 gain)303ef5fb5d4SHans de Goede static int gc0310_gain_set(struct gc0310_device *dev, u32 gain)
304ef5fb5d4SHans de Goede {
305ef5fb5d4SHans de Goede 	struct i2c_client *client = v4l2_get_subdevdata(&dev->sd);
306ef5fb5d4SHans de Goede 	u8 again, dgain;
307ef5fb5d4SHans de Goede 	int ret;
308ef5fb5d4SHans de Goede 
309ef5fb5d4SHans de Goede 	/* Taken from original driver, this never sets dgain lower then 32? */
310ef5fb5d4SHans de Goede 
311ef5fb5d4SHans de Goede 	/* Change 0 - 95 to 32 - 127 */
312ef5fb5d4SHans de Goede 	gain += 32;
313ef5fb5d4SHans de Goede 
314ef5fb5d4SHans de Goede 	if (gain < 64) {
315ef5fb5d4SHans de Goede 		again = 0x0; /* sqrt(2) */
316ef5fb5d4SHans de Goede 		dgain = gain;
317ef5fb5d4SHans de Goede 	} else {
318ef5fb5d4SHans de Goede 		again = 0x2; /* 2 * sqrt(2) */
319ef5fb5d4SHans de Goede 		dgain = gain / 2;
320ef5fb5d4SHans de Goede 	}
321ef5fb5d4SHans de Goede 
322ef5fb5d4SHans de Goede 	ret = i2c_smbus_write_byte_data(client, GC0310_AGC_ADJ, again);
323ef5fb5d4SHans de Goede 	if (ret)
324ef5fb5d4SHans de Goede 		return ret;
325ef5fb5d4SHans de Goede 
326ef5fb5d4SHans de Goede 	return i2c_smbus_write_byte_data(client, GC0310_DGC_ADJ, dgain);
327ef5fb5d4SHans de Goede }
328ef5fb5d4SHans de Goede 
gc0310_s_ctrl(struct v4l2_ctrl * ctrl)329ad85094bSMauro Carvalho Chehab static int gc0310_s_ctrl(struct v4l2_ctrl *ctrl)
330ad85094bSMauro Carvalho Chehab {
331ef5fb5d4SHans de Goede 	struct gc0310_device *dev =
332ef5fb5d4SHans de Goede 		container_of(ctrl->handler, struct gc0310_device, ctrls.handler);
333ef5fb5d4SHans de Goede 	int ret;
334ef5fb5d4SHans de Goede 
3352726c899SHans de Goede 	/* Only apply changes to the controls if the device is powered up */
3362726c899SHans de Goede 	if (!pm_runtime_get_if_in_use(dev->sd.dev))
337ef5fb5d4SHans de Goede 		return 0;
338ad85094bSMauro Carvalho Chehab 
339ad85094bSMauro Carvalho Chehab 	switch (ctrl->id) {
340ef5fb5d4SHans de Goede 	case V4L2_CID_EXPOSURE:
341ef5fb5d4SHans de Goede 		ret = gc0310_exposure_set(dev, ctrl->val);
342ef5fb5d4SHans de Goede 		break;
343ef5fb5d4SHans de Goede 	case V4L2_CID_GAIN:
344ef5fb5d4SHans de Goede 		ret = gc0310_gain_set(dev, ctrl->val);
345ef5fb5d4SHans de Goede 		break;
346ad85094bSMauro Carvalho Chehab 	default:
347ad85094bSMauro Carvalho Chehab 		ret = -EINVAL;
348ef5fb5d4SHans de Goede 		break;
349ad85094bSMauro Carvalho Chehab 	}
350ef5fb5d4SHans de Goede 
3512726c899SHans de Goede 	pm_runtime_put(dev->sd.dev);
352ad85094bSMauro Carvalho Chehab 	return ret;
353ad85094bSMauro Carvalho Chehab }
354ad85094bSMauro Carvalho Chehab 
355ad85094bSMauro Carvalho Chehab static const struct v4l2_ctrl_ops ctrl_ops = {
356ad85094bSMauro Carvalho Chehab 	.s_ctrl = gc0310_s_ctrl,
357ad85094bSMauro Carvalho Chehab };
358ad85094bSMauro Carvalho Chehab 
3599783b96aSHans de Goede static struct v4l2_mbus_framefmt *
gc0310_get_pad_format(struct gc0310_device * dev,struct v4l2_subdev_state * state,unsigned int pad,enum v4l2_subdev_format_whence which)3609783b96aSHans de Goede gc0310_get_pad_format(struct gc0310_device *dev,
3619783b96aSHans de Goede 		      struct v4l2_subdev_state *state,
3629783b96aSHans de Goede 		      unsigned int pad, enum v4l2_subdev_format_whence which)
363ad85094bSMauro Carvalho Chehab {
3649783b96aSHans de Goede 	if (which == V4L2_SUBDEV_FORMAT_TRY)
3659783b96aSHans de Goede 		return v4l2_subdev_get_try_format(&dev->sd, state, pad);
366ad85094bSMauro Carvalho Chehab 
3679783b96aSHans de Goede 	return &dev->mode.fmt;
368ad85094bSMauro Carvalho Chehab }
369ad85094bSMauro Carvalho Chehab 
3709783b96aSHans de Goede /* The GC0310 currently only supports 1 fixed fmt */
gc0310_fill_format(struct v4l2_mbus_framefmt * fmt)3719783b96aSHans de Goede static void gc0310_fill_format(struct v4l2_mbus_framefmt *fmt)
3729783b96aSHans de Goede {
3739783b96aSHans de Goede 	memset(fmt, 0, sizeof(*fmt));
3749783b96aSHans de Goede 	fmt->width = GC0310_NATIVE_WIDTH;
3759783b96aSHans de Goede 	fmt->height = GC0310_NATIVE_HEIGHT;
3769783b96aSHans de Goede 	fmt->field = V4L2_FIELD_NONE;
3779783b96aSHans de Goede 	fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8;
378ad85094bSMauro Carvalho Chehab }
379ad85094bSMauro Carvalho Chehab 
gc0310_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)380ad85094bSMauro Carvalho Chehab static int gc0310_set_fmt(struct v4l2_subdev *sd,
3810d346d2aSTomi Valkeinen 			  struct v4l2_subdev_state *sd_state,
382ad85094bSMauro Carvalho Chehab 			  struct v4l2_subdev_format *format)
383ad85094bSMauro Carvalho Chehab {
3849783b96aSHans de Goede 	struct gc0310_device *dev = to_gc0310_sensor(sd);
3859783b96aSHans de Goede 	struct v4l2_mbus_framefmt *fmt;
386bdfe0bebSMauro Carvalho Chehab 
3879783b96aSHans de Goede 	fmt = gc0310_get_pad_format(dev, sd_state, format->pad, format->which);
3889783b96aSHans de Goede 	gc0310_fill_format(fmt);
389ad85094bSMauro Carvalho Chehab 
3909783b96aSHans de Goede 	format->format = *fmt;
3919783b96aSHans de Goede 	return 0;
392ad85094bSMauro Carvalho Chehab }
393ad85094bSMauro Carvalho Chehab 
gc0310_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)394ad85094bSMauro Carvalho Chehab static int gc0310_get_fmt(struct v4l2_subdev *sd,
3950d346d2aSTomi Valkeinen 			  struct v4l2_subdev_state *sd_state,
396ad85094bSMauro Carvalho Chehab 			  struct v4l2_subdev_format *format)
397ad85094bSMauro Carvalho Chehab {
398ad85094bSMauro Carvalho Chehab 	struct gc0310_device *dev = to_gc0310_sensor(sd);
3999783b96aSHans de Goede 	struct v4l2_mbus_framefmt *fmt;
400ad85094bSMauro Carvalho Chehab 
4019783b96aSHans de Goede 	fmt = gc0310_get_pad_format(dev, sd_state, format->pad, format->which);
4029783b96aSHans de Goede 	format->format = *fmt;
403ad85094bSMauro Carvalho Chehab 	return 0;
404ad85094bSMauro Carvalho Chehab }
405ad85094bSMauro Carvalho Chehab 
gc0310_detect(struct i2c_client * client)406ad85094bSMauro Carvalho Chehab static int gc0310_detect(struct i2c_client *client)
407ad85094bSMauro Carvalho Chehab {
408ad85094bSMauro Carvalho Chehab 	struct i2c_adapter *adapter = client->adapter;
409ad85094bSMauro Carvalho Chehab 	int ret;
410ad85094bSMauro Carvalho Chehab 
411ad85094bSMauro Carvalho Chehab 	if (!i2c_check_functionality(adapter, I2C_FUNC_I2C))
412ad85094bSMauro Carvalho Chehab 		return -ENODEV;
413ad85094bSMauro Carvalho Chehab 
414f5e381ffSHans de Goede 	ret = pm_runtime_get_sync(&client->dev);
415f5e381ffSHans de Goede 	if (ret >= 0)
41665e5ef2fSHans de Goede 		ret = i2c_smbus_read_word_swapped(client, GC0310_SC_CMMN_CHIP_ID_H);
417f5e381ffSHans de Goede 	pm_runtime_put(&client->dev);
41865e5ef2fSHans de Goede 	if (ret < 0) {
41965e5ef2fSHans de Goede 		dev_err(&client->dev, "read sensor_id failed: %d\n", ret);
420ad85094bSMauro Carvalho Chehab 		return -ENODEV;
421ad85094bSMauro Carvalho Chehab 	}
422ad85094bSMauro Carvalho Chehab 
42365e5ef2fSHans de Goede 	dev_dbg(&client->dev, "sensor ID = 0x%x\n", ret);
42465e5ef2fSHans de Goede 
42565e5ef2fSHans de Goede 	if (ret != GC0310_ID) {
42665e5ef2fSHans de Goede 		dev_err(&client->dev, "sensor ID error, read id = 0x%x, target id = 0x%x\n",
42765e5ef2fSHans de Goede 			ret, GC0310_ID);
428ad85094bSMauro Carvalho Chehab 		return -ENODEV;
429ad85094bSMauro Carvalho Chehab 	}
430ad85094bSMauro Carvalho Chehab 
431ad85094bSMauro Carvalho Chehab 	dev_dbg(&client->dev, "detect gc0310 success\n");
432ad85094bSMauro Carvalho Chehab 
433ad85094bSMauro Carvalho Chehab 	return 0;
434ad85094bSMauro Carvalho Chehab }
435ad85094bSMauro Carvalho Chehab 
gc0310_s_stream(struct v4l2_subdev * sd,int enable)436ad85094bSMauro Carvalho Chehab static int gc0310_s_stream(struct v4l2_subdev *sd, int enable)
437ad85094bSMauro Carvalho Chehab {
438ad85094bSMauro Carvalho Chehab 	struct gc0310_device *dev = to_gc0310_sensor(sd);
439ad85094bSMauro Carvalho Chehab 	struct i2c_client *client = v4l2_get_subdevdata(sd);
4402726c899SHans de Goede 	int ret = 0;
441ad85094bSMauro Carvalho Chehab 
4422dfc978aSDeepak R Varma 	dev_dbg(&client->dev, "%s S enable=%d\n", __func__, enable);
443ad85094bSMauro Carvalho Chehab 	mutex_lock(&dev->input_lock);
444ad85094bSMauro Carvalho Chehab 
4452726c899SHans de Goede 	if (dev->is_streaming == enable) {
4462726c899SHans de Goede 		dev_warn(&client->dev, "stream already %s\n", enable ? "started" : "stopped");
447b6763b22SHans de Goede 		goto error_unlock;
4482726c899SHans de Goede 	}
4492726c899SHans de Goede 
4502726c899SHans de Goede 	if (enable) {
4512726c899SHans de Goede 		ret = pm_runtime_get_sync(&client->dev);
4522726c899SHans de Goede 		if (ret < 0)
4532726c899SHans de Goede 			goto error_power_down;
454b6763b22SHans de Goede 
4552ec5bfe0SHans de Goede 		msleep(100);
4562ec5bfe0SHans de Goede 
457b6763b22SHans de Goede 		ret = gc0310_write_reg_array(client, gc0310_reset_register,
458b6763b22SHans de Goede 					     ARRAY_SIZE(gc0310_reset_register));
459b6763b22SHans de Goede 		if (ret)
460b6763b22SHans de Goede 			goto error_power_down;
461b6763b22SHans de Goede 
462b6763b22SHans de Goede 		ret = gc0310_write_reg_array(client, gc0310_VGA_30fps,
463b6763b22SHans de Goede 					     ARRAY_SIZE(gc0310_VGA_30fps));
464b6763b22SHans de Goede 		if (ret)
465b6763b22SHans de Goede 			goto error_power_down;
466b6763b22SHans de Goede 
467b6763b22SHans de Goede 		/* restore value of all ctrls */
468b6763b22SHans de Goede 		ret = __v4l2_ctrl_handler_setup(&dev->ctrls.handler);
469b6763b22SHans de Goede 		if (ret)
470b6763b22SHans de Goede 			goto error_power_down;
471b6763b22SHans de Goede 
472ad85094bSMauro Carvalho Chehab 		/* enable per frame MIPI and sensor ctrl reset  */
47365e5ef2fSHans de Goede 		ret = i2c_smbus_write_byte_data(client, 0xFE, 0x30);
4742b2297b1SHans de Goede 		if (ret)
475b6763b22SHans de Goede 			goto error_power_down;
476ad85094bSMauro Carvalho Chehab 	}
477ad85094bSMauro Carvalho Chehab 
47865e5ef2fSHans de Goede 	ret = i2c_smbus_write_byte_data(client, GC0310_RESET_RELATED, GC0310_REGISTER_PAGE_3);
4792b2297b1SHans de Goede 	if (ret)
480b6763b22SHans de Goede 		goto error_power_down;
481ad85094bSMauro Carvalho Chehab 
48265e5ef2fSHans de Goede 	ret = i2c_smbus_write_byte_data(client, GC0310_SW_STREAM,
48365e5ef2fSHans de Goede 					enable ? GC0310_START_STREAMING : GC0310_STOP_STREAMING);
4842b2297b1SHans de Goede 	if (ret)
485b6763b22SHans de Goede 		goto error_power_down;
486ad85094bSMauro Carvalho Chehab 
48765e5ef2fSHans de Goede 	ret = i2c_smbus_write_byte_data(client, GC0310_RESET_RELATED, GC0310_REGISTER_PAGE_0);
4882b2297b1SHans de Goede 	if (ret)
489b6763b22SHans de Goede 		goto error_power_down;
490b6763b22SHans de Goede 
491b6763b22SHans de Goede 	if (!enable)
4922726c899SHans de Goede 		pm_runtime_put(&client->dev);
493ad85094bSMauro Carvalho Chehab 
4942726c899SHans de Goede 	dev->is_streaming = enable;
495ad85094bSMauro Carvalho Chehab 	mutex_unlock(&dev->input_lock);
4962b2297b1SHans de Goede 	return 0;
4972b2297b1SHans de Goede 
498b6763b22SHans de Goede error_power_down:
4992726c899SHans de Goede 	pm_runtime_put(&client->dev);
5002726c899SHans de Goede 	dev->is_streaming = false;
5012b2297b1SHans de Goede error_unlock:
5022b2297b1SHans de Goede 	mutex_unlock(&dev->input_lock);
503ad85094bSMauro Carvalho Chehab 	return ret;
504ad85094bSMauro Carvalho Chehab }
505ad85094bSMauro Carvalho Chehab 
gc0310_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * interval)506ad85094bSMauro Carvalho Chehab static int gc0310_g_frame_interval(struct v4l2_subdev *sd,
507ad85094bSMauro Carvalho Chehab 				   struct v4l2_subdev_frame_interval *interval)
508ad85094bSMauro Carvalho Chehab {
509ad85094bSMauro Carvalho Chehab 	interval->interval.numerator = 1;
5109783b96aSHans de Goede 	interval->interval.denominator = GC0310_FPS;
511ad85094bSMauro Carvalho Chehab 
512ad85094bSMauro Carvalho Chehab 	return 0;
513ad85094bSMauro Carvalho Chehab }
514ad85094bSMauro Carvalho Chehab 
gc0310_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)515ad85094bSMauro Carvalho Chehab static int gc0310_enum_mbus_code(struct v4l2_subdev *sd,
5160d346d2aSTomi Valkeinen 				 struct v4l2_subdev_state *sd_state,
517ad85094bSMauro Carvalho Chehab 				 struct v4l2_subdev_mbus_code_enum *code)
518ad85094bSMauro Carvalho Chehab {
5199783b96aSHans de Goede 	/* We support only a single format */
5209783b96aSHans de Goede 	if (code->index)
521ad85094bSMauro Carvalho Chehab 		return -EINVAL;
522ad85094bSMauro Carvalho Chehab 
523ad85094bSMauro Carvalho Chehab 	code->code = MEDIA_BUS_FMT_SGRBG8_1X8;
524ad85094bSMauro Carvalho Chehab 	return 0;
525ad85094bSMauro Carvalho Chehab }
526ad85094bSMauro Carvalho Chehab 
gc0310_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)527ad85094bSMauro Carvalho Chehab static int gc0310_enum_frame_size(struct v4l2_subdev *sd,
5280d346d2aSTomi Valkeinen 				  struct v4l2_subdev_state *sd_state,
529ad85094bSMauro Carvalho Chehab 				  struct v4l2_subdev_frame_size_enum *fse)
530ad85094bSMauro Carvalho Chehab {
5319783b96aSHans de Goede 	/* We support only a single resolution */
5329783b96aSHans de Goede 	if (fse->index)
533ad85094bSMauro Carvalho Chehab 		return -EINVAL;
534ad85094bSMauro Carvalho Chehab 
5359783b96aSHans de Goede 	fse->min_width = GC0310_NATIVE_WIDTH;
5369783b96aSHans de Goede 	fse->max_width = GC0310_NATIVE_WIDTH;
5379783b96aSHans de Goede 	fse->min_height = GC0310_NATIVE_HEIGHT;
5389783b96aSHans de Goede 	fse->max_height = GC0310_NATIVE_HEIGHT;
539ad85094bSMauro Carvalho Chehab 
540ad85094bSMauro Carvalho Chehab 	return 0;
541ad85094bSMauro Carvalho Chehab }
542ad85094bSMauro Carvalho Chehab 
gc0310_g_skip_frames(struct v4l2_subdev * sd,u32 * frames)543ad85094bSMauro Carvalho Chehab static int gc0310_g_skip_frames(struct v4l2_subdev *sd, u32 *frames)
544ad85094bSMauro Carvalho Chehab {
5459783b96aSHans de Goede 	*frames = GC0310_SKIP_FRAMES;
546ad85094bSMauro Carvalho Chehab 	return 0;
547ad85094bSMauro Carvalho Chehab }
548ad85094bSMauro Carvalho Chehab 
549ad85094bSMauro Carvalho Chehab static const struct v4l2_subdev_sensor_ops gc0310_sensor_ops = {
550ad85094bSMauro Carvalho Chehab 	.g_skip_frames	= gc0310_g_skip_frames,
551ad85094bSMauro Carvalho Chehab };
552ad85094bSMauro Carvalho Chehab 
553ad85094bSMauro Carvalho Chehab static const struct v4l2_subdev_video_ops gc0310_video_ops = {
554ad85094bSMauro Carvalho Chehab 	.s_stream = gc0310_s_stream,
555ad85094bSMauro Carvalho Chehab 	.g_frame_interval = gc0310_g_frame_interval,
556ad85094bSMauro Carvalho Chehab };
557ad85094bSMauro Carvalho Chehab 
558ad85094bSMauro Carvalho Chehab static const struct v4l2_subdev_pad_ops gc0310_pad_ops = {
559ad85094bSMauro Carvalho Chehab 	.enum_mbus_code = gc0310_enum_mbus_code,
560ad85094bSMauro Carvalho Chehab 	.enum_frame_size = gc0310_enum_frame_size,
561ad85094bSMauro Carvalho Chehab 	.get_fmt = gc0310_get_fmt,
562ad85094bSMauro Carvalho Chehab 	.set_fmt = gc0310_set_fmt,
563ad85094bSMauro Carvalho Chehab };
564ad85094bSMauro Carvalho Chehab 
565ad85094bSMauro Carvalho Chehab static const struct v4l2_subdev_ops gc0310_ops = {
566ad85094bSMauro Carvalho Chehab 	.video = &gc0310_video_ops,
567ad85094bSMauro Carvalho Chehab 	.pad = &gc0310_pad_ops,
568ad85094bSMauro Carvalho Chehab 	.sensor = &gc0310_sensor_ops,
569ad85094bSMauro Carvalho Chehab };
570ad85094bSMauro Carvalho Chehab 
gc0310_init_controls(struct gc0310_device * dev)571ef5fb5d4SHans de Goede static int gc0310_init_controls(struct gc0310_device *dev)
572ef5fb5d4SHans de Goede {
573ef5fb5d4SHans de Goede 	struct v4l2_ctrl_handler *hdl = &dev->ctrls.handler;
574ef5fb5d4SHans de Goede 
575ef5fb5d4SHans de Goede 	v4l2_ctrl_handler_init(hdl, 2);
576ef5fb5d4SHans de Goede 
577ef5fb5d4SHans de Goede 	/* Use the same lock for controls as for everything else */
578ef5fb5d4SHans de Goede 	hdl->lock = &dev->input_lock;
579ef5fb5d4SHans de Goede 	dev->sd.ctrl_handler = hdl;
580ef5fb5d4SHans de Goede 
581ef5fb5d4SHans de Goede 	dev->ctrls.exposure =
582ef5fb5d4SHans de Goede 		v4l2_ctrl_new_std(hdl, &ctrl_ops, V4L2_CID_EXPOSURE, 0, 4095, 1, 1023);
583ef5fb5d4SHans de Goede 
584ef5fb5d4SHans de Goede 	/* 32 steps at base gain 1 + 64 half steps at base gain 2 */
585ef5fb5d4SHans de Goede 	dev->ctrls.gain =
586ef5fb5d4SHans de Goede 		v4l2_ctrl_new_std(hdl, &ctrl_ops, V4L2_CID_GAIN, 0, 95, 1, 31);
587ef5fb5d4SHans de Goede 
588ef5fb5d4SHans de Goede 	return hdl->error;
589ef5fb5d4SHans de Goede }
590ef5fb5d4SHans de Goede 
gc0310_remove(struct i2c_client * client)591ed5c2f5fSUwe Kleine-König static void gc0310_remove(struct i2c_client *client)
592ad85094bSMauro Carvalho Chehab {
593ad85094bSMauro Carvalho Chehab 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
594ad85094bSMauro Carvalho Chehab 	struct gc0310_device *dev = to_gc0310_sensor(sd);
595bdfe0bebSMauro Carvalho Chehab 
596ad85094bSMauro Carvalho Chehab 	dev_dbg(&client->dev, "gc0310_remove...\n");
597ad85094bSMauro Carvalho Chehab 
598*1aace3daSHans de Goede 	v4l2_async_unregister_subdev(sd);
599ad85094bSMauro Carvalho Chehab 	media_entity_cleanup(&dev->sd.entity);
600ef5fb5d4SHans de Goede 	v4l2_ctrl_handler_free(&dev->ctrls.handler);
6012746a966SHans de Goede 	mutex_destroy(&dev->input_lock);
602*1aace3daSHans de Goede 	fwnode_handle_put(dev->ep_fwnode);
6032726c899SHans de Goede 	pm_runtime_disable(&client->dev);
604ad85094bSMauro Carvalho Chehab }
605ad85094bSMauro Carvalho Chehab 
gc0310_probe(struct i2c_client * client)606ad85094bSMauro Carvalho Chehab static int gc0310_probe(struct i2c_client *client)
607ad85094bSMauro Carvalho Chehab {
608ad85094bSMauro Carvalho Chehab 	struct gc0310_device *dev;
609ad85094bSMauro Carvalho Chehab 	int ret;
610c03496b3SMauro Carvalho Chehab 
611340b4dd6SHans de Goede 	dev = devm_kzalloc(&client->dev, sizeof(*dev), GFP_KERNEL);
612ad85094bSMauro Carvalho Chehab 	if (!dev)
613ad85094bSMauro Carvalho Chehab 		return -ENOMEM;
614ad85094bSMauro Carvalho Chehab 
615*1aace3daSHans de Goede 	/*
616*1aace3daSHans de Goede 	 * Sometimes the fwnode graph is initialized by the bridge driver.
617*1aace3daSHans de Goede 	 * Bridge drivers doing this may also add GPIO mappings, wait for this.
618*1aace3daSHans de Goede 	 */
619*1aace3daSHans de Goede 	dev->ep_fwnode = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL);
620*1aace3daSHans de Goede 	if (!dev->ep_fwnode)
621*1aace3daSHans de Goede 		return dev_err_probe(&client->dev, -EPROBE_DEFER, "waiting for fwnode graph endpoint\n");
6222ec5bfe0SHans de Goede 
6232ec5bfe0SHans de Goede 	dev->reset = devm_gpiod_get(&client->dev, "reset", GPIOD_OUT_HIGH);
624*1aace3daSHans de Goede 	if (IS_ERR(dev->reset)) {
625*1aace3daSHans de Goede 		fwnode_handle_put(dev->ep_fwnode);
6262ec5bfe0SHans de Goede 		return dev_err_probe(&client->dev, PTR_ERR(dev->reset),
6272ec5bfe0SHans de Goede 				     "getting reset GPIO\n");
628*1aace3daSHans de Goede 	}
6292ec5bfe0SHans de Goede 
6302ec5bfe0SHans de Goede 	dev->powerdown = devm_gpiod_get(&client->dev, "powerdown", GPIOD_OUT_HIGH);
631*1aace3daSHans de Goede 	if (IS_ERR(dev->powerdown)) {
632*1aace3daSHans de Goede 		fwnode_handle_put(dev->ep_fwnode);
6332ec5bfe0SHans de Goede 		return dev_err_probe(&client->dev, PTR_ERR(dev->powerdown),
6342ec5bfe0SHans de Goede 				     "getting powerdown GPIO\n");
635*1aace3daSHans de Goede 	}
6362ec5bfe0SHans de Goede 
637ad85094bSMauro Carvalho Chehab 	mutex_init(&dev->input_lock);
638bdfe0bebSMauro Carvalho Chehab 	v4l2_i2c_subdev_init(&dev->sd, client, &gc0310_ops);
6399783b96aSHans de Goede 	gc0310_fill_format(&dev->mode.fmt);
640ad85094bSMauro Carvalho Chehab 
6412726c899SHans de Goede 	pm_runtime_set_suspended(&client->dev);
6422726c899SHans de Goede 	pm_runtime_enable(&client->dev);
6432726c899SHans de Goede 	pm_runtime_set_autosuspend_delay(&client->dev, 1000);
6442726c899SHans de Goede 	pm_runtime_use_autosuspend(&client->dev);
6452726c899SHans de Goede 
646f5e381ffSHans de Goede 	ret = gc0310_detect(client);
6472726c899SHans de Goede 	if (ret) {
6482726c899SHans de Goede 		gc0310_remove(client);
6492726c899SHans de Goede 		return ret;
6502726c899SHans de Goede 	}
651ad85094bSMauro Carvalho Chehab 
652ad85094bSMauro Carvalho Chehab 	dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
653ad85094bSMauro Carvalho Chehab 	dev->pad.flags = MEDIA_PAD_FL_SOURCE;
654ad85094bSMauro Carvalho Chehab 	dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
655*1aace3daSHans de Goede 	dev->sd.fwnode = dev->ep_fwnode;
656ef5fb5d4SHans de Goede 
657ef5fb5d4SHans de Goede 	ret = gc0310_init_controls(dev);
658ad85094bSMauro Carvalho Chehab 	if (ret) {
659ad85094bSMauro Carvalho Chehab 		gc0310_remove(client);
660ad85094bSMauro Carvalho Chehab 		return ret;
661ad85094bSMauro Carvalho Chehab 	}
662ad85094bSMauro Carvalho Chehab 
663ad85094bSMauro Carvalho Chehab 	ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad);
6642ec5bfe0SHans de Goede 	if (ret) {
665ad85094bSMauro Carvalho Chehab 		gc0310_remove(client);
666ad85094bSMauro Carvalho Chehab 		return ret;
667ad85094bSMauro Carvalho Chehab 	}
668ad85094bSMauro Carvalho Chehab 
669*1aace3daSHans de Goede 	ret = v4l2_async_register_subdev_sensor(&dev->sd);
6702ec5bfe0SHans de Goede 	if (ret) {
6712ec5bfe0SHans de Goede 		gc0310_remove(client);
6722ec5bfe0SHans de Goede 		return ret;
6732ec5bfe0SHans de Goede 	}
6742ec5bfe0SHans de Goede 
6752ec5bfe0SHans de Goede 	return 0;
6762ec5bfe0SHans de Goede }
6772ec5bfe0SHans de Goede 
gc0310_suspend(struct device * dev)6782726c899SHans de Goede static int gc0310_suspend(struct device *dev)
6792726c899SHans de Goede {
6802726c899SHans de Goede 	struct v4l2_subdev *sd = dev_get_drvdata(dev);
6812ec5bfe0SHans de Goede 	struct gc0310_device *gc0310_dev = to_gc0310_sensor(sd);
6822726c899SHans de Goede 
6832ec5bfe0SHans de Goede 	gpiod_set_value_cansleep(gc0310_dev->powerdown, 1);
6842ec5bfe0SHans de Goede 	gpiod_set_value_cansleep(gc0310_dev->reset, 1);
6852ec5bfe0SHans de Goede 	return 0;
6862726c899SHans de Goede }
6872726c899SHans de Goede 
gc0310_resume(struct device * dev)6882726c899SHans de Goede static int gc0310_resume(struct device *dev)
6892726c899SHans de Goede {
6902726c899SHans de Goede 	struct v4l2_subdev *sd = dev_get_drvdata(dev);
6912ec5bfe0SHans de Goede 	struct gc0310_device *gc0310_dev = to_gc0310_sensor(sd);
6922726c899SHans de Goede 
6932ec5bfe0SHans de Goede 	usleep_range(10000, 15000);
6942ec5bfe0SHans de Goede 	gpiod_set_value_cansleep(gc0310_dev->reset, 0);
6952ec5bfe0SHans de Goede 	usleep_range(10000, 15000);
6962ec5bfe0SHans de Goede 	gpiod_set_value_cansleep(gc0310_dev->powerdown, 0);
6972ec5bfe0SHans de Goede 
6982ec5bfe0SHans de Goede 	return 0;
6992726c899SHans de Goede }
7002726c899SHans de Goede 
7012726c899SHans de Goede static DEFINE_RUNTIME_DEV_PM_OPS(gc0310_pm_ops, gc0310_suspend, gc0310_resume, NULL);
7022726c899SHans de Goede 
703ad85094bSMauro Carvalho Chehab static const struct acpi_device_id gc0310_acpi_match[] = {
704ad85094bSMauro Carvalho Chehab 	{"INT0310"},
705ad85094bSMauro Carvalho Chehab 	{},
706ad85094bSMauro Carvalho Chehab };
707ad85094bSMauro Carvalho Chehab MODULE_DEVICE_TABLE(acpi, gc0310_acpi_match);
708ad85094bSMauro Carvalho Chehab 
709ad85094bSMauro Carvalho Chehab static struct i2c_driver gc0310_driver = {
710ad85094bSMauro Carvalho Chehab 	.driver = {
711ad85094bSMauro Carvalho Chehab 		.name = "gc0310",
7122726c899SHans de Goede 		.pm = pm_sleep_ptr(&gc0310_pm_ops),
713ad85094bSMauro Carvalho Chehab 		.acpi_match_table = gc0310_acpi_match,
714ad85094bSMauro Carvalho Chehab 	},
715625ac9afSUwe Kleine-König 	.probe = gc0310_probe,
716ad85094bSMauro Carvalho Chehab 	.remove = gc0310_remove,
717ad85094bSMauro Carvalho Chehab };
718ad85094bSMauro Carvalho Chehab module_i2c_driver(gc0310_driver);
719ad85094bSMauro Carvalho Chehab 
720ad85094bSMauro Carvalho Chehab MODULE_AUTHOR("Lai, Angie <angie.lai@intel.com>");
721ad85094bSMauro Carvalho Chehab MODULE_DESCRIPTION("A low-level driver for GalaxyCore GC0310 sensors");
722ad85094bSMauro Carvalho Chehab MODULE_LICENSE("GPL");
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