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/openbmc/linux/drivers/net/hamradio/
H A Dz8530.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 #define AUTO_ENAB 0x20 /* Auto Enables */
91 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
145 /* Write Register 12 (lower byte of baud rate generator time constant) */
147 /* Write Register 13 (upper byte of baud rate generator time constant) */
150 #define BRENABL 1 /* Baud rate generator enable */
151 #define BRSRC 2 /* Baud rate generator source */
153 #define AUTOECHO 8 /* Auto Echo */
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/openbmc/linux/drivers/tty/serial/
H A Dsuncore.c1 // SPDX-License-Identifier: GPL-2.0
32 drv->minor = sunserial_current_minor; in sunserial_register_minors()
33 drv->nr += count; in sunserial_register_minors()
35 if (drv->nr == count) in sunserial_register_minors()
39 drv->tty_driver->name_base = drv->minor - 64; in sunserial_register_minors()
47 drv->nr -= count; in sunserial_unregister_minors()
48 sunserial_current_minor -= count; in sunserial_unregister_minors()
50 if (drv->nr == 0) in sunserial_unregister_minors()
61 drv->cons = con; in sunserial_console_match()
78 con->index = line; in sunserial_console_match()
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H A Dmxs-auart.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
11 * Copyright 2008-2010 Freescale Semiconductor, Inc.
34 #include <linux/dma-mapping.h>
90 #define AUART_LINECTRL_WLEN(v) ((((v) - 5) & 0x3) << 5)
138 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
140 * input is idle, then the watchdog counter will decrement each bit-time. Note
141 * 7-bit-time is added to the programmed value, so a value of zero will set
142 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
146 * value is 0x3 (31 bit-time).
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H A Dmilbeaut_usio.c1 // SPDX-License-Identifier: GPL-2.0
15 #define USIO_NAME "mlb-usio-uart"
67 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_stop_tx()
68 port->membase + MLB_USIO_REG_FCR); in mlb_usio_stop_tx()
69 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE, in mlb_usio_stop_tx()
70 port->membase + MLB_USIO_REG_SCR); in mlb_usio_stop_tx()
75 struct circ_buf *xmit = &port->state->xmit; in mlb_usio_tx_chars()
78 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_tx_chars()
79 port->membase + MLB_USIO_REG_FCR); in mlb_usio_tx_chars()
80 writeb(readb(port->membase + MLB_USIO_REG_SCR) & in mlb_usio_tx_chars()
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H A Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
94 #define AUTO_ENAB 0x20 /* Auto Enables */
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
181 /* Write Register 12 (lower byte of baud rate generator time constant) */
183 /* Write Register 13 (upper byte of baud rate generator time constant) */
186 #define BRENAB 1 /* Baud rate generator enable */
187 #define BRSRC 2 /* Baud rate generator source */
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H A Dmax310x.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
50 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
64 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
65 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
66 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
104 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
117 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
118 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
121 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
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H A Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
113 #define AUTO_ENAB 0x20 /* Auto Enables */
144 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
200 /* Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) */
202 /* Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) */
205 #define BRENABL 1 /* Baud rate generator enable */
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H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
86 #define AUTO_ENAB 0x20 /* Auto Enables */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
183 /* Write Register 12 (lower byte of baud rate generator time constant) */
185 /* Write Register 13 (upper byte of baud rate generator time constant) */
188 #define BRENAB 1 /* Baud rate generator enable */
189 #define BRSRC 2 /* Baud rate generator source */
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H A Dma35d1_serial.c1 // SPDX-License-Identifier: GPL-2.0+
36 /* MA35_IER_REG - Interrupt Enable Register */
40 #define MA35_IER_RTO_IEN BIT(4) /* RX Time-out Interrupt Enable */
42 #define MA35_IER_TIME_OUT_EN BIT(11) /* RX Buffer Time-out Counter Enable */
43 #define MA35_IER_AUTO_RTS BIT(12) /* nRTS Auto-flow Control Enable */
44 #define MA35_IER_AUTO_CTS BIT(13) /* nCTS Auto-flow Control Enable */
46 /* MA35_FCR_REG - FIFO Control Register */
62 /* MA35_LCR_REG - Line Control Register */
74 /* MA35_MCR_REG - Modem Control Register */
79 /* MA35_MSR_REG - Modem Status Register */
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H A Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
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H A Dliteuart.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019-2020 Antmicro <www.antmicro.com>
25 * The definitions below are true for LiteX SoC configured for 8-bit CSR Bus,
26 * 32-bit aligned.
76 uart->irq_reg |= mask; in liteuart_update_irq_reg()
78 uart->irq_reg &= ~mask; in liteuart_update_irq_reg()
80 if (port->irq) in liteuart_update_irq_reg()
81 litex_write8(port->membase + OFF_EV_ENABLE, uart->irq_reg); in liteuart_update_irq_reg()
99 del_timer(&uart->timer); in liteuart_stop_rx()
104 unsigned char __iomem *membase = port->membase; in liteuart_rx_chars()
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H A Dfsl_lpuart.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
13 #include <linux/dma-mapping.h>
29 /* All registers are 8-bit width */
118 /* 32-bit global registers only for i.MX7ULP/i.MX8x
123 /* 32-bit register definition */
244 #define DRIVER_NAME "fsl-lpuart"
337 .rx_watermark = 7, /* A lower watermark is ideal for low baud rates. */
347 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
348 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
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/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dserial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
19 where N is the port number (non-negative decimal integer) as printed on the
28 cts-gpios:
34 dcd-gpios:
40 dsr-gpios:
46 dtr-gpios:
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/openbmc/u-boot/include/
H A Dfsl_qe.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
21 #define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE)
74 /* QE CECR Sub Block Code - sub block code of QE command.
108 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
134 QE_BRG1, /* Baud Rate Generator 1 */
135 QE_BRG2, /* Baud Rate Generator 2 */
136 QE_BRG3, /* Baud Rate Generator 3 */
137 QE_BRG4, /* Baud Rate Generator 4 */
138 QE_BRG5, /* Baud Rate Generator 5 */
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H A Dns16550.h15 * added support for port on 64-bit bus
31 #define CONFIG_SYS_NS16550_REG_SIZE (-1)
40 unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
45 unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
49 * struct ns16550_platdata - information about a NS16550 port
123 /* Ingenic JZ47xx specific UART-enable bit. */
139 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
213 * ns16550_calc_divisor() - calculate the divisor given clock and baud rate
220 * @baudrate: Required baud rate
221 * @return baud rate divisor that should be used
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/openbmc/qemu/hw/char/
H A Dstm32l4x5_usart.c4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
15 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
22 #include "chardev/char-fe.h"
23 #include "chardev/char-serial.h"
28 #include "hw/qdev-clock.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-properties-system.h"
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/openbmc/linux/drivers/tty/serial/8250/
H A D8250_fintek.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2016 Ricardo Ribalda, Qtechnology A/S
105 outb(reg, pdata->base_port + ADDR_PORT); in sio_read_reg()
106 return inb(pdata->base_port + DATA_PORT); in sio_read_reg()
111 outb(reg, pdata->base_port + ADDR_PORT); in sio_write_reg()
112 outb(data, pdata->base_port + DATA_PORT); in sio_write_reg()
127 return -EBUSY; in fintek_8250_enter_key()
149 return -ENODEV; in fintek_8250_check_id()
152 return -ENODEV; in fintek_8250_check_id()
167 return -ENODEV; in fintek_8250_check_id()
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H A D8250_port.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
255 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
256 * workaround of errata A-008006 which states that tx_loadsz should
268 .name = "Palmchip BK-3103",
354 offset = offset << p->regshift; in hub6_serial_in()
355 outb(p->hub6 - 1 + offset, p->iobase); in hub6_serial_in()
356 return inb(p->iobase + 1); in hub6_serial_in()
361 offset = offset << p->regshift; in hub6_serial_out()
362 outb(p->hub6 - 1 + offset, p->iobase); in hub6_serial_out()
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H A D8250_exar.c1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
105 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
111 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
112 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
133 * ---- ---- --------
137 * 3 - <reserved>
141 * 7 - <reserved>
144 * 10 - Red LED
145 * 11..15 - <unused>
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/openbmc/linux/drivers/tty/serial/jsm/
H A Djsm_neo.c1 // SPDX-License-Identifier: GPL-2.0+
25 * a non-destructive, read-only location on the Neo card.
27 * In this case, we are reading the DVID (Read-only Device Identification)
32 readb(bd->re_map_membase + 0x8D); in neo_pci_posting_flush()
38 ier = readb(&ch->ch_neo_uart->ier); in neo_set_cts_flow_control()
39 efr = readb(&ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); in neo_set_cts_flow_control()
43 /* Turn on auto CTS flow control */ in neo_set_cts_flow_control()
47 /* Turn off auto Xon flow control */ in neo_set_cts_flow_control()
51 writeb(0, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
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/openbmc/linux/include/soc/fsl/qe/
H A Dqe.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
33 QE_BRG1, /* Baud Rate Generator 1 */
34 QE_BRG2, /* Baud Rate Generator 2 */
35 QE_BRG3, /* Baud Rate Generator 3 */
36 QE_BRG4, /* Baud Rate Generator 4 */
37 QE_BRG5, /* Baud Rate Generator 5 */
38 QE_BRG6, /* Baud Rate Generator 6 */
39 QE_BRG7, /* Baud Rate Generator 7 */
40 QE_BRG8, /* Baud Rate Generator 8 */
41 QE_BRG9, /* Baud Rate Generator 9 */
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/openbmc/linux/drivers/media/dvb-frontends/
H A Dbcm3510_priv.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (C) 2001-5, B2C2 inc.
267 /* auto reacquire */
301 u8 PE :1; /* baud clock pin */
303 u8 BE :1; /* baud clock pin */
364 u8 ARI :1; /* auto reacquire */
/openbmc/linux/arch/m68k/include/asm/
H A Dmcfuart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfuart.h -- ColdFire internal UART support defines.
7 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
39 #define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
40 #define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
59 #define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
83 #define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
/openbmc/u-boot/drivers/spi/
H A Dzynq_spi.c1 // SPDX-License-Identifier: GPL-2.0+
21 #define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
30 #define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
31 #define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
74 struct zynq_spi_platdata *plat = bus->platdata; in zynq_spi_ofdata_to_platdata()
75 const void *blob = gd->fdt_blob; in zynq_spi_ofdata_to_platdata()
78 plat->regs = (struct zynq_spi_regs *)devfdt_get_addr(bus); in zynq_spi_ofdata_to_platdata()
81 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", in zynq_spi_ofdata_to_platdata()
83 plat->deactivate_delay_us = fdtdec_get_int(blob, node, in zynq_spi_ofdata_to_platdata()
84 "spi-deactivate-delay", 0); in zynq_spi_ofdata_to_platdata()
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/openbmc/u-boot/board/synopsys/emsdp/
H A DREADME2 Useful notes on bulding and using of U-Boot on
8 The DesignWare ARC EM Software Development Platform is FPGA-bases platform
12 versions of ARC EM CPUs. U-Boot is built to be run on the simplest
16 The board has the following features useful for U-Boot:
17 * On-board 2-channel FTDI TTL-to-USB converter
18 - The first channel is used for serial debug port (which makes it possible
22 There's no HW flow-control and baud-rate is 115200.
24 - The second channel is used for built-in Digilent USB JTAG probe.
29 - Also with help of this FTDI chip it is possible to reset entire
30 board with help of a special `rff-ftdi-reset` utility, see:
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