Lines Matching +full:auto +full:- +full:baud
1 // SPDX-License-Identifier: GPL-2.0+
21 #define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
30 #define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
31 #define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
74 struct zynq_spi_platdata *plat = bus->platdata; in zynq_spi_ofdata_to_platdata()
75 const void *blob = gd->fdt_blob; in zynq_spi_ofdata_to_platdata()
78 plat->regs = (struct zynq_spi_regs *)devfdt_get_addr(bus); in zynq_spi_ofdata_to_platdata()
81 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", in zynq_spi_ofdata_to_platdata()
83 plat->deactivate_delay_us = fdtdec_get_int(blob, node, in zynq_spi_ofdata_to_platdata()
84 "spi-deactivate-delay", 0); in zynq_spi_ofdata_to_platdata()
85 plat->activate_delay_us = fdtdec_get_int(blob, node, in zynq_spi_ofdata_to_platdata()
86 "spi-activate-delay", 0); in zynq_spi_ofdata_to_platdata()
87 plat->speed_hz = plat->frequency / 2; in zynq_spi_ofdata_to_platdata()
89 debug("%s: regs=%p max-frequency=%d\n", __func__, in zynq_spi_ofdata_to_platdata()
90 plat->regs, plat->frequency); in zynq_spi_ofdata_to_platdata()
97 struct zynq_spi_regs *regs = priv->regs; in zynq_spi_init_hw()
102 writel(~confr, ®s->enr); in zynq_spi_init_hw()
105 writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->idr); in zynq_spi_init_hw()
108 while (readl(®s->isr) & in zynq_spi_init_hw()
110 readl(®s->rxdr); in zynq_spi_init_hw()
113 writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->isr); in zynq_spi_init_hw()
115 /* Manual slave select and Auto start */ in zynq_spi_init_hw()
119 writel(confr, ®s->cr); in zynq_spi_init_hw()
122 writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr); in zynq_spi_init_hw()
130 priv->regs = plat->regs; in zynq_spi_probe()
131 priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH; in zynq_spi_probe()
141 struct udevice *bus = dev->parent; in spi_cs_activate()
142 struct zynq_spi_platdata *plat = bus->platdata; in spi_cs_activate()
144 struct zynq_spi_regs *regs = priv->regs; in spi_cs_activate()
148 if (plat->deactivate_delay_us && priv->last_transaction_us) { in spi_cs_activate()
150 delay_us = timer_get_us() - priv->last_transaction_us; in spi_cs_activate()
151 if (delay_us < plat->deactivate_delay_us) in spi_cs_activate()
152 udelay(plat->deactivate_delay_us - delay_us); in spi_cs_activate()
155 clrbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK); in spi_cs_activate()
156 cr = readl(®s->cr); in spi_cs_activate()
159 * xxx0 - cs0 in spi_cs_activate()
160 * xx01 - cs1 in spi_cs_activate()
161 * x011 - cs2 in spi_cs_activate()
163 cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; in spi_cs_activate()
164 writel(cr, ®s->cr); in spi_cs_activate()
166 if (plat->activate_delay_us) in spi_cs_activate()
167 udelay(plat->activate_delay_us); in spi_cs_activate()
172 struct udevice *bus = dev->parent; in spi_cs_deactivate()
173 struct zynq_spi_platdata *plat = bus->platdata; in spi_cs_deactivate()
175 struct zynq_spi_regs *regs = priv->regs; in spi_cs_deactivate()
177 setbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK); in spi_cs_deactivate()
180 if (plat->deactivate_delay_us) in spi_cs_deactivate()
181 priv->last_transaction_us = timer_get_us(); in spi_cs_deactivate()
186 struct udevice *bus = dev->parent; in zynq_spi_claim_bus()
188 struct zynq_spi_regs *regs = priv->regs; in zynq_spi_claim_bus()
190 writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr); in zynq_spi_claim_bus()
197 struct udevice *bus = dev->parent; in zynq_spi_release_bus()
199 struct zynq_spi_regs *regs = priv->regs; in zynq_spi_release_bus()
203 writel(~confr, ®s->enr); in zynq_spi_release_bus()
211 struct udevice *bus = dev->parent; in zynq_spi_xfer()
213 struct zynq_spi_regs *regs = priv->regs; in zynq_spi_xfer()
222 bus->seq, slave_plat->cs, bitlen, len, flags); in zynq_spi_xfer()
226 return -1; in zynq_spi_xfer()
229 priv->cs = slave_plat->cs; in zynq_spi_xfer()
234 /* Write the data into TX FIFO - tx threshold is fifo_depth */ in zynq_spi_xfer()
236 while ((tx_tvl < priv->fifo_depth) && tx_len) { in zynq_spi_xfer()
241 writel(buf, ®s->txdr); in zynq_spi_xfer()
242 tx_len--; in zynq_spi_xfer()
248 status = readl(®s->isr); in zynq_spi_xfer()
252 return -1; in zynq_spi_xfer()
254 status = readl(®s->isr); in zynq_spi_xfer()
258 status = readl(®s->isr); in zynq_spi_xfer()
260 buf = readl(®s->rxdr); in zynq_spi_xfer()
263 status = readl(®s->isr); in zynq_spi_xfer()
264 rx_len--; in zynq_spi_xfer()
276 struct zynq_spi_platdata *plat = bus->platdata; in zynq_spi_set_speed()
278 struct zynq_spi_regs *regs = priv->regs; in zynq_spi_set_speed()
282 if (speed > plat->frequency) in zynq_spi_set_speed()
283 speed = plat->frequency; in zynq_spi_set_speed()
286 confr = readl(®s->cr); in zynq_spi_set_speed()
290 } else if (plat->speed_hz != speed) { in zynq_spi_set_speed()
292 ((plat->frequency / in zynq_spi_set_speed()
295 plat->speed_hz = speed / (2 << baud_rate_val); in zynq_spi_set_speed()
300 writel(confr, ®s->cr); in zynq_spi_set_speed()
301 priv->freq = speed; in zynq_spi_set_speed()
304 priv->regs, priv->freq); in zynq_spi_set_speed()
312 struct zynq_spi_regs *regs = priv->regs; in zynq_spi_set_mode()
316 confr = readl(®s->cr); in zynq_spi_set_mode()
324 writel(confr, ®s->cr); in zynq_spi_set_mode()
325 priv->mode = mode; in zynq_spi_set_mode()
327 debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode); in zynq_spi_set_mode()
341 { .compatible = "xlnx,zynq-spi-r1p6" },
342 { .compatible = "cdns,spi-r1p6" },