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/openbmc/u-boot/arch/arm/dts/
H A Dast2500.dtsi3 * https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi
9 compatible = "aspeed,ast2500";
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&vic>;
38 #address-cells = <1>;
39 #size-cells = <0>;
42 compatible = "arm,arm1176jzf-s";
54 compatible = "simple-bus";
55 #address-cells = <1>;
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H A Dast2500-u-boot.dtsi1 #include <dt-bindings/clock/ast2500-clock.h>
2 #include <dt-bindings/reset/ast2500-reset.h>
4 #include "ast2500.dtsi"
7 scu: clock-controller@1e6e2000 { label
8 compatible = "aspeed,ast2500-scu";
10 u-boot,dm-pre-reloc;
11 #clock-cells = <1>;
12 #reset-cells = <1>;
15 rst: reset-controller {
16 u-boot,dm-pre-reloc;
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Daspeed,ast2500-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/aspeed,ast2500-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ASPEED AST2500 Pin Controller
10 - Andrew Jeffery <andrew@aj.id.au>
16 - compatible: Should be one of the following:
17 "aspeed,ast2500-scu", "syscon", "simple-mfd"
18 "aspeed,g5-scu", "syscon", "simple-mfd"
25 const: aspeed,ast2500-pinctrl
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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Daspeed,ast2x00-scu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mfd/aspeed,ast2x00-scu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Joel Stanley <joel@jms.id.au>
15 - Andrew Jeffery <andrew@aj.id.au>
20 - enum:
21 - aspeed,ast2400-scu
22 - aspeed,ast2500-scu
23 - aspeed,ast2600-scu
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Daspeed,ast2xxx-scu-ic.txt1 Aspeed AST25XX and AST26XX SCU Interrupt Controller
4 - #interrupt-cells : must be 1
5 - compatible : must be "aspeed,ast2500-scu-ic",
6 "aspeed,ast2600-scu-ic0" or
7 "aspeed,ast2600-scu-ic1"
8 - interrupts : interrupt from the parent controller
9 - interrupt-controller : indicates that the controller receives and
17 scu_ic: interrupt-controller@18 {
18 #interrupt-cells = <1>;
19 compatible = "aspeed,ast2500-scu-ic";
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/openbmc/linux/Documentation/devicetree/bindings/misc/
H A Daspeed-p2a-ctrl.txt2 Device tree bindings for Aspeed AST2400/AST2500 PCI-to-AHB Bridge Control Driver
14 - compatible: must be one of:
15 - "aspeed,ast2400-p2a-ctrl"
16 - "aspeed,ast2500-p2a-ctrl"
21 - reg: A hint for the memory regions associated with the P2A controller
22 - memory-region: A phandle to a reserved_memory region to be used for the PCI
25 The p2a-control node should be the child of a syscon node with the required
28 - compatible : Should be one of the following:
29 "aspeed,ast2400-scu", "syscon", "simple-mfd"
30 "aspeed,ast2500-scu", "syscon", "simple-mfd"
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/openbmc/linux/drivers/gpu/drm/aspeed/
H A Daspeed_gfx_drv.c1 // SPDX-License-Identifier: GPL-2.0+
5 #include <linux/dma-mapping.h>
37 * The AST2500 supports a total of 3 output paths:
56 * The driver was written with the 'AST2500 Software Programming Guide' v17,
61 u32 dac_reg; /* DAC register in SCU */
63 u32 vga_scratch_reg; /* VGA scratch register in SCU */
93 { .compatible = "aspeed,ast2400-gfx", .data = &ast2400_config },
94 { .compatible = "aspeed,ast2500-gfx", .data = &ast2500_config },
95 { .compatible = "aspeed,ast2600-gfx", .data = &ast2600_config },
114 drm->mode_config.min_width = 0; in aspeed_gfx_setup_mode_config()
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/openbmc/linux/Documentation/devicetree/bindings/soc/aspeed/
H A Dxdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eddie James <eajames@linux.ibm.com>
13 This binding describes the XDMA Engine embedded in the AST2500 and AST2600
20 - aspeed,ast2500-xdma
21 - aspeed,ast2600-xdma
33 reset-names:
35 - const: device
36 - const: root-complex
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/openbmc/u-boot/drivers/clk/aspeed/
H A Dclk_ast2500.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <clk-uclass.h>
15 #include <dt-bindings/clock/ast2500-clock.h>
16 #include <dt-bindings/reset/ast2500-reset.h>
36 * For H-PLL and M-PLL the formula is
38 * M - Numerator
39 * N - Denumerator
40 * P - Post Divider
43 * D-PLL and D2-PLL have extra divider (OD + 1), which is not
52 extern u32 ast2500_get_clkin(struct ast2500_scu *scu) in ast2500_get_clkin() argument
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/openbmc/u-boot/drivers/reset/aspeed/
H A Dreset-ast2500.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <reset-uclass.h>
18 struct ast2500_scu *scu; member
23 struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev); in ast2500_reset_deassert()
24 struct ast2500_scu *scu = priv->scu; in ast2500_reset_deassert() local
27 debug("ast2500_reset_deassert reset_ctl->id %ld \n", reset_ctl->id); in ast2500_reset_deassert()
29 if(reset_ctl->id >= 32) in ast2500_reset_deassert()
30 clrbits_le32(&scu->sysreset_ctrl2 , BIT(reset_ctl->id - 32)); in ast2500_reset_deassert()
32 clrbits_le32(&scu->sysreset_ctrl1 , BIT(reset_ctl->id)); in ast2500_reset_deassert()
39 struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev); in ast2500_reset_assert()
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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Daspeed,ast2600-fmc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
11 - Cédric Le Goater <clg@kaod.org>
15 SPI) of the AST2400, AST2500 and AST2600 SOCs.
18 - $ref: spi-controller.yaml#
23 - aspeed,ast2600-fmc
24 - aspeed,ast2600-spi
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/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-g5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
3 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
7 compatible = "aspeed,ast2500";
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&vic>;
36 #address-cells = <1>;
37 #size-cells = <0>;
40 compatible = "arm,arm1176jzf-s";
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H A Daspeed-g6.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
6 #include <dt-bindings/clock/ast2600-clock.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
47 #address-cells = <1>;
48 #size-cells = <0>;
49 enable-method = "aspeed,ast2600-smp";
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/openbmc/linux/drivers/soc/aspeed/
H A Daspeed-lpc-ctrl.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/aspeed-lpc-ctrl.h>
19 #define DEVICE_NAME "aspeed-lpc-ctrl"
40 struct regmap *scu; member
45 return container_of(file->private_data, struct aspeed_lpc_ctrl, in file_aspeed_lpc_ctrl()
52 unsigned long vsize = vma->vm_end - vma->vm_start; in aspeed_lpc_ctrl_mmap()
53 pgprot_t prot = vma->vm_page_prot; in aspeed_lpc_ctrl_mmap()
55 if (vma->vm_pgoff + vma_pages(vma) > lpc_ctrl->mem_size >> PAGE_SHIFT) in aspeed_lpc_ctrl_mmap()
56 return -EINVAL; in aspeed_lpc_ctrl_mmap()
61 if (remap_pfn_range(vma, vma->vm_start, in aspeed_lpc_ctrl_mmap()
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/openbmc/linux/drivers/fsi/
H A Dfsi-master-ast-cf.c1 // SPDX-License-Identifier: GPL-2.0+
4 * A FSI master controller, using a simple GPIO bit-banging interface
25 #include "fsi-master.h"
26 #include "cf-fsi-fw.h"
28 #define FW_FILE_NAME "cf-fsi-fw.bin"
30 /* Common SCU based coprocessor control registers */
35 /* AST2500 specific ones */
90 struct regmap *scu; member
132 msg->msg <<= bits; in msg_push_bits()
133 msg->msg |= data & ((1ull << bits) - 1); in msg_push_bits()
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/openbmc/linux/drivers/irqchip/
H A Dirq-aspeed-scu-ic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Aspeed AST24XX, AST25XX, and AST26XX SCU Interrupt Controller
42 struct regmap *scu; member
55 unsigned int mask = scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT; in aspeed_scu_ic_irq_handler()
60 * The SCU IC has just one register to control its operation and read in aspeed_scu_ic_irq_handler()
69 regmap_read(scu_ic->scu, scu_ic->reg, &sts); in aspeed_scu_ic_irq_handler()
70 enabled = sts & scu_ic->irq_enable; in aspeed_scu_ic_irq_handler()
73 bit = scu_ic->irq_shift; in aspeed_scu_ic_irq_handler()
74 max = scu_ic->num_irqs + bit; in aspeed_scu_ic_irq_handler()
77 generic_handle_domain_irq(scu_ic->irq_domain, in aspeed_scu_ic_irq_handler()
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/openbmc/linux/Documentation/devicetree/bindings/serial/
H A D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
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/openbmc/qemu/hw/arm/
H A Daspeed_ast2400.c10 * the COPYING file in the top-level directory.
18 #include "hw/char/serial-mm.h"
20 #include "qemu/error-report.h"
24 #include "target/arm/cpu-qom.h"
148 return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]); in aspeed_soc_ast2400_get_irq()
160 if (sscanf(sc->name, "%7s", socname) != 1) { in aspeed_ast2400_soc_init()
164 for (i = 0; i < sc->num_cpus; i++) { in aspeed_ast2400_soc_init()
165 object_initialize_child(obj, "cpu[*]", &a->cpu[i], in aspeed_ast2400_soc_init()
169 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); in aspeed_ast2400_soc_init()
170 object_initialize_child(obj, "scu", &s->scu, typename); in aspeed_ast2400_soc_init()
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/openbmc/linux/drivers/gpu/drm/ast/
H A Dast_main.c14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
70 struct drm_device *dev = &ast->base; in ast_enable_mmio()
74 return devm_add_action_or_reset(dev->dev, ast_enable_mmio_release, ast); in ast_enable_mmio()
84 struct drm_device *dev = &ast->base; in ast_device_config_init()
85 struct pci_dev *pdev = to_pci_dev(dev->dev); in ast_device_config_init()
86 struct device_node *np = dev->dev->of_node; in ast_device_config_init()
92 * Find configuration mode and read SCU revision in ast_device_config_init()
95 ast->config_mode = ast_use_defaults; in ast_device_config_init()
97 /* Check if we have device-tree properties */ in ast_device_config_init()
98 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", &data)) { in ast_device_config_init()
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/openbmc/u-boot/drivers/ram/aspeed/
H A Dsdram_ast2500.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2012-2020 ASPEED Technology Inc.
20 #include <dt-bindings/clock/ast2500-clock.h>
22 /* in order to speed up DRAM init time, write pre-defined values to registers
26 /* bit-field of m_pll_param */
86 struct ast2500_scu *scu; member
93 writel(0, &phy->phy[2]); in ast2500_sdrammc_init_phy()
94 writel(0, &phy->phy[6]); in ast2500_sdrammc_init_phy()
95 writel(0, &phy->phy[8]); in ast2500_sdrammc_init_phy()
96 writel(0, &phy->phy[10]); in ast2500_sdrammc_init_phy()
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/openbmc/qemu/docs/system/arm/
H A Daspeed.rst1 …ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, `…
6 Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the
7 AST2500 with an ARM1176JZS CPU (800MHz), the AST2600
8 with dual cores ARM Cortex-A7 CPUs (1.2GHz) and more recently the AST2700
9 with quad cores ARM Cortex-A35 64 bits CPUs (1.6GHz)
16 - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
17 - ``quanta-q71l-bmc`` OpenBMC Quanta BMC
18 - ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S)
19 - ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176)
21 AST2500 SoC based machines :
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/openbmc/linux/drivers/clk/
H A Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
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/openbmc/qemu/include/hw/watchdog/
H A Dwdt_aspeed.h4 * Copyright (C) 2016-2017 IBM Corp.
7 * COPYING file in the top-level directory.
19 #define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400"
20 #define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500"
21 #define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
22 #define TYPE_ASPEED_2700_WDT TYPE_ASPEED_WDT "-ast2700"
23 #define TYPE_ASPEED_1030_WDT TYPE_ASPEED_WDT "-ast1030"
37 AspeedSCUState *scu; member
/openbmc/qemu/include/hw/timer/
H A Daspeed_timer.h20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
31 #define TYPE_ASPEED_2400_TIMER TYPE_ASPEED_TIMER "-ast2400"
32 #define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500"
33 #define TYPE_ASPEED_2600_TIMER TYPE_ASPEED_TIMER "-ast2600"
34 #define TYPE_ASPEED_1030_TIMER TYPE_ASPEED_TIMER "-ast1030"
67 AspeedSCUState *scu; member
/openbmc/qemu/include/hw/misc/
H A Daspeed_scu.h9 * the COPYING file in the top-level directory.
17 #define TYPE_ASPEED_SCU "aspeed.scu"
19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
22 #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700"
23 #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700"
24 #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"
84 * arch/arm/mach-aspeed/include/mach/regs-scu.h
86 * Copyright (C) 2012-2020 ASPEED Technology Inc.
[all …]

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