Lines Matching +full:ast2500 +full:- +full:scu
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2012-2020 ASPEED Technology Inc.
20 #include <dt-bindings/clock/ast2500-clock.h>
22 /* in order to speed up DRAM init time, write pre-defined values to registers
26 /* bit-field of m_pll_param */
86 struct ast2500_scu *scu; member
93 writel(0, &phy->phy[2]); in ast2500_sdrammc_init_phy()
94 writel(0, &phy->phy[6]); in ast2500_sdrammc_init_phy()
95 writel(0, &phy->phy[8]); in ast2500_sdrammc_init_phy()
96 writel(0, &phy->phy[10]); in ast2500_sdrammc_init_phy()
97 writel(0, &phy->phy[12]); in ast2500_sdrammc_init_phy()
98 writel(0, &phy->phy[42]); in ast2500_sdrammc_init_phy()
99 writel(0, &phy->phy[44]); in ast2500_sdrammc_init_phy()
101 writel(0x86000000, &phy->phy[16]); in ast2500_sdrammc_init_phy()
102 writel(0x00008600, &phy->phy[17]); in ast2500_sdrammc_init_phy()
103 writel(0x80000000, &phy->phy[18]); in ast2500_sdrammc_init_phy()
104 writel(0x80808080, &phy->phy[19]); in ast2500_sdrammc_init_phy()
111 struct ast2500_sdrammc_regs *regs = info->regs; in ast2500_ddr_phy_init_process()
113 writel(0, ®s->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
114 writel(0x4040, &info->phy->phy[51]); in ast2500_ddr_phy_init_process()
116 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
117 while ((readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT)) in ast2500_ddr_phy_init_process()
120 ®s->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
125 writel(0, &info->regs->phy_ctrl[0]); in ast2500_sdrammc_set_vref()
126 writel((vref << 8) | 0x6, &info->phy->phy[48]); in ast2500_sdrammc_set_vref()
132 struct ast2500_sdrammc_regs *regs = info->regs; in ast2500_ddr_cbr_test()
140 (0x5c << SDRAM_REFRESH_PERIOD_SHIFT), ®s->refresh_timing); in ast2500_ddr_cbr_test()
141 writel((0xfff << SDRAM_TEST_LEN_SHIFT), ®s->test_addr); in ast2500_ddr_cbr_test()
142 writel(0xff00ff00, ®s->test_init_val); in ast2500_ddr_cbr_test()
144 SDRAM_TEST_ERRSTOP, ®s->ecc_test_ctrl); in ast2500_ddr_cbr_test()
146 while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE)) in ast2500_ddr_cbr_test()
149 if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) { in ast2500_ddr_cbr_test()
150 ret = -EIO; in ast2500_ddr_cbr_test()
154 ®s->ecc_test_ctrl); in ast2500_ddr_cbr_test()
155 while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE)) in ast2500_ddr_cbr_test()
157 if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) { in ast2500_ddr_cbr_test()
158 ret = -EIO; in ast2500_ddr_cbr_test()
164 writel(0, ®s->refresh_timing); in ast2500_ddr_cbr_test()
165 writel(0, ®s->ecc_test_ctrl); in ast2500_ddr_cbr_test()
201 u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK) in ast2500_sdrammc_get_vga_mem_size()
209 struct ast2500_sdrammc_regs *regs = info->regs; in ast2500_sdrammc_update_size()
218 cap_param = (readl(&info->regs->config) & SDRAM_CONF_CAP_MASK) >> SDRAM_CONF_CAP_SHIFT; in ast2500_sdrammc_update_size()
221 info->info.base = CONFIG_SYS_SDRAM_BASE; in ast2500_sdrammc_update_size()
222 info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info); in ast2500_sdrammc_update_size()
224 if (0 == (readl(®s->config) & SDRAM_CONF_ECC_EN)) in ast2500_sdrammc_update_size()
227 hw_size = readl(®s->ecc_range_ctrl) & GENMASK(29, 20); in ast2500_sdrammc_update_size()
230 info->info.size = hw_size; in ast2500_sdrammc_update_size()
263 --cap_param; in ast2500_sdrammc_calc_size()
268 clrsetbits_le32(&info->regs->ac_timing[1], in ast2500_sdrammc_calc_size()
273 info->info.base = CONFIG_SYS_SDRAM_BASE; in ast2500_sdrammc_calc_size()
274 info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info); in ast2500_sdrammc_calc_size()
275 clrsetbits_le32(&info->regs->config, in ast2500_sdrammc_calc_size()
283 struct ast2500_sdrammc_regs *regs = info->regs; in ast2500_sdrammc_ecc_enable()
288 if (conf_size > info->info.size) { in ast2500_sdrammc_ecc_enable()
291 info->info.size / SDRAM_SIZE_1MB); in ast2500_sdrammc_ecc_enable()
292 conf_size = info->info.size; in ast2500_sdrammc_ecc_enable()
294 conf_size = info->info.size; in ast2500_sdrammc_ecc_enable()
297 info->info.size = (((conf_size / 9) * 8) >> 20) << 20; in ast2500_sdrammc_ecc_enable()
298 writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl); in ast2500_sdrammc_ecc_enable()
299 reg = readl(®s->config) | in ast2500_sdrammc_ecc_enable()
301 writel(reg, ®s->config); in ast2500_sdrammc_ecc_enable()
303 writel(0, ®s->test_init_val); in ast2500_sdrammc_ecc_enable()
304 writel(0, ®s->test_addr); in ast2500_sdrammc_ecc_enable()
305 writel(0x221, ®s->ecc_test_ctrl); in ast2500_sdrammc_ecc_enable()
306 while (0 == (readl(®s->ecc_test_ctrl) & BIT(12))) in ast2500_sdrammc_ecc_enable()
308 writel(0, ®s->ecc_test_ctrl); in ast2500_sdrammc_ecc_enable()
309 writel(BIT(31), ®s->intr_ctrl); in ast2500_sdrammc_ecc_enable()
310 writel(0, ®s->intr_ctrl); in ast2500_sdrammc_ecc_enable()
312 writel(0x400, ®s->ecc_test_ctrl); in ast2500_sdrammc_ecc_enable()
332 writel(conf, &info->regs->config); in ast2500_sdrammc_init_ddr4()
334 writel(ddr4_ac_timing[i], &info->regs->ac_timing[i]); in ast2500_sdrammc_init_ddr4()
336 writel(DDR4_MR46_MODE, &info->regs->mr46_mode_setting); in ast2500_sdrammc_init_ddr4()
337 writel(DDR4_MR5_MODE, &info->regs->mr5_mode_setting); in ast2500_sdrammc_init_ddr4()
338 writel(DDR4_MR02_MODE, &info->regs->mr02_mode_setting); in ast2500_sdrammc_init_ddr4()
339 writel(DDR4_MR13_MODE, &info->regs->mr13_mode_setting); in ast2500_sdrammc_init_ddr4()
343 &info->phy->phy[ddr4_phy_config.index[i]]); in ast2500_sdrammc_init_ddr4()
346 writel(power_control, &info->regs->power_control); in ast2500_sdrammc_init_ddr4()
358 &info->regs->refresh_timing); in ast2500_sdrammc_init_ddr4()
360 setbits_le32(&info->regs->power_control, in ast2500_sdrammc_init_ddr4()
365 setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_INIT_EN); in ast2500_sdrammc_init_ddr4()
366 while (!(readl(&info->regs->config) & SDRAM_CONF_CACHE_INIT_DONE)) in ast2500_sdrammc_init_ddr4()
368 setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_EN); in ast2500_sdrammc_init_ddr4()
370 writel(SDRAM_MISC_DDR4_TREFRESH, &info->regs->misc_control); in ast2500_sdrammc_init_ddr4()
372 if (dev_read_bool(dev, "aspeed,ecc-enabled")) { in ast2500_sdrammc_init_ddr4()
375 ecc_size = dev_read_u32_default(dev, "aspeed,ecc-size-mb", 0); in ast2500_sdrammc_init_ddr4()
393 | SDRAM_REQ_MEMCHECK, &info->regs->req_limit_mask); in ast2500_sdrammc_init_ddr4()
400 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); in ast2500_sdrammc_unlock()
401 while (!readl(&info->regs->protection_key)) in ast2500_sdrammc_unlock()
407 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); in ast2500_sdrammc_lock()
408 while (readl(&info->regs->protection_key)) in ast2500_sdrammc_lock()
415 struct ast2500_sdrammc_regs *regs = priv->regs; in ast2500_sdrammc_init_required()
420 ecc_requested = dev_read_bool(dev, "aspeed,ecc-enabled"); in ast2500_sdrammc_init_required()
421 ecc_enabled = readl(®s->config) & SDRAM_CONF_ECC_EN; in ast2500_sdrammc_init_required()
422 dram_ready = readl(&priv->scu->vga_handshake[0]) & BIT(6); in ast2500_sdrammc_init_required()
436 struct ast2500_sdrammc_regs *regs = priv->regs; in ast2500_sdrammc_probe()
439 int ret = clk_get_by_index(dev, 0, &priv->ddr_clk); in ast2500_sdrammc_probe()
447 /* find the SCU base address from the aspeed clock device */ in ast2500_sdrammc_probe()
454 priv->scu = devfdt_get_addr_ptr(clk_dev); in ast2500_sdrammc_probe()
456 if (IS_ERR(priv->scu)) { in ast2500_sdrammc_probe()
457 debug("%s(): can't get SCU\n", __func__); in ast2500_sdrammc_probe()
458 return PTR_ERR(priv->scu); in ast2500_sdrammc_probe()
464 if (!(readl(&priv->regs->config) & SDRAM_CONF_CACHE_EN)) { in ast2500_sdrammc_probe()
465 setbits_le32(&priv->regs->config, in ast2500_sdrammc_probe()
467 while (!(readl(&priv->regs->config) & in ast2500_sdrammc_probe()
470 setbits_le32(&priv->regs->config, SDRAM_CONF_CACHE_EN); in ast2500_sdrammc_probe()
473 writel(SDRAM_MISC_DDR4_TREFRESH, &priv->regs->misc_control); in ast2500_sdrammc_probe()
478 reg = readl(&priv->scu->m_pll_param); in ast2500_sdrammc_probe()
480 writel(reg, &priv->scu->m_pll_param); in ast2500_sdrammc_probe()
483 writel(reg, &priv->scu->m_pll_param); in ast2500_sdrammc_probe()
485 clk_set_rate(&priv->ddr_clk, priv->clock_rate); in ast2500_sdrammc_probe()
491 ®s->power_control); in ast2500_sdrammc_probe()
492 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); in ast2500_sdrammc_probe()
495 writel(~(SDRAM_REQ_CPU | SDRAM_REQ_AHB), ®s->req_limit_mask); in ast2500_sdrammc_probe()
498 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); in ast2500_sdrammc_probe()
500 setbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL); in ast2500_sdrammc_probe()
502 ast2500_sdrammc_init_phy(priv->phy); in ast2500_sdrammc_probe()
503 if (readl(&priv->scu->hwstrap) & SCU_HWSTRAP_DDR4) { in ast2500_sdrammc_probe()
507 return -EINVAL; in ast2500_sdrammc_probe()
510 clrbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL); in ast2500_sdrammc_probe()
513 setbits_le32(&priv->scu->vga_handshake[0], BIT(6) | BIT(7)); in ast2500_sdrammc_probe()
522 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); in ast2500_sdrammc_ofdata_to_platdata()
523 priv->phy = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); in ast2500_sdrammc_ofdata_to_platdata()
525 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), in ast2500_sdrammc_ofdata_to_platdata()
526 "clock-frequency", 0); in ast2500_sdrammc_ofdata_to_platdata()
527 if (!priv->clock_rate) { in ast2500_sdrammc_ofdata_to_platdata()
529 return -EINVAL; in ast2500_sdrammc_ofdata_to_platdata()
539 *info = priv->info; in ast2500_sdrammc_get_info()
549 { .compatible = "aspeed,ast2500-sdrammc" },