Lines Matching +full:ast2500 +full:- +full:scu
1 // SPDX-License-Identifier: GPL-2.0
10 #include <clk-uclass.h>
15 #include <dt-bindings/clock/ast2500-clock.h>
16 #include <dt-bindings/reset/ast2500-reset.h>
36 * For H-PLL and M-PLL the formula is
38 * M - Numerator
39 * N - Denumerator
40 * P - Post Divider
43 * D-PLL and D2-PLL have extra divider (OD + 1), which is not
52 extern u32 ast2500_get_clkin(struct ast2500_scu *scu) in ast2500_get_clkin() argument
54 return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ in ast2500_get_clkin()
59 * Get the rate of the M-PLL clock from input clock frequency and
60 * the value of the M-PLL Parameter Register.
62 extern u32 ast2500_get_mpll_rate(struct ast2500_scu *scu) in ast2500_get_mpll_rate() argument
64 u32 clkin = ast2500_get_clkin(scu); in ast2500_get_mpll_rate()
65 u32 mpll_reg = readl(&scu->m_pll_param); in ast2500_get_mpll_rate()
77 * Get the rate of the H-PLL clock from input clock frequency and
78 * the value of the H-PLL Parameter Register.
80 extern u32 ast2500_get_hpll_rate(struct ast2500_scu *scu) in ast2500_get_hpll_rate() argument
82 u32 clkin = ast2500_get_clkin(scu); in ast2500_get_hpll_rate()
83 u32 hpll_reg = readl(&scu->h_pll_param); in ast2500_get_hpll_rate()
96 * Get the rate of the D-PLL clock from input clock frequency and
97 * the value of the D-PLL Parameter Register.
99 extern u32 ast2500_get_dpll_rate(struct ast2500_scu *scu) in ast2500_get_dpll_rate() argument
101 u32 clkin = ast2500_get_clkin(scu); in ast2500_get_dpll_rate()
102 u32 dpll_reg = readl(&scu->d_pll_param); in ast2500_get_dpll_rate()
113 * Get the rate of the D2-PLL clock from input clock frequency and
114 * the value of the D2-PLL Parameter Register.
116 extern u32 ast2500_get_d2pll_rate(struct ast2500_scu *scu) in ast2500_get_d2pll_rate() argument
118 u32 clkin = ast2500_get_clkin(scu); in ast2500_get_d2pll_rate()
119 u32 d2pll_reg = readl(&scu->d2_pll_param); in ast2500_get_d2pll_rate()
133 static u32 ast2500_get_hclk(struct ast2500_scu *scu) in ast2500_get_hclk() argument
135 ulong ahb_div = 1 + ((readl(&scu->hwstrap) in ast2500_get_hclk()
142 rate = ast2500_get_hpll_rate(scu); in ast2500_get_hclk()
146 static u32 ast2500_get_pclk(struct ast2500_scu *scu) in ast2500_get_pclk() argument
149 ulong apb_div = 4 + 4 * ((readl(&scu->clk_sel1) in ast2500_get_pclk()
152 rate = ast2500_get_hpll_rate(scu); in ast2500_get_pclk()
157 static u32 ast2500_get_sdio_clk_rate(struct ast2500_scu *scu) in ast2500_get_sdio_clk_rate() argument
159 u32 clkin = ast2500_get_hpll_rate(scu); in ast2500_get_sdio_clk_rate()
160 u32 clk_sel = readl(&scu->clk_sel1); in ast2500_get_sdio_clk_rate()
168 static u32 ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_idx) in ast2500_get_uart_clk_rate() argument
171 * ast2500 datasheet is very confusing when it comes to UART clocks, in ast2500_get_uart_clk_rate()
179 if (readl(&scu->misc_ctrl2) & in ast2500_get_uart_clk_rate()
180 (1 << (uart_idx - 1 + SCU_MISC2_UARTCLK_SHIFT))) in ast2500_get_uart_clk_rate()
185 if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13) in ast2500_get_uart_clk_rate()
193 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); in ast2500_clk_get_rate()
196 switch (clk->id) { in ast2500_clk_get_rate()
198 rate = ast2500_get_hpll_rate(priv->scu); in ast2500_clk_get_rate()
201 rate = ast2500_get_mpll_rate(priv->scu); in ast2500_clk_get_rate()
204 rate = ast2500_get_dpll_rate(priv->scu); in ast2500_clk_get_rate()
207 rate = ast2500_get_d2pll_rate(priv->scu); in ast2500_clk_get_rate()
210 rate = ast2500_get_hclk(priv->scu); in ast2500_clk_get_rate()
213 rate = ast2500_get_pclk(priv->scu); in ast2500_clk_get_rate()
216 rate = ast2500_get_uart_clk_rate(priv->scu, 1); in ast2500_clk_get_rate()
219 rate = ast2500_get_uart_clk_rate(priv->scu, 2); in ast2500_clk_get_rate()
222 rate = ast2500_get_uart_clk_rate(priv->scu, 3); in ast2500_clk_get_rate()
225 rate = ast2500_get_uart_clk_rate(priv->scu, 4); in ast2500_clk_get_rate()
228 rate = ast2500_get_uart_clk_rate(priv->scu, 5); in ast2500_clk_get_rate()
231 rate = ast2500_get_sdio_clk_rate(priv->scu); in ast2500_clk_get_rate()
235 return -ENOENT; in ast2500_clk_get_rate()
261 if (default_cfg->input_rate == input_rate && in ast2500_get_clock_config_default()
262 default_cfg->rate == requested_rate) { in ast2500_get_clock_config_default()
263 *cfg = default_cfg->cfg; in ast2500_get_clock_config_default()
272 * @input_rate - the rate of input clock in Hz
273 * @requested_rate - desired output rate in Hz
274 * @div - this is an IN/OUT parameter, at input all fields of the config
317 if (new_rate_khz - rate_khz < delta) { in ast2500_calc_clock_config()
318 delta = new_rate_khz - rate_khz; in ast2500_calc_clock_config()
329 static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate) in ast2500_configure_ddr() argument
331 ulong clkin = ast2500_get_clkin(scu); in ast2500_configure_ddr()
341 mpll_reg = readl(&scu->m_pll_param); in ast2500_configure_ddr()
348 writel(mpll_reg, &scu->m_pll_param); in ast2500_configure_ddr()
350 return ast2500_get_mpll_rate(scu); in ast2500_configure_ddr()
353 static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate) in ast2500_configure_d2pll() argument
370 ulong clkin = ast2500_get_clkin(scu); in ast2500_configure_d2pll()
375 | SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]); in ast2500_configure_d2pll()
379 * This would disconnect it from D2-PLL. in ast2500_configure_d2pll()
381 clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF, in ast2500_configure_d2pll()
390 &scu->d2_pll_param); in ast2500_configure_d2pll()
392 clrbits_le32(&scu->d2_pll_ext_param[0], in ast2500_configure_d2pll()
395 clrsetbits_le32(&scu->misc_ctrl2, in ast2500_configure_d2pll()
406 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); in ast2500_clk_set_rate()
409 switch (clk->id) { in ast2500_clk_set_rate()
412 new_rate = ast2500_configure_ddr(priv->scu, rate); in ast2500_clk_set_rate()
416 new_rate = ast2500_configure_d2pll(priv->scu, rate); in ast2500_clk_set_rate()
420 return -ENOENT; in ast2500_clk_set_rate()
429 static ulong ast2500_configure_mac(struct ast2500_scu *scu, int index) in ast2500_configure_mac() argument
431 ulong hpll_rate = ast2500_get_hpll_rate(scu); in ast2500_configure_mac()
447 hwstrap = readl(&scu->hwstrap); in ast2500_configure_mac()
475 return -EINVAL; in ast2500_configure_mac()
478 clrsetbits_le32(&scu->clk_sel1, SCU_MACCLK_MASK, in ast2500_configure_mac()
479 ((divisor - 2) / 2) << SCU_MACCLK_SHIFT); in ast2500_configure_mac()
482 * Disable MAC, start its clock and re-enable it. in ast2500_configure_mac()
486 setbits_le32(&scu->sysreset_ctrl1, reset_bit); in ast2500_configure_mac()
488 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit); in ast2500_configure_mac()
490 clrbits_le32(&scu->sysreset_ctrl1, reset_bit); in ast2500_configure_mac()
494 &scu->clk_duty_sel); in ast2500_configure_mac()
496 writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay); in ast2500_configure_mac()
497 writel(clk_delay_settings, &scu->mac_clk_delay_100M); in ast2500_configure_mac()
498 writel(clk_delay_settings, &scu->mac_clk_delay_10M); in ast2500_configure_mac()
504 static ulong ast2500_enable_sdclk(struct ast2500_scu *scu) in ast2500_enable_sdclk() argument
512 setbits_le32(&scu->sysreset_ctrl1, reset_bit); in ast2500_enable_sdclk()
515 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit); in ast2500_enable_sdclk()
517 clrbits_le32(&scu->sysreset_ctrl1, reset_bit); in ast2500_enable_sdclk()
526 static ulong ast2500_enable_extsdclk(struct ast2500_scu *scu) in ast2500_enable_extsdclk() argument
528 u32 clk_sel = readl(&scu->clk_sel1); in ast2500_enable_extsdclk()
533 // SDCLK = G4 H-PLL / 4, G5 = H-PLL /8 in ast2500_enable_extsdclk()
536 writel(clk_sel, &scu->clk_sel1); in ast2500_enable_extsdclk()
539 setbits_le32(&scu->clk_sel1, enableclk_bit); in ast2500_enable_extsdclk()
544 static ulong ast2500_enable_usbahclk(struct ast2500_scu *scu) in ast2500_enable_usbahclk() argument
552 setbits_le32(&scu->sysreset_ctrl1, reset_bit); in ast2500_enable_usbahclk()
554 setbits_le32(&scu->clk_stop_ctrl1, clkstop_bit); in ast2500_enable_usbahclk()
557 clrbits_le32(&scu->sysreset_ctrl1, reset_bit); in ast2500_enable_usbahclk()
562 static ulong ast2500_enable_usbbhclk(struct ast2500_scu *scu) in ast2500_enable_usbbhclk() argument
570 setbits_le32(&scu->sysreset_ctrl1, reset_bit); in ast2500_enable_usbbhclk()
572 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit); in ast2500_enable_usbbhclk()
575 clrbits_le32(&scu->sysreset_ctrl1, reset_bit); in ast2500_enable_usbbhclk()
582 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); in ast2500_clk_enable()
584 switch (clk->id) { in ast2500_clk_enable()
591 ast2500_configure_mac(priv->scu, 1); in ast2500_clk_enable()
594 ast2500_configure_mac(priv->scu, 2); in ast2500_clk_enable()
597 ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE); in ast2500_clk_enable()
600 ast2500_enable_sdclk(priv->scu); in ast2500_clk_enable()
603 ast2500_enable_extsdclk(priv->scu); in ast2500_clk_enable()
606 ast2500_enable_usbahclk(priv->scu); in ast2500_clk_enable()
609 ast2500_enable_usbbhclk(priv->scu); in ast2500_clk_enable()
613 return -ENOENT; in ast2500_clk_enable()
630 priv->scu = devfdt_get_addr_ptr(dev); in ast2500_clk_probe()
631 if (IS_ERR(priv->scu)) in ast2500_clk_probe()
632 return PTR_ERR(priv->scu); in ast2500_clk_probe()
642 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); in ast2500_clk_bind()
691 if (ret == -ENOTSUPP) { in soc_clk_dump()
711 { .compatible = "aspeed,ast2500-scu" },