Home
last modified time | relevance | path

Searched +full:assert +full:- +full:falling +full:- +full:edge (Results 1 – 25 of 29) sorted by relevance

12

/openbmc/linux/Documentation/devicetree/bindings/pps/
H A Dpps-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pps/pps-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabio Estevam <festevam@gmail.com>
14 const: pps-gpio
20 echo-gpios:
24 echo-active-ms:
27 assert-falling-edge:
28 description: Indicates a falling edge assert, when present. Rising edge if absent.
[all …]
/openbmc/linux/sound/drivers/
H A Dportman2x4.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) by Levent Guendogdu <levon@feature-it.com>
9 * - cleanup and rewrite
11 * - source code cleanup
13 * - fixed compilation problem with alsa 1.0.6a (removed MODULE_CLASSES,
17 * - added 2.6 kernel support
19 …* - added parport_unregister_driver to the startup routine if the driver fails to detect a po…
20 * - added support for all 4 output ports in portman_putmidi
22 * - added checks for opened input device in interrupt handler
24 * - ported from alsa 0.5 to 1.0
[all …]
/openbmc/phosphor-buttons/src/
H A Dgpio.cpp8 // http://www.apache.org/licenses/LICENSE-2.0
26 #include <phosphor-logging/lg2.hpp>
41 if (state == GpioState::assert) in setGpioState()
43 writeBuffer = GpioValueMap[polarity].assert; in setGpioState()
60 int result = -1; in getGpioState()
80 GpioState gpioState = (readBuffer == GpioValueMap[polarity].assert) in getGpioState()
81 ? (GpioState::assert) in getGpioState()
139 lg2::error("{NAME}: Error configuring gpio-{NUM}: {RESULT}", "NAME", in configGroupGpio()
184 return -1; in configGpio()
205 return -1; in configGpio()
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp157c-odyssey.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp157c-odyssey-som.dtsi"
11 model = "Seeed Studio Odyssey-STM32MP157C Board";
12 compatible = "seeed,stm32mp157c-odyssey",
13 "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
21 stdout-path = "serial0:115200n8";
26 pinctrl-names = "default", "sleep";
27 pinctrl-0 = <&dcmi_pins_b>;
28 pinctrl-1 = <&dcmi_sleep_pins_b>;
[all …]
H A Dstm32mp15xx-dhcom-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
6 #include "stm32mp15-pinctrl.dtsi"
7 #include "stm32mp15xxaa-pinctrl.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/mfd/st,stpmic1.h>
24 reserved-memory {
25 #address-cells = <1>;
26 #size-cells = <1>;
30 compatible = "shared-dma-pool";
[all …]
/openbmc/linux/drivers/scsi/
H A DNCR5380.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * +1 (303) 666-5836
19 * 1+ (719) 578-3400
20 * 1+ (800) 334-5454
65 * either arbitration is occurring or the phase-indicating signals (
66 * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
74 #define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
76 #define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
79 #define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
80 #define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
[all …]
/openbmc/linux/drivers/pps/clients/
H A Dpps-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pps-gpio.c -- PPS client driver using GPIO
9 #define PPS_GPIO_NAME "pps-gpio"
55 rising_edge = gpiod_get_value(info->gpio_pin); in pps_gpio_irq_handler()
56 if ((rising_edge && !info->assert_falling_edge) || in pps_gpio_irq_handler()
57 (!rising_edge && info->assert_falling_edge)) in pps_gpio_irq_handler()
58 pps_event(info->pps, &ts, PPS_CAPTUREASSERT, data); in pps_gpio_irq_handler()
59 else if (info->capture_clear && in pps_gpio_irq_handler()
60 ((rising_edge && info->assert_falling_edge) || in pps_gpio_irq_handler()
61 (!rising_edge && !info->assert_falling_edge))) in pps_gpio_irq_handler()
[all …]
/openbmc/linux/drivers/staging/greybus/
H A Darche-platform.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2014-2015 Google Inc.
6 * Copyright 2014-2015 Linaro Ltd.
39 WD_STATE_BOOT_INIT, /* WD = falling edge (low) */
40 WD_STATE_COLDBOOT_TRIG, /* WD = rising edge (high), > 30msec */
51 struct gpio_desc *wake_detect; /* bi-dir,maps to WAKE_MOD & WAKE_FRAME signals */
73 /* Requires calling context to hold arche_pdata->platform_state_mutex */
77 arche_pdata->state = state; in arche_platform_set_state()
80 /* Requires arche_pdata->wake_lock is held by calling context */
84 arche_pdata->wake_detect_state = state; in arche_platform_set_wake_detect_state()
[all …]
H A Darche-apb-ctrl.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2014-2015 Google Inc.
6 * Copyright 2014-2015 Linaro Ltd.
68 struct device *dev = &pdev->dev; in coldboot_seq()
72 if (apb->init_disabled || in coldboot_seq()
73 apb->state == ARCHE_PLATFORM_STATE_ACTIVE) in coldboot_seq()
77 assert_reset(apb->resetn); in coldboot_seq()
79 if (apb->state == ARCHE_PLATFORM_STATE_FW_FLASHING && apb->spi_en) in coldboot_seq()
80 devm_gpiod_put(dev, apb->spi_en); in coldboot_seq()
83 if (!IS_ERR(apb->vcore)) { in coldboot_seq()
[all …]
/openbmc/linux/drivers/pinctrl/starfive/
H A Dpinctrl-starfive-jh7100.c1 // SPDX-License-Identifier: GPL-2.0
26 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
29 #include "../pinctrl-utils.h"
33 #define DRIVER_NAME "pinctrl-starfive"
37 * https://github.com/starfive-tech/JH7100_Docs
48 * The following 32-bit registers come in pairs, but only the offset of the
49 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
50 * the second GPIO 32-63.
54 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
55 * interrupt is level-triggered.
[all …]
H A Dpinctrl-starfive-jh7110.c1 // SPDX-License-Identifier: GPL-2.0
27 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
30 #include "../pinctrl-utils.h"
33 #include "pinctrl-starfive-jh7110.h"
52 * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
100 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_pin_dbg_show()
102 seq_printf(s, "%s", dev_name(pctldev->dev)); in jh7110_pin_dbg_show()
104 if (pin < sfp->gc.ngpio) { in jh7110_pin_dbg_show()
107 u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset); in jh7110_pin_dbg_show()
108 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset); in jh7110_pin_dbg_show()
[all …]
/openbmc/linux/drivers/usb/dwc3/
H A Ddwc3-qcom.c1 // SPDX-License-Identifier: GPL-2.0
4 * Inspired by dwc3-of-simple.c
123 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
125 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
128 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
130 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
142 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST; in dwc3_qcom_vbus_notifier()
154 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL; in dwc3_qcom_host_notifier()
161 struct device *dev = qcom->dev; in dwc3_qcom_register_extcon()
165 if (!of_property_read_bool(dev->of_node, "extcon")) in dwc3_qcom_register_extcon()
[all …]
/openbmc/u-boot/drivers/spi/
H A Dpic32_spi.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/clock/microchip,clock.h>
36 #define PIC32_SPI_CTRL_CKE BIT(8) /* Tx on falling edge */
67 u32 speed_hz; /* spi-clk rate */
84 writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set); in pic32_spi_enable()
89 writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr); in pic32_spi_disable()
94 u32 sr = readl(&priv->regs->status.raw); in pic32_spi_rx_fifo_level()
101 u32 sr = readl(&priv->regs->status.raw); in pic32_spi_tx_fifo_level()
111 tx_left = (priv->tx_end - priv->tx) / n_bytes; in pic32_tx_max()
112 tx_room = priv->fifo_n_word - pic32_spi_tx_fifo_level(priv); in pic32_tx_max()
[all …]
/openbmc/linux/drivers/ata/
H A Dpata_octeon_cf.c8 * Copyright (C) 2005 - 2012 Cavium Inc.
31 * -- 8 bits no irq, no DMA
32 * -- 16 bits no irq, no DMA
33 * -- 16 bits True IDE mode with DMA, but no irq.
106 reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */ in octeon_cf_set_boot_reg_cfg()
108 reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */ in octeon_cf_set_boot_reg_cfg()
128 struct octeon_cf_port *cf_port = ap->private_data; in octeon_cf_set_piomode()
150 BUG_ON(ata_timing_compute(dev, dev->pio_mode, &timing, T, T)); in octeon_cf_set_piomode()
154 t2--; in octeon_cf_set_piomode()
158 trh--; in octeon_cf_set_piomode()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_optc.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
33 optc1->tg_regs->reg
36 optc1->base.ctx
40 optc1->tg_shift->field_name, optc1->tg_mask->field_name
45 * apply_front_porch_workaround() - This is a workaround for a bug that has
54 if (timing->flags.INTERLACE == 1) { in apply_front_porch_workaround()
55 if (timing->v_front_porch < 2) in apply_front_porch_workaround()
56 timing->v_front_porch = 2; in apply_front_porch_workaround()
58 if (timing->v_front_porch < 1) in apply_front_porch_workaround()
59 timing->v_front_porch = 1; in apply_front_porch_workaround()
[all …]
/openbmc/linux/lib/zstd/decompress/
H A Dzstd_decompress_block.c5 * This source code is licensed under both the BSD-style license (found in the
8 * You may select, at your option, one of the above-listed licenses.
14 /*-*******************************************************
50 /*-*************************************************************
63 bpPtr->lastBlock = cBlockHeader & 1; in ZSTD_getcBlockSize()
64 bpPtr->blockType = (blockType_e)((cBlockHeader >> 1) & 3); in ZSTD_getcBlockSize()
65 bpPtr->origSize = cSize; /* only useful for RLE */ in ZSTD_getcBlockSize()
66 if (bpPtr->blockType == bt_rle) return 1; in ZSTD_getcBlockSize()
67 RETURN_ERROR_IF(bpPtr->blockType == bt_reserved, corruption_detected, ""); in ZSTD_getcBlockSize()
79 dctx->litBuffer = (BYTE*)dst + ZSTD_BLOCKSIZE_MAX + WILDCOPY_OVERLENGTH; in ZSTD_allocateLiteralsBuffer()
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
[all …]
/openbmc/qemu/hw/gpio/
H A Daspeed_gpio.c4 * Copyright (C) 2017-2019 IBM Corp.
6 * SPDX-License-Identifier: GPL-2.0-or-later
10 #include "qemu/host-utils.h"
36 * -----------------------------
37 * | 0 | 0 | 0 | falling-edge
38 * | 0 | 0 | 1 | rising-edge
39 * | 0 | 1 | 0 | level-low
40 * | 0 | 1 | 1 | level-high
41 * | 1 | X | X | dual-edge
168 /* AST2600 only - 1.8V gpios */
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpio-pca953x.c1 // SPDX-License-Identifier: GPL-2.0-only
126 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
138 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0); in pca953x_acpi_get_irq()
152 * relative. Since first controller (gpio-sch.c) and
153 * second (gpio-dwapb.c) are at the fixed bases, we may
175 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
227 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); in pca953x_bank_shift()
249 * - Standard set, below 0x40, each port can be replicated up to 8 times
250 * - PCA953x standard
255 * - PCA957x with mixed up registers
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
11 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
18 #include <linux/dma-mapping.h>
74 #define DRV_NAME "spi-bcm2835"
83 * struct bcm2835_spi - BCM2835 SPI controller
99 * @debugfs_dir: the debugfs directory - neede to remove debugfs when
113 * @fill_tx_desc: preallocated TX DMA descriptor used for RX-only transfers
146 * struct bcm2835_spidev - BCM2835 SPI target
147 * @prepare_cs: precalculated CS register value for ->prepare_message()
[all …]
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1 // SPDX-License-Identifier: GPL-2.0
55 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) in ddr3_tip_dynamic_read_leveling()
59 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
60 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
81 * assuming non multi-CS configuration in ddr3_tip_dynamic_read_leveling()
118 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
119 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
121 tm->interface_params[if_id].speed_bin_index; in ddr3_tip_dynamic_read_leveling()
199 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
200 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c81 dc->ctx
84 dc->ctx->logger
86 static const char DC_BUILD_ID[] = "production-build";
91 * DC is the OS-agnostic component of the amdgpu DC driver.
98 * struct dc - The central struct. One per driver. Created on driver load,
101 * struct dc_context - One per driver.
104 * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
107 * struct dc_sink - One per display. Created on boot or hotplug.
110 * sinks (in the Multi-Stream Transport case)
112 * struct resource_pool - One per driver. Represents the hw blocks not in the
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Dni_mio_common.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Hardware driver for DAQ-STC based boards
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
17 * 340747b.pdf AT-MIO E series Register Level Programmer Manual
19 * 340934b.pdf DAQ-STC reference manual
31 * 321791a.pdf discontinuation of at-mio-16e-10 rev. c
32 * 321808a.pdf about at-mio-16e-10 rev P
33 * 321837a.pdf discontinuation of at-mio-16de-10 rev d
[all …]
/openbmc/linux/drivers/net/ethernet/sun/
H A Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
104 len of non-reassembly pkt
183 #define BIM_CFG_64BIT_DISABLE 0x004 /* disable 64-bit mode */
185 #define BIM_CFG_32BIT 0x010 /* (ro) 1 = 32-bit slot, 0 = 64-bit */
216 reset when hot-swap is being
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
45 * -------------------------------------------
47 * --------------------------------------------+
[all …]

12