Lines Matching +full:assert +full:- +full:falling +full:- +full:edge
4 * Copyright (C) 2017-2019 IBM Corp.
6 * SPDX-License-Identifier: GPL-2.0-or-later
10 #include "qemu/host-utils.h"
36 * -----------------------------
37 * | 0 | 0 | 0 | falling-edge
38 * | 0 | 0 | 1 | rising-edge
39 * | 0 | 1 | 0 | level-low
40 * | 0 | 1 | 1 | level-high
41 * | 1 | X | X | dual-edge
168 /* AST2600 only - 1.8V gpios */
171 * AST2400 (memory offsets 0x0-0x198) and a second controller with 1.8V gpios
172 * (memory offsets 0x800-0x9D4).
241 /* GPIOA0 - GPIOAA7 Control Register */
265 uint32_t int_trigger = extract32(regs->int_sens_0, gpio, 1) in aspeed_evaluate_irq()
266 | extract32(regs->int_sens_1, gpio, 1) << 1 in aspeed_evaluate_irq()
267 | extract32(regs->int_sens_2, gpio, 1) << 2; in aspeed_evaluate_irq()
268 uint32_t gpio_curr_high = extract32(regs->data_value, gpio, 1); in aspeed_evaluate_irq()
269 uint32_t gpio_int_enabled = extract32(regs->int_enable, gpio, 1); in aspeed_evaluate_irq()
288 regs->int_status = deposit32(regs->int_status, gpio, 1, 1); in aspeed_evaluate_irq()
295 (pb - ((tb *)(((char *)pa) + offsetof(ta, m))))
305 uint32_t input_mask = regs->input_mask; in aspeed_gpio_update()
306 uint32_t direction = regs->direction; in aspeed_gpio_update()
307 uint32_t old = regs->data_value; in aspeed_gpio_update()
323 /* ...and we're output or not input-masked... */ in aspeed_gpio_update()
330 regs->data_value |= mask; in aspeed_gpio_update()
332 regs->data_value &= ~mask; in aspeed_gpio_update()
337 /* ...trigger the line-state IRQ */ in aspeed_gpio_update()
339 qemu_set_irq(s->gpios[set][gpio], !!(new & mask)); in aspeed_gpio_update()
344 s->pending++; in aspeed_gpio_update()
349 qemu_set_irq(s->irq, !!(s->pending)); in aspeed_gpio_update()
358 reg_val = s->sets[set_idx].data_value; in aspeed_gpio_get_pin_level()
366 uint32_t value = s->sets[set_idx].data_value; in aspeed_gpio_set_pin_level()
375 aspeed_gpio_update(s, &s->sets[set_idx], value, in aspeed_gpio_set_pin_level()
376 ~s->sets[set_idx].direction); in aspeed_gpio_set_pin_level()
381 * |-----------------------------|
388 * data_value, direction, interrupt [enable, sens[0-2]], reset_tol and
409 cmd_source = extract32(regs->cmd_source_0, i, 1) in update_value_control_source()
410 | (extract32(regs->cmd_source_1, i, 1) << 1); in update_value_control_source()
581 uint64_t idx = -1; in aspeed_gpio_read()
589 idx -= GPIO_DEBOUNCE_TIME_1; in aspeed_gpio_read()
590 debounce_value = (uint64_t) s->debounce_regs[idx]; in aspeed_gpio_read()
595 if (idx >= agc->reg_table_count) { in aspeed_gpio_read()
601 reg = &agc->reg_table[idx]; in aspeed_gpio_read()
602 if (reg->set_idx >= agc->nr_gpio_sets) { in aspeed_gpio_read()
608 set = &s->sets[reg->set_idx]; in aspeed_gpio_read()
609 switch (reg->type) { in aspeed_gpio_read()
611 value = set->data_value; in aspeed_gpio_read()
614 value = set->direction; in aspeed_gpio_read()
617 value = set->int_enable; in aspeed_gpio_read()
620 value = set->int_sens_0; in aspeed_gpio_read()
623 value = set->int_sens_1; in aspeed_gpio_read()
626 value = set->int_sens_2; in aspeed_gpio_read()
629 value = set->int_status; in aspeed_gpio_read()
632 value = set->reset_tol; in aspeed_gpio_read()
635 value = set->debounce_1; in aspeed_gpio_read()
638 value = set->debounce_2; in aspeed_gpio_read()
641 value = set->cmd_source_0; in aspeed_gpio_read()
644 value = set->cmd_source_1; in aspeed_gpio_read()
647 value = set->data_read; in aspeed_gpio_read()
650 value = set->input_mask; in aspeed_gpio_read()
678 set = &s->sets[set_idx]; in aspeed_gpio_write_index_mode()
679 props = &agc->props[set_idx]; in aspeed_gpio_write_index_mode()
688 reg_value = set->data_read; in aspeed_gpio_write_index_mode()
691 reg_value &= props->output; in aspeed_gpio_write_index_mode()
692 reg_value = update_value_control_source(set, set->data_value, in aspeed_gpio_write_index_mode()
694 set->data_read = reg_value; in aspeed_gpio_write_index_mode()
695 aspeed_gpio_update(s, set, reg_value, set->direction); in aspeed_gpio_write_index_mode()
698 reg_value = set->direction; in aspeed_gpio_write_index_mode()
704 * ------------------------------------------------------------ in aspeed_gpio_write_index_mode()
713 reg_value = (reg_value | ~props->input) & props->output; in aspeed_gpio_write_index_mode()
714 set->direction = update_value_control_source(set, set->direction, in aspeed_gpio_write_index_mode()
718 reg_value = set->int_enable; in aspeed_gpio_write_index_mode()
721 set->int_enable = update_value_control_source(set, set->int_enable, in aspeed_gpio_write_index_mode()
723 reg_value = set->int_sens_0; in aspeed_gpio_write_index_mode()
726 set->int_sens_0 = update_value_control_source(set, set->int_sens_0, in aspeed_gpio_write_index_mode()
728 reg_value = set->int_sens_1; in aspeed_gpio_write_index_mode()
731 set->int_sens_1 = update_value_control_source(set, set->int_sens_1, in aspeed_gpio_write_index_mode()
733 reg_value = set->int_sens_2; in aspeed_gpio_write_index_mode()
736 set->int_sens_2 = update_value_control_source(set, set->int_sens_2, in aspeed_gpio_write_index_mode()
740 /* pending is either 1 or 0 for a 1-bit field */ in aspeed_gpio_write_index_mode()
741 pending = extract32(set->int_status, pin_idx, 1); in aspeed_gpio_write_index_mode()
743 assert(s->pending >= pending); in aspeed_gpio_write_index_mode()
745 /* No change to s->pending if pending is 0 */ in aspeed_gpio_write_index_mode()
746 s->pending -= pending; in aspeed_gpio_write_index_mode()
750 * was pending or not. The post-condition is that it mustn't be in aspeed_gpio_write_index_mode()
753 set->int_status = deposit32(set->int_status, pin_idx, 1, 0); in aspeed_gpio_write_index_mode()
757 reg_value = set->debounce_1; in aspeed_gpio_write_index_mode()
760 set->debounce_1 = update_value_control_source(set, set->debounce_1, in aspeed_gpio_write_index_mode()
762 reg_value = set->debounce_2; in aspeed_gpio_write_index_mode()
765 set->debounce_2 = update_value_control_source(set, set->debounce_2, in aspeed_gpio_write_index_mode()
769 reg_value = set->reset_tol; in aspeed_gpio_write_index_mode()
772 set->reset_tol = update_value_control_source(set, set->reset_tol, in aspeed_gpio_write_index_mode()
776 reg_value = set->cmd_source_0; in aspeed_gpio_write_index_mode()
779 set->cmd_source_0 = reg_value & ASPEED_CMD_SRC_MASK; in aspeed_gpio_write_index_mode()
780 reg_value = set->cmd_source_1; in aspeed_gpio_write_index_mode()
783 set->cmd_source_1 = reg_value & ASPEED_CMD_SRC_MASK; in aspeed_gpio_write_index_mode()
786 reg_value = set->input_mask; in aspeed_gpio_write_index_mode()
794 set->input_mask = reg_value & props->input; in aspeed_gpio_write_index_mode()
802 aspeed_gpio_update(s, set, set->data_value, UINT32_MAX); in aspeed_gpio_write_index_mode()
812 uint64_t idx = -1; in aspeed_gpio_write()
828 idx -= GPIO_DEBOUNCE_TIME_1; in aspeed_gpio_write()
829 s->debounce_regs[idx] = (uint32_t) data; in aspeed_gpio_write()
833 if (idx >= agc->reg_table_count) { in aspeed_gpio_write()
839 reg = &agc->reg_table[idx]; in aspeed_gpio_write()
840 if (reg->set_idx >= agc->nr_gpio_sets) { in aspeed_gpio_write()
846 set = &s->sets[reg->set_idx]; in aspeed_gpio_write()
847 props = &agc->props[reg->set_idx]; in aspeed_gpio_write()
849 switch (reg->type) { in aspeed_gpio_write()
851 data &= props->output; in aspeed_gpio_write()
852 data = update_value_control_source(set, set->data_value, data); in aspeed_gpio_write()
853 set->data_read = data; in aspeed_gpio_write()
854 aspeed_gpio_update(s, set, data, set->direction); in aspeed_gpio_write()
860 * ------------------------------------------------------------ in aspeed_gpio_write()
869 data = (data | ~props->input) & props->output; in aspeed_gpio_write()
870 set->direction = update_value_control_source(set, set->direction, data); in aspeed_gpio_write()
873 set->int_enable = update_value_control_source(set, set->int_enable, in aspeed_gpio_write()
877 set->int_sens_0 = update_value_control_source(set, set->int_sens_0, in aspeed_gpio_write()
881 set->int_sens_1 = update_value_control_source(set, set->int_sens_1, in aspeed_gpio_write()
885 set->int_sens_2 = update_value_control_source(set, set->int_sens_2, in aspeed_gpio_write()
889 cleared = ctpop32(data & set->int_status); in aspeed_gpio_write()
890 if (s->pending && cleared) { in aspeed_gpio_write()
891 assert(s->pending >= cleared); in aspeed_gpio_write()
892 s->pending -= cleared; in aspeed_gpio_write()
894 set->int_status &= ~data; in aspeed_gpio_write()
897 set->reset_tol = update_value_control_source(set, set->reset_tol, in aspeed_gpio_write()
901 set->debounce_1 = update_value_control_source(set, set->debounce_1, in aspeed_gpio_write()
905 set->debounce_2 = update_value_control_source(set, set->debounce_2, in aspeed_gpio_write()
909 set->cmd_source_0 = data & ASPEED_CMD_SRC_MASK; in aspeed_gpio_write()
912 set->cmd_source_1 = data & ASPEED_CMD_SRC_MASK; in aspeed_gpio_write()
923 set->input_mask = data & props->input; in aspeed_gpio_write()
930 aspeed_gpio_update(s, set, set->data_value, UINT32_MAX); in aspeed_gpio_write()
939 for (set_idx = 0; set_idx < agc->nr_gpio_sets; set_idx++) { in get_set_idx()
940 const GPIOSetProperties *set_props = &agc->props[set_idx]; in get_set_idx()
942 if (!strncmp(group, set_props->group_label[g_idx], strlen(group))) { in get_set_idx()
948 return -1; in get_set_idx()
960 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { in aspeed_gpio_get_pin()
962 if (sscanf(name, "gpio%3[18A-E]%1d", group, &pin) != 2) { in aspeed_gpio_get_pin()
968 if (set_idx == -1) { in aspeed_gpio_get_pin()
989 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { in aspeed_gpio_set_pin()
991 if (sscanf(name, "gpio%3[18A-E]%1d", group, &pin) != 2) { in aspeed_gpio_set_pin()
997 if (set_idx == -1) { in aspeed_gpio_set_pin()
1017 if (set_idx >= agc->nr_gpio_sets) { in aspeed_gpio_2700_read_control_reg()
1023 set = &s->sets[set_idx]; in aspeed_gpio_2700_read_control_reg()
1025 extract32(set->data_read, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1027 extract32(set->direction, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1029 extract32(set->int_enable, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1031 extract32(set->int_sens_0, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1033 extract32(set->int_sens_1, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1035 extract32(set->int_sens_2, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1037 extract32(set->reset_tol, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1039 extract32(set->debounce_1, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1041 extract32(set->debounce_2, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1043 extract32(set->input_mask, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1045 extract32(set->int_status, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1047 extract32(set->data_value, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1065 if (set_idx >= agc->nr_gpio_sets) { in aspeed_gpio_2700_write_control_reg()
1071 set = &s->sets[set_idx]; in aspeed_gpio_2700_write_control_reg()
1072 props = &agc->props[set_idx]; in aspeed_gpio_2700_write_control_reg()
1075 group_value = set->direction; in aspeed_gpio_2700_write_control_reg()
1081 * ------------------------------------------------------------ in aspeed_gpio_2700_write_control_reg()
1090 group_value = (group_value | ~props->input) & props->output; in aspeed_gpio_2700_write_control_reg()
1091 set->direction = update_value_control_source(set, set->direction, in aspeed_gpio_2700_write_control_reg()
1095 group_value = set->data_read; in aspeed_gpio_2700_write_control_reg()
1098 group_value &= props->output; in aspeed_gpio_2700_write_control_reg()
1099 group_value = update_value_control_source(set, set->data_read, in aspeed_gpio_2700_write_control_reg()
1101 set->data_read = group_value; in aspeed_gpio_2700_write_control_reg()
1104 group_value = set->int_enable; in aspeed_gpio_2700_write_control_reg()
1107 set->int_enable = update_value_control_source(set, set->int_enable, in aspeed_gpio_2700_write_control_reg()
1111 group_value = set->int_sens_0; in aspeed_gpio_2700_write_control_reg()
1114 set->int_sens_0 = update_value_control_source(set, set->int_sens_0, in aspeed_gpio_2700_write_control_reg()
1118 group_value = set->int_sens_1; in aspeed_gpio_2700_write_control_reg()
1121 set->int_sens_1 = update_value_control_source(set, set->int_sens_1, in aspeed_gpio_2700_write_control_reg()
1125 group_value = set->int_sens_2; in aspeed_gpio_2700_write_control_reg()
1128 set->int_sens_2 = update_value_control_source(set, set->int_sens_2, in aspeed_gpio_2700_write_control_reg()
1132 group_value = set->reset_tol; in aspeed_gpio_2700_write_control_reg()
1135 set->reset_tol = update_value_control_source(set, set->reset_tol, in aspeed_gpio_2700_write_control_reg()
1139 group_value = set->debounce_1; in aspeed_gpio_2700_write_control_reg()
1142 set->debounce_1 = update_value_control_source(set, set->debounce_1, in aspeed_gpio_2700_write_control_reg()
1146 group_value = set->debounce_2; in aspeed_gpio_2700_write_control_reg()
1149 set->debounce_2 = update_value_control_source(set, set->debounce_2, in aspeed_gpio_2700_write_control_reg()
1153 group_value = set->input_mask; in aspeed_gpio_2700_write_control_reg()
1161 set->input_mask = group_value & props->input; in aspeed_gpio_2700_write_control_reg()
1169 /* pending is either 1 or 0 for a 1-bit field */ in aspeed_gpio_2700_write_control_reg()
1170 pending = extract32(set->int_status, pin_idx, 1); in aspeed_gpio_2700_write_control_reg()
1172 assert(s->pending >= pending); in aspeed_gpio_2700_write_control_reg()
1174 /* No change to s->pending if pending is 0 */ in aspeed_gpio_2700_write_control_reg()
1175 s->pending -= pending; in aspeed_gpio_2700_write_control_reg()
1179 * was pending or not. The post-condition is that it mustn't be in aspeed_gpio_2700_write_control_reg()
1182 set->int_status = deposit32(set->int_status, pin_idx, 1, 0); in aspeed_gpio_2700_write_control_reg()
1185 aspeed_gpio_update(s, set, set->data_value, UINT32_MAX); in aspeed_gpio_2700_write_control_reg()
1202 if (reg >= agc->reg_table_count) { in aspeed_gpio_2700_read()
1211 idx = reg - R_GPIO_2700_DEBOUNCE_TIME_1; in aspeed_gpio_2700_read()
1220 value = (uint64_t) s->debounce_regs[idx]; in aspeed_gpio_2700_read()
1223 idx = reg - R_GPIO_2700_INT_STATUS_1; in aspeed_gpio_2700_read()
1225 if (idx >= agc->nr_gpio_sets) { in aspeed_gpio_2700_read()
1232 set = &s->sets[idx]; in aspeed_gpio_2700_read()
1233 value = (uint64_t) set->int_status; in aspeed_gpio_2700_read()
1236 pin = reg - R_GPIO_A0_CONTROL; in aspeed_gpio_2700_read()
1238 if (pin >= agc->nr_gpio_pins) { in aspeed_gpio_2700_read()
1269 if (reg >= agc->reg_table_count) { in aspeed_gpio_2700_write()
1278 idx = reg - R_GPIO_2700_DEBOUNCE_TIME_1; in aspeed_gpio_2700_write()
1287 s->debounce_regs[idx] = (uint32_t) data; in aspeed_gpio_2700_write()
1290 pin = reg - R_GPIO_A0_CONTROL; in aspeed_gpio_2700_write()
1292 if (pin >= agc->nr_gpio_pins) { in aspeed_gpio_2700_write()
1392 memset(s->sets, 0, sizeof(s->sets)); in aspeed_gpio_reset()
1402 sysbus_init_irq(sbd, &s->irq); in aspeed_gpio_realize()
1406 const GPIOSetProperties *props = &agc->props[i]; in aspeed_gpio_realize()
1407 uint32_t skip = ~(props->input | props->output); in aspeed_gpio_realize()
1412 sysbus_init_irq(sbd, &s->gpios[i][j]); in aspeed_gpio_realize()
1416 memory_region_init_io(&s->iomem, OBJECT(s), agc->reg_ops, s, in aspeed_gpio_realize()
1417 TYPE_ASPEED_GPIO, agc->mem_size); in aspeed_gpio_realize()
1419 sysbus_init_mmio(sbd, &s->iomem); in aspeed_gpio_realize()
1428 const GPIOSetProperties *props = &agc->props[i]; in aspeed_gpio_init()
1429 uint32_t skip = ~(props->input | props->output); in aspeed_gpio_init()
1436 const char *group = &props->group_label[group_idx][0]; in aspeed_gpio_init()
1485 dc->realize = aspeed_gpio_realize; in aspeed_gpio_class_init()
1487 dc->desc = "Aspeed GPIO Controller"; in aspeed_gpio_class_init()
1488 dc->vmsd = &vmstate_aspeed_gpio; in aspeed_gpio_class_init()
1495 agc->props = ast2400_set_props; in aspeed_gpio_ast2400_class_init()
1496 agc->nr_gpio_pins = 216; in aspeed_gpio_ast2400_class_init()
1497 agc->nr_gpio_sets = 7; in aspeed_gpio_ast2400_class_init()
1498 agc->reg_table = aspeed_3_3v_gpios; in aspeed_gpio_ast2400_class_init()
1499 agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; in aspeed_gpio_ast2400_class_init()
1500 agc->mem_size = 0x1000; in aspeed_gpio_ast2400_class_init()
1501 agc->reg_ops = &aspeed_gpio_ops; in aspeed_gpio_ast2400_class_init()
1508 agc->props = ast2500_set_props; in aspeed_gpio_2500_class_init()
1509 agc->nr_gpio_pins = 228; in aspeed_gpio_2500_class_init()
1510 agc->nr_gpio_sets = 8; in aspeed_gpio_2500_class_init()
1511 agc->reg_table = aspeed_3_3v_gpios; in aspeed_gpio_2500_class_init()
1512 agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; in aspeed_gpio_2500_class_init()
1513 agc->mem_size = 0x1000; in aspeed_gpio_2500_class_init()
1514 agc->reg_ops = &aspeed_gpio_ops; in aspeed_gpio_2500_class_init()
1521 agc->props = ast2600_3_3v_set_props; in aspeed_gpio_ast2600_3_3v_class_init()
1522 agc->nr_gpio_pins = 208; in aspeed_gpio_ast2600_3_3v_class_init()
1523 agc->nr_gpio_sets = 7; in aspeed_gpio_ast2600_3_3v_class_init()
1524 agc->reg_table = aspeed_3_3v_gpios; in aspeed_gpio_ast2600_3_3v_class_init()
1525 agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; in aspeed_gpio_ast2600_3_3v_class_init()
1526 agc->mem_size = 0x800; in aspeed_gpio_ast2600_3_3v_class_init()
1527 agc->reg_ops = &aspeed_gpio_ops; in aspeed_gpio_ast2600_3_3v_class_init()
1534 agc->props = ast2600_1_8v_set_props; in aspeed_gpio_ast2600_1_8v_class_init()
1535 agc->nr_gpio_pins = 36; in aspeed_gpio_ast2600_1_8v_class_init()
1536 agc->nr_gpio_sets = 2; in aspeed_gpio_ast2600_1_8v_class_init()
1537 agc->reg_table = aspeed_1_8v_gpios; in aspeed_gpio_ast2600_1_8v_class_init()
1538 agc->reg_table_count = GPIO_1_8V_REG_ARRAY_SIZE; in aspeed_gpio_ast2600_1_8v_class_init()
1539 agc->mem_size = 0x800; in aspeed_gpio_ast2600_1_8v_class_init()
1540 agc->reg_ops = &aspeed_gpio_ops; in aspeed_gpio_ast2600_1_8v_class_init()
1547 agc->props = ast1030_set_props; in aspeed_gpio_1030_class_init()
1548 agc->nr_gpio_pins = 151; in aspeed_gpio_1030_class_init()
1549 agc->nr_gpio_sets = 6; in aspeed_gpio_1030_class_init()
1550 agc->reg_table = aspeed_3_3v_gpios; in aspeed_gpio_1030_class_init()
1551 agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; in aspeed_gpio_1030_class_init()
1552 agc->mem_size = 0x1000; in aspeed_gpio_1030_class_init()
1553 agc->reg_ops = &aspeed_gpio_ops; in aspeed_gpio_1030_class_init()
1560 agc->props = ast2700_set_props; in aspeed_gpio_2700_class_init()
1561 agc->nr_gpio_pins = 216; in aspeed_gpio_2700_class_init()
1562 agc->nr_gpio_sets = 7; in aspeed_gpio_2700_class_init()
1563 agc->reg_table_count = GPIO_2700_REG_ARRAY_SIZE; in aspeed_gpio_2700_class_init()
1564 agc->mem_size = 0x1000; in aspeed_gpio_2700_class_init()
1565 agc->reg_ops = &aspeed_gpio_2700_ops; in aspeed_gpio_2700_class_init()
1578 .name = TYPE_ASPEED_GPIO "-ast2400",
1585 .name = TYPE_ASPEED_GPIO "-ast2500",
1592 .name = TYPE_ASPEED_GPIO "-ast2600",
1599 .name = TYPE_ASPEED_GPIO "-ast2600-1_8v",
1606 .name = TYPE_ASPEED_GPIO "-ast1030",
1613 .name = TYPE_ASPEED_GPIO "-ast2700",