1 // SPDX-License-Identifier: GPL-2.0
26 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
29 #include "../pinctrl-utils.h"
33 #define DRIVER_NAME "pinctrl-starfive"
37  * https://github.com/starfive-tech/JH7100_Docs
48  * The following 32-bit registers come in pairs, but only the offset of the
49  * first register is defined. The first controls (interrupts for) GPIO 0-31 and
50  * the second GPIO 32-63.
54  * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
55  * interrupt is level-triggered.
60  * Edge-Trigger Interrupt Type.  If set to 1 the interrupt gets triggered on
62  * single edge.
68  * rising edge (edge-triggered) or high level (level-triggered). If set to 0 the
69  * interrupt is triggered on a falling edge (edge-triggered) or low level
70  * (level-triggered).
82  * Clear Edge-Triggered Interrupts. Write a 1 to clear the edge-triggered
88  * Edge-Triggered Interrupt Status. A 1 means the configured edge was detected.
93  * Interrupt Status after Masking. A 1 means the configured edge or level was
105  * From the data sheet section 12.2, there are 64 32-bit output data registers
124  * 32-bit registers controlling PAD_GPIO[0] to PAD_GPIO[63] followed by
144  * one of seven pre-defined multiplexed signal groups on PAD_FUNC_SHARE and
151  * sfp->gpio.pin_base = PAD_INVALID_GPIO then
160  *  | 31 - 24 | 23 - 16 | 15 - 8 |     7    |     6    |  5 - 0  |
165  *  |      31       | 30 - 8 |   7 - 0   |
170 	return v & (NR_GPIOS - 1);  in starfive_pinmux_to_gpio()
175 	return ((v & BIT(7)) << (31 - 7)) | ((v >> 24) & GENMASK(7, 0));  in starfive_pinmux_to_dout()
180 	return ((v & BIT(6)) << (31 - 6)) | ((v >> 16) & GENMASK(7, 0));  in starfive_pinmux_to_doen()
203 	return (clamp(i, 14U, 63U) - 14) / 7;  in starfive_drive_strength_from_max_mA()
219 	return pin - sfp->gpios.pin_base;  in starfive_pin_to_gpio()
225 	return sfp->gpios.pin_base + gpio;  in starfive_gpio_to_pin()
464 	reg = sfp->base + GPON_DOUT_CFG + 8 * gpio;  in starfive_pin_dbg_show()
482 	struct device *dev = sfp->gc.parent;  in starfive_dt_node_to_map()
503 			return -EINVAL;  in starfive_dt_node_to_map()
509 			return -EINVAL;  in starfive_dt_node_to_map()
521 		return -ENOMEM;  in starfive_dt_node_to_map()
525 		return -ENOMEM;  in starfive_dt_node_to_map()
529 	mutex_lock(&sfp->mutex);  in starfive_dt_node_to_map()
536 			ret = -ENOMEM;  in starfive_dt_node_to_map()
545 				ret = -ENOMEM;  in starfive_dt_node_to_map()
551 				ret = -ENOMEM;  in starfive_dt_node_to_map()
566 			map[nmaps].data.mux.function = np->name;  in starfive_dt_node_to_map()
572 				ret = -ENOMEM;  in starfive_dt_node_to_map()
587 			ret = -EINVAL;  in starfive_dt_node_to_map()
615 	ret = pinmux_generic_add_function(pctldev, np->name, pgnames, ngroups, NULL);  in starfive_dt_node_to_map()
617 		dev_err(dev, "error adding function %s: %d\n", np->name, ret);  in starfive_dt_node_to_map()
623 	mutex_unlock(&sfp->mutex);  in starfive_dt_node_to_map()
630 	mutex_unlock(&sfp->mutex);  in starfive_dt_node_to_map()
647 	struct device *dev = sfp->gc.parent;  in starfive_set_mux()
654 		return -EINVAL;  in starfive_set_mux()
656 	pinmux = group->data;  in starfive_set_mux()
657 	for (i = 0; i < group->num_pins; i++) {  in starfive_set_mux()
671 		reg_dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;  in starfive_set_mux()
672 		reg_doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;  in starfive_set_mux()
674 			reg_din = sfp->base + GPI_CFG_OFFSET + 4 * din;  in starfive_set_mux()
678 		raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_set_mux()
683 		raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_set_mux()
700 	void __iomem *reg = sfp->padctl + 4 * (pin / 2);  in starfive_padctl_get()
710 	void __iomem *reg = sfp->padctl + 4 * (pin / 2);  in starfive_padctl_rmw()
716 	dev_dbg(sfp->gc.parent, "padctl_rmw(%u, 0x%03x, 0x%03x)\n", pin, _mask, _value);  in starfive_padctl_rmw()
718 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_padctl_rmw()
721 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_padctl_rmw()
727 	{ "starfive,strong-pull-up", PIN_CONFIG_STARFIVE_STRONG_PULL_UP, 1 },
732 	PCONFDUMP(PIN_CONFIG_STARFIVE_STRONG_PULL_UP, "input bias strong pull-up", NULL, false),
784 		return -ENOTSUPP;  in starfive_pinconf_get()
788 	return enabled ? 0 : -EINVAL;  in starfive_pinconf_get()
798 		return -EINVAL;  in starfive_pinconf_group_get()
800 	return starfive_pinconf_get(pctldev, group->pins[0], config);  in starfive_pinconf_group_get()
815 		return -EINVAL;  in starfive_pinconf_group_set()
830 				return -ENOTSUPP;  in starfive_pinconf_group_set()
836 				return -ENOTSUPP;  in starfive_pinconf_group_set()
875 			return -ENOTSUPP;  in starfive_pinconf_group_set()
879 	for (i = 0; i < group->num_pins; i++)  in starfive_pinconf_group_set()
880 		starfive_padctl_rmw(sfp, group->pins[i], mask, value);  in starfive_pinconf_group_set()
921 	return pinctrl_gpio_request(gc->base + gpio);  in starfive_gpio_request()
926 	pinctrl_gpio_free(gc->base + gpio);  in starfive_gpio_free()
932 	void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;  in starfive_gpio_get_direction()
944 	void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;  in starfive_gpio_direction_input()
952 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_gpio_direction_input()
954 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_gpio_direction_input()
962 	void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;  in starfive_gpio_direction_output()
963 	void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;  in starfive_gpio_direction_output()
966 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_gpio_direction_output()
969 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_gpio_direction_output()
982 	void __iomem *din = sfp->base + GPIODIN + 4 * (gpio / 32);  in starfive_gpio_get()
991 	void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;  in starfive_gpio_set()
994 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_gpio_set()
996 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_gpio_set()
1014 			return -ENOTSUPP;  in starfive_gpio_set_config()
1020 			return -ENOTSUPP;  in starfive_gpio_set_config()
1035 		return -ENOTSUPP;  in starfive_gpio_set_config()
1046 	sfp->gpios.name = sfp->gc.label;  in starfive_gpio_add_pin_ranges()
1047 	sfp->gpios.base = sfp->gc.base;  in starfive_gpio_add_pin_ranges()
1049 	 * sfp->gpios.pin_base depends on the chosen signal group  in starfive_gpio_add_pin_ranges()
1052 	sfp->gpios.npins = NR_GPIOS;  in starfive_gpio_add_pin_ranges()
1053 	sfp->gpios.gc = &sfp->gc;  in starfive_gpio_add_pin_ranges()
1054 	pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);  in starfive_gpio_add_pin_ranges()
1062 	void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);  in starfive_irq_ack()
1066 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_irq_ack()
1068 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_irq_ack()
1075 	void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);  in starfive_irq_mask()
1080 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_irq_mask()
1083 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_irq_mask()
1085 	gpiochip_disable_irq(&sfp->gc, gpio);  in starfive_irq_mask()
1092 	void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);  in starfive_irq_mask_ack()
1093 	void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);  in starfive_irq_mask_ack()
1098 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_irq_mask_ack()
1102 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_irq_mask_ack()
1109 	void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);  in starfive_irq_unmask()
1114 	gpiochip_enable_irq(&sfp->gc, gpio);  in starfive_irq_unmask()
1116 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_irq_unmask()
1119 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_irq_unmask()
1126 	void __iomem *base = sfp->base + 4 * (gpio / 32);  in starfive_irq_set_type()
1133 		irq_type  = mask; /* 1: edge triggered */  in starfive_irq_set_type()
1134 		edge_both = 0;    /* 0: single edge */  in starfive_irq_set_type()
1135 		polarity  = mask; /* 1: rising edge */  in starfive_irq_set_type()
1138 		irq_type  = mask; /* 1: edge triggered */  in starfive_irq_set_type()
1139 		edge_both = 0;    /* 0: single edge */  in starfive_irq_set_type()
1140 		polarity  = 0;    /* 0: falling edge */  in starfive_irq_set_type()
1143 		irq_type  = mask; /* 1: edge triggered */  in starfive_irq_set_type()
1158 		return -EINVAL;  in starfive_irq_set_type()
1166 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_irq_set_type()
1173 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_irq_set_type()
1197 	mis = readl_relaxed(sfp->base + GPIOMIS + 0);  in starfive_gpio_irq_handler()
1199 		generic_handle_domain_irq(sfp->gc.irq.domain, pin);  in starfive_gpio_irq_handler()
1201 	mis = readl_relaxed(sfp->base + GPIOMIS + 4);  in starfive_gpio_irq_handler()
1203 		generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32);  in starfive_gpio_irq_handler()
1213 	writel(0, sfp->base + GPIOIE + 0);  in starfive_gpio_init_hw()
1214 	writel(0, sfp->base + GPIOIE + 4);  in starfive_gpio_init_hw()
1215 	/* clear edge interrupt flags */  in starfive_gpio_init_hw()
1216 	writel(~0U, sfp->base + GPIOIC + 0);  in starfive_gpio_init_hw()
1217 	writel(~0U, sfp->base + GPIOIC + 4);  in starfive_gpio_init_hw()
1219 	writel(1, sfp->base + GPIOEN);  in starfive_gpio_init_hw()
1230 	struct device *dev = &pdev->dev;  in starfive_probe()
1239 		return -ENOMEM;  in starfive_probe()
1241 	sfp->base = devm_platform_ioremap_resource_byname(pdev, "gpio");  in starfive_probe()
1242 	if (IS_ERR(sfp->base))  in starfive_probe()
1243 		return PTR_ERR(sfp->base);  in starfive_probe()
1245 	sfp->padctl = devm_platform_ioremap_resource_byname(pdev, "padctl");  in starfive_probe()
1246 	if (IS_ERR(sfp->padctl))  in starfive_probe()
1247 		return PTR_ERR(sfp->padctl);  in starfive_probe()
1266 	 * We don't want to assert reset and risk undoing pin muxing for the  in starfive_probe()
1275 	sfp->gc.parent = dev;  in starfive_probe()
1276 	raw_spin_lock_init(&sfp->lock);  in starfive_probe()
1277 	mutex_init(&sfp->mutex);  in starfive_probe()
1279 	ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl);  in starfive_probe()
1283 	if (!of_property_read_u32(dev->of_node, "starfive,signal-group", &value)) {  in starfive_probe()
1285 			return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);  in starfive_probe()
1286 		writel(value, sfp->padctl + IO_PADSHARE_SEL);  in starfive_probe()
1289 	value = readl(sfp->padctl + IO_PADSHARE_SEL);  in starfive_probe()
1292 		sfp->gpios.pin_base = PAD_INVALID_GPIO;  in starfive_probe()
1295 		sfp->gpios.pin_base = PAD_GPIO(0);  in starfive_probe()
1298 		sfp->gpios.pin_base = PAD_FUNC_SHARE(72);  in starfive_probe()
1301 		sfp->gpios.pin_base = PAD_FUNC_SHARE(70);  in starfive_probe()
1304 		sfp->gpios.pin_base = PAD_FUNC_SHARE(0);  in starfive_probe()
1307 		return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);  in starfive_probe()
1310 	sfp->gc.label = dev_name(dev);  in starfive_probe()
1311 	sfp->gc.owner = THIS_MODULE;  in starfive_probe()
1312 	sfp->gc.request = starfive_gpio_request;  in starfive_probe()
1313 	sfp->gc.free = starfive_gpio_free;  in starfive_probe()
1314 	sfp->gc.get_direction = starfive_gpio_get_direction;  in starfive_probe()
1315 	sfp->gc.direction_input = starfive_gpio_direction_input;  in starfive_probe()
1316 	sfp->gc.direction_output = starfive_gpio_direction_output;  in starfive_probe()
1317 	sfp->gc.get = starfive_gpio_get;  in starfive_probe()
1318 	sfp->gc.set = starfive_gpio_set;  in starfive_probe()
1319 	sfp->gc.set_config = starfive_gpio_set_config;  in starfive_probe()
1320 	sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges;  in starfive_probe()
1321 	sfp->gc.base = -1;  in starfive_probe()
1322 	sfp->gc.ngpio = NR_GPIOS;  in starfive_probe()
1324 	gpio_irq_chip_set_chip(&sfp->gc.irq, &starfive_irq_chip);  in starfive_probe()
1325 	sfp->gc.irq.parent_handler = starfive_gpio_irq_handler;  in starfive_probe()
1326 	sfp->gc.irq.num_parents = 1;  in starfive_probe()
1327 	sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,  in starfive_probe()
1328 					   sizeof(*sfp->gc.irq.parents), GFP_KERNEL);  in starfive_probe()
1329 	if (!sfp->gc.irq.parents)  in starfive_probe()
1330 		return -ENOMEM;  in starfive_probe()
1331 	sfp->gc.irq.default_type = IRQ_TYPE_NONE;  in starfive_probe()
1332 	sfp->gc.irq.handler = handle_bad_irq;  in starfive_probe()
1333 	sfp->gc.irq.init_hw = starfive_gpio_init_hw;  in starfive_probe()
1338 	sfp->gc.irq.parents[0] = ret;  in starfive_probe()
1340 	ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);  in starfive_probe()
1344 	irq_domain_set_pm_device(sfp->gc.irq.domain, dev);  in starfive_probe()
1347 	return pinctrl_enable(sfp->pctl);  in starfive_probe()
1351 	{ .compatible = "starfive,jh7100-pinctrl" },