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/openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_llh_internal.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
46 * base address: 0x000003a0
50 /* register address for bitfield rx dma good octet counter lsw [1f:0] */
52 /* register address for bitfield rx dma good packet counter lsw [1f:0] */
54 /* register address for bitfield tx dma good octet counter lsw [1f:0] */
56 /* register address for bitfield tx dma good packet counter lsw [1f:0] */
59 /* register address for bitfield rx dma good octet counter msw [3f:20] */
61 /* register address for bitfield rx dma good packet counter msw [3f:20] */
[all …]
/openbmc/u-boot/doc/device-tree-bindings/mtd/
H A Dmtd-physmap.txt1 CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
6 - compatible : should contain the specific model of mtd chip(s)
7 used, if known, followed by either "cfi-flash", "jedec-flash",
8 "mtd-ram" or "mtd-rom".
9 - reg : Address range(s) of the mtd chip(s)
11 non-identical chips can be described in one node.
12 - bank-width : Width (in bytes) of the bank. Equal to the
13 device width times the number of interleaved chips.
14 - device-width : (optional) Width of a single mtd chip. If
15 omitted, assumed to be equal to 'bank-width'.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dnvidia,tegra20-gmi.txt10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
19 addresses in the GMI address space. Should be 2.
[all …]
/openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
H A Dhw_atl2_llh_internal.h1 /* SPDX-License-Identifier: GPL-2.0-only */
32 /* register address for bitfield rpf_new_rpf_en */
40 /* width of bitfield rpf_new_rpf_en */
51 /* register address for bitfield l2_uc_req_tag0{f}[2:0] */
59 /* width of bitfield l2_uc_req_tag0{f}[2:0] */
69 /* register address for bitfield rpf_l2_bc_req_tag */
77 /* width of bitfield rpf_l2_bc_req_tag */
87 /* register address for bitfield rpf_rss_red1_data[4:0] */
94 /* width of bitfield rpf_rss_red1_data[4:0] */
105 /* register address for bitfield vlan_req_tag0{f}[3:0] */
[all …]
/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-stm32-qspi.txt2 --------------------------------------------
5 - compatible : should be "st,stm32-qspi".
6 - reg : 1. Physical base address and size of SPI registers map.
7 2. Physical base address & size of mapped NOR Flash.
8 - spi-max-frequency : Max supported spi frequency.
9 - status : enable in requried dts.
12 --------------------------
13 - spi-max-frequency : Max supported spi frequency.
14 - spi-tx-bus-width : Bus width (number of lines) for writing (1-4)
15 - spi-rx-bus-width : Bus width (number of lines) for reading (1-4)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dmtd-physmap.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
10 - Rob Herring <robh@kernel.org>
17 - $ref: mtd.yaml#
18 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
23 - items:
24 - enum:
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/openbmc/linux/drivers/acpi/acpica/
H A Dhwvalid.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: hwvalid - I/O request validation
6 * Copyright (C) 2000 - 2023, Intel Corp.
18 acpi_hw_validate_io_request(acpi_io_address address, u32 bit_width);
22 * conditionally illegal. This table must remain ordered by port address.
37 * RTC: Real-time clock
77 * PARAMETERS: Address Address of I/O port/register
82 * DESCRIPTION: Validates an I/O request (address/length). Certain ports are
90 acpi_hw_validate_io_request(acpi_io_address address, u32 bit_width) in acpi_hw_validate_io_request() argument
109 last_address = address + byte_width - 1; in acpi_hw_validate_io_request()
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H A Dexregion.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: exregion - ACPI default op_region (address space) handlers
6 * Copyright (C) 2000 - 2023, Intel Corp.
21 * PARAMETERS: function - Read or Write operation
22 * address - Where in the space to read or write
23 * bit_width - Field width in bits (8, 16, or 32)
24 * value - Pointer to in or out value
25 * handler_context - Pointer to Handler's context
26 * region_context - Pointer to context specific to the
31 * DESCRIPTION: Handler for the System Memory address space (Op Region)
[all …]
/openbmc/linux/include/media/
H A Dv4l2-cci.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 * struct cci_reg_sequence - An individual write from a sequence of CCI writes
20 * @reg: Register address, use CCI_REG#() macros to encode reg width
31 * Macros to define register address with the register width encoded
54 * cci_read() - Read a value from a single CCI register
57 * @reg: Register address to read, use CCI_REG#() macros to encode reg width
67 * cci_write() - Write a value to a single CCI register
70 * @reg: Register address to write, use CCI_REG#() macros to encode reg width
80 * cci_update_bits() - Perform a read/modify/write cycle on
84 * @reg: Register address to update, use CCI_REG#() macros to encode reg width
[all …]
/openbmc/linux/arch/arm64/boot/dts/realtek/
H A Drtd129x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2016-2019 Andreas Färber
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/realtek,rtd1295.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
20 reserved-memory {
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
H A Drtd139x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/realtek,rtd1295.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
34 no-map;
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H A Drtd16xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
32 no-map;
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
33 #address-cells = <1>;
[all …]
H A Dfsl-ls208xa-qds.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 phy-handle = <&mdio0_phy12>;
15 phy-connection-type = "sgmii";
19 phy-handle = <&mdio0_phy13>;
20 phy-connection-type = "sgmii";
24 phy-handle = <&mdio0_phy14>;
25 phy-connection-type = "sgmii";
29 phy-handle = <&mdio0_phy15>;
30 phy-connection-type = "sgmii";
34 mmc-hs200-1_8v;
[all …]
H A Dfsl-ls2081a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls2088a.dtsi"
17 compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
25 stdout-path = "serial1:115200n8";
33 compatible = "jedec,spi-nor";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 spi-max-frequency = <3000000>;
51 #address-cells = <1>;
[all …]
/openbmc/linux/drivers/video/
H A Dsticore.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/video/console/sticore.c -
7 * Copyright (C) 2001-2023 Helge Deller <deller@gmx.de>
8 * Copyright (C) 2001-2002 Thomas Bogendoerfer <tsbogend@alpha.franken.de>
11 * - call STI in virtual mode rather than in real mode
12 * - screen blanking with state_mgmt() in text mode STI ?
13 * - try to make it work on m68k hp workstations ;)
29 #include <asm/parisc-device.h>
48 if (IS_ENABLED(CONFIG_64BIT) && sti->do_call64) { in store_sti_val()
49 /* used for 64-bit STI ROM */ in store_sti_val()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr-channel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Julius Werner <jwerner@chromium.org>
21 - jedec,lpddr2-channel
22 - jedec,lpddr3-channel
23 - jedec,lpddr4-channel
24 - jedec,lpddr5-channel
26 io-width:
[all …]
/openbmc/openbmc-tools/bi2cp/
H A Dbi2cp3 # SPDX-License-Identifier: Apache-2.0
16 def __new__(cls, value, width): argument
19 obj.width = width
22 MONITOR_CONFIG = (0xD5, -1)
26 DEVICE_ID = (0xFD, -1)
30 def __new__(cls, value, width): argument
33 obj.width = width
41 PAGE_PLUS_WRITE = (0x05, -1)
42 PAGE_PLUS_READ = (0x06, -1)
83 MFR_MODEL = (0x9A, -1)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/misc/
H A Difm-csi.txt4 - compatible: "ifm,o2d-csi"
5 - reg: specifies sensor chip select number and associated address range
6 - interrupts: external interrupt line number and interrupt sense mode
8 - gpios: three gpio-specifiers for "capture", "reset" and "master enable"
10 - ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
12 - ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
13 - ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
14 - ifm,csi-wait-cycles: sensor bus wait cycles
17 - ifm,csi-byte-swap: if this property is present, the byte swapping on
23 compatible = "ifm,o2d-csi";
[all …]
/openbmc/linux/include/video/
H A Ds1d13xxxfb.h4 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
44 #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/l…
45 #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=N…
47 #define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */
50 #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines …
52 #define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */
55 #define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */
56 #define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */
57 #define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */
58 #define S1DREG_LCD_MEM_OFF0 0x0046 /* LCD Memory Address Offset Register 0 */
[all …]
/openbmc/linux/arch/arm/boot/dts/realtek/
H A Drtd1195.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 * Copyright (c) 2017-2019 Andreas Färber
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/realtek,rtd1195.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a7";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
8 /dts-v1/;
10 #include "fsl-ls1088a.dtsi"
14 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
22 #address-cells = <2>;
23 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <1>;
33 compatible = "cfi-flash";
35 bank-width = <2>;
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_debug.c43 if (dc->debug.surface_trace) \
48 if (dc->debug.timing_trace) \
53 if (dc->debug.clock_trace) \
63 DC_LOGGER_INIT(dc->ctx->logger); in pre_surface_trace()
71 "plane_state->visible = %d;\n" in pre_surface_trace()
72 "plane_state->flip_immediate = %d;\n" in pre_surface_trace()
73 "plane_state->address.type = %d;\n" in pre_surface_trace()
74 "plane_state->address.grph.addr.quad_part = 0x%llX;\n" in pre_surface_trace()
75 "plane_state->address.grph.meta_addr.quad_part = 0x%llX;\n" in pre_surface_trace()
76 "plane_state->scaling_quality.h_taps = %d;\n" in pre_surface_trace()
[all …]
/openbmc/linux/drivers/staging/sm750fb/
H A Dsm750_accel.c1 // SPDX-License-Identifier: GPL-2.0
22 writel(regValue, accel->dprBase + offset); in write_dpr()
27 return readl(accel->dprBase + offset); in read_dpr()
32 writel(data, accel->dpPortBase); in write_dpPort()
89 u32 x, u32 y, u32 width, u32 height, in sm750_hw_fillrect() argument
94 if (accel->de_wait() != 0) { in sm750_hw_fillrect()
100 return -1; in sm750_hw_fillrect()
121 ((width << DE_DIMENSION_X_SHIFT) & DE_DIMENSION_X_MASK) | in sm750_hw_fillrect()
135 * @sBase: Address of source: offset in frame buffer
139 * @dBase: Address of destination: offset in frame buffer
[all …]

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