1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 /*
24  * dc_debug.c
25  *
26  *  Created on: Nov 3, 2016
27  *      Author: yonsun
28  */
29 
30 #include "dm_services.h"
31 
32 #include "dc.h"
33 
34 #include "core_status.h"
35 #include "core_types.h"
36 
37 #include "resource.h"
38 
39 #define DC_LOGGER_INIT(logger)
40 
41 
42 #define SURFACE_TRACE(...) do {\
43 		if (dc->debug.surface_trace) \
44 			DC_LOG_IF_TRACE(__VA_ARGS__); \
45 } while (0)
46 
47 #define TIMING_TRACE(...) do {\
48 	if (dc->debug.timing_trace) \
49 		DC_LOG_SYNC(__VA_ARGS__); \
50 } while (0)
51 
52 #define CLOCK_TRACE(...) do {\
53 	if (dc->debug.clock_trace) \
54 		DC_LOG_BANDWIDTH_CALCS(__VA_ARGS__); \
55 } while (0)
56 
pre_surface_trace(struct dc * dc,const struct dc_plane_state * const * plane_states,int surface_count)57 void pre_surface_trace(
58 		struct dc *dc,
59 		const struct dc_plane_state *const *plane_states,
60 		int surface_count)
61 {
62 	int i;
63 	DC_LOGGER_INIT(dc->ctx->logger);
64 
65 	for (i = 0; i < surface_count; i++) {
66 		const struct dc_plane_state *plane_state = plane_states[i];
67 
68 		SURFACE_TRACE("Planes %d:\n", i);
69 
70 		SURFACE_TRACE(
71 				"plane_state->visible = %d;\n"
72 				"plane_state->flip_immediate = %d;\n"
73 				"plane_state->address.type = %d;\n"
74 				"plane_state->address.grph.addr.quad_part = 0x%llX;\n"
75 				"plane_state->address.grph.meta_addr.quad_part = 0x%llX;\n"
76 				"plane_state->scaling_quality.h_taps = %d;\n"
77 				"plane_state->scaling_quality.v_taps = %d;\n"
78 				"plane_state->scaling_quality.h_taps_c = %d;\n"
79 				"plane_state->scaling_quality.v_taps_c = %d;\n",
80 				plane_state->visible,
81 				plane_state->flip_immediate,
82 				plane_state->address.type,
83 				plane_state->address.grph.addr.quad_part,
84 				plane_state->address.grph.meta_addr.quad_part,
85 				plane_state->scaling_quality.h_taps,
86 				plane_state->scaling_quality.v_taps,
87 				plane_state->scaling_quality.h_taps_c,
88 				plane_state->scaling_quality.v_taps_c);
89 
90 		SURFACE_TRACE(
91 				"plane_state->src_rect.x = %d;\n"
92 				"plane_state->src_rect.y = %d;\n"
93 				"plane_state->src_rect.width = %d;\n"
94 				"plane_state->src_rect.height = %d;\n"
95 				"plane_state->dst_rect.x = %d;\n"
96 				"plane_state->dst_rect.y = %d;\n"
97 				"plane_state->dst_rect.width = %d;\n"
98 				"plane_state->dst_rect.height = %d;\n"
99 				"plane_state->clip_rect.x = %d;\n"
100 				"plane_state->clip_rect.y = %d;\n"
101 				"plane_state->clip_rect.width = %d;\n"
102 				"plane_state->clip_rect.height = %d;\n",
103 				plane_state->src_rect.x,
104 				plane_state->src_rect.y,
105 				plane_state->src_rect.width,
106 				plane_state->src_rect.height,
107 				plane_state->dst_rect.x,
108 				plane_state->dst_rect.y,
109 				plane_state->dst_rect.width,
110 				plane_state->dst_rect.height,
111 				plane_state->clip_rect.x,
112 				plane_state->clip_rect.y,
113 				plane_state->clip_rect.width,
114 				plane_state->clip_rect.height);
115 
116 		SURFACE_TRACE(
117 				"plane_state->plane_size.surface_size.x = %d;\n"
118 				"plane_state->plane_size.surface_size.y = %d;\n"
119 				"plane_state->plane_size.surface_size.width = %d;\n"
120 				"plane_state->plane_size.surface_size.height = %d;\n"
121 				"plane_state->plane_size.surface_pitch = %d;\n",
122 				plane_state->plane_size.surface_size.x,
123 				plane_state->plane_size.surface_size.y,
124 				plane_state->plane_size.surface_size.width,
125 				plane_state->plane_size.surface_size.height,
126 				plane_state->plane_size.surface_pitch);
127 
128 
129 		SURFACE_TRACE(
130 				"plane_state->tiling_info.gfx8.num_banks = %d;\n"
131 				"plane_state->tiling_info.gfx8.bank_width = %d;\n"
132 				"plane_state->tiling_info.gfx8.bank_width_c = %d;\n"
133 				"plane_state->tiling_info.gfx8.bank_height = %d;\n"
134 				"plane_state->tiling_info.gfx8.bank_height_c = %d;\n"
135 				"plane_state->tiling_info.gfx8.tile_aspect = %d;\n"
136 				"plane_state->tiling_info.gfx8.tile_aspect_c = %d;\n"
137 				"plane_state->tiling_info.gfx8.tile_split = %d;\n"
138 				"plane_state->tiling_info.gfx8.tile_split_c = %d;\n"
139 				"plane_state->tiling_info.gfx8.tile_mode = %d;\n"
140 				"plane_state->tiling_info.gfx8.tile_mode_c = %d;\n",
141 				plane_state->tiling_info.gfx8.num_banks,
142 				plane_state->tiling_info.gfx8.bank_width,
143 				plane_state->tiling_info.gfx8.bank_width_c,
144 				plane_state->tiling_info.gfx8.bank_height,
145 				plane_state->tiling_info.gfx8.bank_height_c,
146 				plane_state->tiling_info.gfx8.tile_aspect,
147 				plane_state->tiling_info.gfx8.tile_aspect_c,
148 				plane_state->tiling_info.gfx8.tile_split,
149 				plane_state->tiling_info.gfx8.tile_split_c,
150 				plane_state->tiling_info.gfx8.tile_mode,
151 				plane_state->tiling_info.gfx8.tile_mode_c);
152 
153 		SURFACE_TRACE(
154 				"plane_state->tiling_info.gfx8.pipe_config = %d;\n"
155 				"plane_state->tiling_info.gfx8.array_mode = %d;\n"
156 				"plane_state->color_space = %d;\n"
157 				"plane_state->dcc.enable = %d;\n"
158 				"plane_state->format = %d;\n"
159 				"plane_state->rotation = %d;\n"
160 				"plane_state->stereo_format = %d;\n",
161 				plane_state->tiling_info.gfx8.pipe_config,
162 				plane_state->tiling_info.gfx8.array_mode,
163 				plane_state->color_space,
164 				plane_state->dcc.enable,
165 				plane_state->format,
166 				plane_state->rotation,
167 				plane_state->stereo_format);
168 
169 		SURFACE_TRACE("plane_state->tiling_info.gfx9.swizzle = %d;\n",
170 				plane_state->tiling_info.gfx9.swizzle);
171 
172 		SURFACE_TRACE("\n");
173 	}
174 	SURFACE_TRACE("\n");
175 }
176 
update_surface_trace(struct dc * dc,const struct dc_surface_update * updates,int surface_count)177 void update_surface_trace(
178 		struct dc *dc,
179 		const struct dc_surface_update *updates,
180 		int surface_count)
181 {
182 	int i;
183 	DC_LOGGER_INIT(dc->ctx->logger);
184 
185 	for (i = 0; i < surface_count; i++) {
186 		const struct dc_surface_update *update = &updates[i];
187 
188 		SURFACE_TRACE("Update %d\n", i);
189 		if (update->flip_addr) {
190 			SURFACE_TRACE("flip_addr->address.type = %d;\n"
191 					"flip_addr->address.grph.addr.quad_part = 0x%llX;\n"
192 					"flip_addr->address.grph.meta_addr.quad_part = 0x%llX;\n"
193 					"flip_addr->flip_immediate = %d;\n",
194 					update->flip_addr->address.type,
195 					update->flip_addr->address.grph.addr.quad_part,
196 					update->flip_addr->address.grph.meta_addr.quad_part,
197 					update->flip_addr->flip_immediate);
198 		}
199 
200 		if (update->plane_info) {
201 			SURFACE_TRACE(
202 					"plane_info->color_space = %d;\n"
203 					"plane_info->format = %d;\n"
204 					"plane_info->plane_size.surface_pitch = %d;\n"
205 					"plane_info->plane_size.surface_size.height = %d;\n"
206 					"plane_info->plane_size.surface_size.width = %d;\n"
207 					"plane_info->plane_size.surface_size.x = %d;\n"
208 					"plane_info->plane_size.surface_size.y = %d;\n"
209 					"plane_info->rotation = %d;\n"
210 					"plane_info->stereo_format = %d;\n",
211 					update->plane_info->color_space,
212 					update->plane_info->format,
213 					update->plane_info->plane_size.surface_pitch,
214 					update->plane_info->plane_size.surface_size.height,
215 					update->plane_info->plane_size.surface_size.width,
216 					update->plane_info->plane_size.surface_size.x,
217 					update->plane_info->plane_size.surface_size.y,
218 					update->plane_info->rotation,
219 					update->plane_info->stereo_format);
220 
221 			SURFACE_TRACE(
222 					"plane_info->tiling_info.gfx8.num_banks = %d;\n"
223 					"plane_info->tiling_info.gfx8.bank_width = %d;\n"
224 					"plane_info->tiling_info.gfx8.bank_width_c = %d;\n"
225 					"plane_info->tiling_info.gfx8.bank_height = %d;\n"
226 					"plane_info->tiling_info.gfx8.bank_height_c = %d;\n"
227 					"plane_info->tiling_info.gfx8.tile_aspect = %d;\n"
228 					"plane_info->tiling_info.gfx8.tile_aspect_c = %d;\n"
229 					"plane_info->tiling_info.gfx8.tile_split = %d;\n"
230 					"plane_info->tiling_info.gfx8.tile_split_c = %d;\n"
231 					"plane_info->tiling_info.gfx8.tile_mode = %d;\n"
232 					"plane_info->tiling_info.gfx8.tile_mode_c = %d;\n",
233 					update->plane_info->tiling_info.gfx8.num_banks,
234 					update->plane_info->tiling_info.gfx8.bank_width,
235 					update->plane_info->tiling_info.gfx8.bank_width_c,
236 					update->plane_info->tiling_info.gfx8.bank_height,
237 					update->plane_info->tiling_info.gfx8.bank_height_c,
238 					update->plane_info->tiling_info.gfx8.tile_aspect,
239 					update->plane_info->tiling_info.gfx8.tile_aspect_c,
240 					update->plane_info->tiling_info.gfx8.tile_split,
241 					update->plane_info->tiling_info.gfx8.tile_split_c,
242 					update->plane_info->tiling_info.gfx8.tile_mode,
243 					update->plane_info->tiling_info.gfx8.tile_mode_c);
244 
245 			SURFACE_TRACE(
246 					"plane_info->tiling_info.gfx8.pipe_config = %d;\n"
247 					"plane_info->tiling_info.gfx8.array_mode = %d;\n"
248 					"plane_info->visible = %d;\n"
249 					"plane_info->per_pixel_alpha = %d;\n",
250 					update->plane_info->tiling_info.gfx8.pipe_config,
251 					update->plane_info->tiling_info.gfx8.array_mode,
252 					update->plane_info->visible,
253 					update->plane_info->per_pixel_alpha);
254 
255 			SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n",
256 					update->plane_info->tiling_info.gfx9.swizzle);
257 		}
258 
259 		if (update->scaling_info) {
260 			SURFACE_TRACE(
261 					"scaling_info->src_rect.x = %d;\n"
262 					"scaling_info->src_rect.y = %d;\n"
263 					"scaling_info->src_rect.width = %d;\n"
264 					"scaling_info->src_rect.height = %d;\n"
265 					"scaling_info->dst_rect.x = %d;\n"
266 					"scaling_info->dst_rect.y = %d;\n"
267 					"scaling_info->dst_rect.width = %d;\n"
268 					"scaling_info->dst_rect.height = %d;\n"
269 					"scaling_info->clip_rect.x = %d;\n"
270 					"scaling_info->clip_rect.y = %d;\n"
271 					"scaling_info->clip_rect.width = %d;\n"
272 					"scaling_info->clip_rect.height = %d;\n"
273 					"scaling_info->scaling_quality.h_taps = %d;\n"
274 					"scaling_info->scaling_quality.v_taps = %d;\n"
275 					"scaling_info->scaling_quality.h_taps_c = %d;\n"
276 					"scaling_info->scaling_quality.v_taps_c = %d;\n",
277 					update->scaling_info->src_rect.x,
278 					update->scaling_info->src_rect.y,
279 					update->scaling_info->src_rect.width,
280 					update->scaling_info->src_rect.height,
281 					update->scaling_info->dst_rect.x,
282 					update->scaling_info->dst_rect.y,
283 					update->scaling_info->dst_rect.width,
284 					update->scaling_info->dst_rect.height,
285 					update->scaling_info->clip_rect.x,
286 					update->scaling_info->clip_rect.y,
287 					update->scaling_info->clip_rect.width,
288 					update->scaling_info->clip_rect.height,
289 					update->scaling_info->scaling_quality.h_taps,
290 					update->scaling_info->scaling_quality.v_taps,
291 					update->scaling_info->scaling_quality.h_taps_c,
292 					update->scaling_info->scaling_quality.v_taps_c);
293 		}
294 		SURFACE_TRACE("\n");
295 	}
296 	SURFACE_TRACE("\n");
297 }
298 
post_surface_trace(struct dc * dc)299 void post_surface_trace(struct dc *dc)
300 {
301 	DC_LOGGER_INIT(dc->ctx->logger);
302 
303 	SURFACE_TRACE("post surface process.\n");
304 
305 }
306 
context_timing_trace(struct dc * dc,struct resource_context * res_ctx)307 void context_timing_trace(
308 		struct dc *dc,
309 		struct resource_context *res_ctx)
310 {
311 	int i;
312 	int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0};
313 	struct crtc_position position;
314 	unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
315 	DC_LOGGER_INIT(dc->ctx->logger);
316 
317 
318 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
319 		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
320 		/* get_position() returns CRTC vertical/horizontal counter
321 		 * hence not applicable for underlay pipe
322 		 */
323 		if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx)
324 			continue;
325 
326 		pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position);
327 		h_pos[i] = position.horizontal_count;
328 		v_pos[i] = position.vertical_count;
329 	}
330 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
331 		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
332 
333 		if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx)
334 			continue;
335 
336 		TIMING_TRACE("OTG_%d   H_tot:%d  V_tot:%d   H_pos:%d  V_pos:%d\n",
337 				pipe_ctx->stream_res.tg->inst,
338 				pipe_ctx->stream->timing.h_total,
339 				pipe_ctx->stream->timing.v_total,
340 				h_pos[i], v_pos[i]);
341 	}
342 }
343 
context_clock_trace(struct dc * dc,struct dc_state * context)344 void context_clock_trace(
345 		struct dc *dc,
346 		struct dc_state *context)
347 {
348 	DC_LOGGER_INIT(dc->ctx->logger);
349 	CLOCK_TRACE("Current: dispclk_khz:%d  max_dppclk_khz:%d  dcfclk_khz:%d\n"
350 			"dcfclk_deep_sleep_khz:%d  fclk_khz:%d  socclk_khz:%d\n",
351 			context->bw_ctx.bw.dcn.clk.dispclk_khz,
352 			context->bw_ctx.bw.dcn.clk.dppclk_khz,
353 			context->bw_ctx.bw.dcn.clk.dcfclk_khz,
354 			context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
355 			context->bw_ctx.bw.dcn.clk.fclk_khz,
356 			context->bw_ctx.bw.dcn.clk.socclk_khz);
357 	CLOCK_TRACE("Calculated: dispclk_khz:%d  max_dppclk_khz:%d  dcfclk_khz:%d\n"
358 			"dcfclk_deep_sleep_khz:%d  fclk_khz:%d  socclk_khz:%d\n",
359 			context->bw_ctx.bw.dcn.clk.dispclk_khz,
360 			context->bw_ctx.bw.dcn.clk.dppclk_khz,
361 			context->bw_ctx.bw.dcn.clk.dcfclk_khz,
362 			context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
363 			context->bw_ctx.bw.dcn.clk.fclk_khz,
364 			context->bw_ctx.bw.dcn.clk.socclk_khz);
365 }
366 
367 /**
368  * dc_status_to_str - convert dc_status to a human readable string
369  * @status: dc_status to be converted
370  *
371  * Return:
372  * A string describing the DC status.
373  */
dc_status_to_str(enum dc_status status)374 char *dc_status_to_str(enum dc_status status)
375 {
376 	switch (status) {
377 	case DC_OK:
378 		return "DC OK";
379 	case DC_NO_CONTROLLER_RESOURCE:
380 		return "No controller resource";
381 	case DC_NO_STREAM_ENC_RESOURCE:
382 		return "No stream encoder";
383 	case DC_NO_CLOCK_SOURCE_RESOURCE:
384 		return "No clock source";
385 	case DC_FAIL_CONTROLLER_VALIDATE:
386 		return "Controller validation failure";
387 	case DC_FAIL_ENC_VALIDATE:
388 		return "Encoder validation failure";
389 	case DC_FAIL_ATTACH_SURFACES:
390 		return "Surfaces attachment failure";
391 	case DC_FAIL_DETACH_SURFACES:
392 		return "Surfaces detachment failure";
393 	case DC_FAIL_SURFACE_VALIDATE:
394 		return "Surface validation failure";
395 	case DC_NO_DP_LINK_BANDWIDTH:
396 		return "No DP link bandwidth";
397 	case DC_EXCEED_DONGLE_CAP:
398 		return "Exceed dongle capability";
399 	case DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED:
400 		return "Unsupported pixel format";
401 	case DC_FAIL_BANDWIDTH_VALIDATE:
402 		return "Bandwidth validation failure (BW and Watermark)";
403 	case DC_FAIL_SCALING:
404 		return "Scaling failure";
405 	case DC_FAIL_DP_LINK_TRAINING:
406 		return "DP link training failure";
407 	case DC_FAIL_DSC_VALIDATE:
408 		return "DSC validation failure";
409 	case DC_NO_DSC_RESOURCE:
410 		return "No DSC resource";
411 	case DC_FAIL_UNSUPPORTED_1:
412 		return "Unsupported";
413 	case DC_FAIL_CLK_EXCEED_MAX:
414 		return "Clk exceed max failure";
415 	case DC_FAIL_CLK_BELOW_MIN:
416 		return "Fail clk below minimum";
417 	case DC_FAIL_CLK_BELOW_CFG_REQUIRED:
418 		return "Fail clk below required CFG (hard_min in PPLIB)";
419 	case DC_NOT_SUPPORTED:
420 		return "The operation is not supported.";
421 	case DC_UNSUPPORTED_VALUE:
422 		return "The value specified is not supported.";
423 	case DC_NO_LINK_ENC_RESOURCE:
424 		return "No link encoder resource";
425 	case DC_FAIL_DP_PAYLOAD_ALLOCATION:
426 		return "Fail dp payload allocation";
427 	case DC_FAIL_DP_LINK_BANDWIDTH:
428 		return "Insufficient DP link bandwidth";
429 	case DC_ERROR_UNEXPECTED:
430 		return "Unexpected error";
431 	}
432 
433 	return "Unexpected status error";
434 }
435