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/openbmc/u-boot/include/
H A Dfsl_dtsec.h21 u32 tctrl; /* Transmit control register */
45 /* transmit and receive counter */
71 /* transmit counters */
72 u32 tbyt; /* Transmit byte counter */
73 u32 tpkt; /* Transmit packet */
74 u32 tmca; /* Transmit multicast packet */
75 u32 tbca; /* Transmit broadcast packet */
76 u32 txpf; /* Transmit pause control frame */
77 u32 tdfr; /* Transmit deferral packet */
78 u32 tedf; /* Transmit excessive deferral pkt */
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H A Dtsec.h215 /* Transmit and Receive Counters */
241 /* Transmit Counters */
242 u32 tbyt; /* Transmit Byte Counter */
243 u32 tpkt; /* Transmit Packet */
244 u32 tmca; /* Transmit Multicast Packet */
245 u32 tbca; /* Transmit Broadcast Packet */
246 u32 txpf; /* Transmit Pause Control Frame */
247 u32 tdfr; /* Transmit Deferral Packet */
248 u32 tedf; /* Transmit Excessive Deferral Packet */
249 u32 tscl; /* Transmit Single Collision Packet */
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/openbmc/linux/drivers/net/ethernet/apple/
H A Dbmac.h27 #define TXFIFOCSR 0x100 /* transmit FIFO control */
29 #define TXTH 0x110 /* transmit threshold */
46 #define TXPNTR 0x1a0 /* transmit pointer */
60 # define TxUnderrun 0x00000200 /* Transmit FIFO underrun */
77 # define TxDMAError 0x04000000 /* Error during transmit DMA */
78 # define TxDMALateError 0x08000000 /* Late error during transmit DMA */
79 # define TxParityError 0x10000000 /* Parity error during transmit DMA */
80 # define TxTagError 0x20000000 /* Tag error during transmit DMA */
93 /* transmit control */
94 #define TXRST 0x420 /* transmit reset */
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/openbmc/linux/sound/soc/fsl/
H A Dfsl_sai.h23 #define FSL_SAI_TCSR(ofs) (0x00 + ofs) /* SAI Transmit Control */
24 #define FSL_SAI_TCR1(ofs) (0x04 + ofs) /* SAI Transmit Configuration 1 */
25 #define FSL_SAI_TCR2(ofs) (0x08 + ofs) /* SAI Transmit Configuration 2 */
26 #define FSL_SAI_TCR3(ofs) (0x0c + ofs) /* SAI Transmit Configuration 3 */
27 #define FSL_SAI_TCR4(ofs) (0x10 + ofs) /* SAI Transmit Configuration 4 */
28 #define FSL_SAI_TCR5(ofs) (0x14 + ofs) /* SAI Transmit Configuration 5 */
29 #define FSL_SAI_TDR0 0x20 /* SAI Transmit Data 0 */
30 #define FSL_SAI_TDR1 0x24 /* SAI Transmit Data 1 */
31 #define FSL_SAI_TDR2 0x28 /* SAI Transmit Data 2 */
32 #define FSL_SAI_TDR3 0x2C /* SAI Transmit Data 3 */
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/openbmc/linux/Documentation/userspace-api/media/cec/
H A Dcec-ioc-receive.rst14 CEC_RECEIVE, CEC_TRANSMIT - Receive or transmit a CEC message
52 2. the transmit result of an earlier non-blocking transmit (the ``sequence``
55 3. the reply to an earlier non-blocking transmit (the ``sequence`` field will
61 ``CEC_CAP_TRANSMIT`` is set. If there is no more room in the transmit
63 The transmit queue has enough room for 18 messages (about 1 second worth
66 idea to fully fill up the transmit queue.
68 If the file descriptor is in non-blocking mode then the transmit will
69 return 0 and the result of the transmit will be available via
70 :ref:`ioctl CEC_RECEIVE <CEC_RECEIVE>` once the transmit has finished.
71 If a non-blocking transmit also specified waiting for a reply, then
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/openbmc/linux/drivers/net/ethernet/amd/
H A Dariadne.h80 #define CSR20 0x1400 /* Current Transmit Buffer Address */
81 #define CSR21 0x1500 /* Current Transmit Buffer Address */
90 #define CSR30 0x1e00 /* - Base Address of Transmit Ring */
91 #define CSR31 0x1f00 /* - Base Address of transmit Ring */
92 #define CSR32 0x2000 /* Next Transmit Descriptor Address */
93 #define CSR33 0x2100 /* Next Transmit Descriptor Address */
94 #define CSR34 0x2200 /* Current Transmit Descriptor Address */
95 #define CSR35 0x2300 /* Current Transmit Descriptor Address */
98 #define CSR38 0x2600 /* Next Next Transmit Descriptor Address */
99 #define CSR39 0x2700 /* Next Next Transmit Descriptor Address */
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/openbmc/linux/drivers/net/ethernet/sun/
H A Dsunhme.h45 #define GREG_STAT_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
58 #define GREG_STAT_EOPERR 0x00400000 /* Transmit descriptor did not have EOP set */
60 #define GREG_STAT_HOSTTOTX 0x01000000 /* Moved from host memory to transmit-FIFO */
62 #define GREG_STAT_TXEACK 0x04000000 /* Error during transmit dma */
63 #define GREG_STAT_TXLERR 0x08000000 /* Late error during transmit dma */
64 #define GREG_STAT_TXPERR 0x10000000 /* Parity error during transmit dma */
65 #define GREG_STAT_TXTERR 0x20000000 /* Tag error during transmit dma */
82 #define GREG_IMASK_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
95 #define GREG_IMASK_EOPERR 0x00400000 /* Transmit descriptor did not have EOP set */
97 #define GREG_IMASK_HOSTTOTX 0x01000000 /* Moved from host memory to transmit-FIFO */
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H A Dsunbmac.h17 #define GLOB_TSIZE 0x14UL /* Transmit partition size */
29 #define GLOB_STAT_TX 0x00000008 /* BigMAC Transmit IRQ */
58 #define CREG_STAT_TXIRQ 0x00200000 /* Transmit Interrupt */
60 #define CREG_STAT_TXLERR 0x00040000 /* Late Transmit Error */
61 #define CREG_STAT_TXPERR 0x00020000 /* Transmit Parity Error */
62 #define CREG_STAT_TXSERR 0x00010000 /* Transmit SBUS error ack */
95 #define BMAC_ALIMIT 0x218UL /* Transmit attempt limit */
96 #define BMAC_STIME 0x21cUL /* Transmit slot time */
97 #define BMAC_PLEN 0x220UL /* Size of transmit preamble */
98 #define BMAC_PPAT 0x224UL /* Pattern for transmit preamble */
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/openbmc/linux/drivers/net/ethernet/actions/
H A Dowl-emac.h35 /* Transmit/receive poll demand registers */
41 /* Receive/transmit descriptor list base address registers */
47 #define OWL_EMAC_MSK_MAC_CSR5_TS GENMASK(22, 20) /* Transmit process state */
50 #define OWL_EMAC_VAL_MAC_CSR5_TS_CDES 0x07 /* Closing transmit descriptor */
60 #define OWL_EMAC_BIT_MAC_CSR5_ETI BIT(10) /* Early transmit interrupt */
64 #define OWL_EMAC_BIT_MAC_CSR5_UNF BIT(5) /* Transmit underflow */
67 #define OWL_EMAC_BIT_MAC_CSR5_TU BIT(2) /* Transmit buffer unavailable */
68 #define OWL_EMAC_BIT_MAC_CSR5_TPS BIT(1) /* Transmit process stopped */
69 #define OWL_EMAC_BIT_MAC_CSR5_TI BIT(0) /* Transmit interrupt */
74 #define OWL_EMAC_BIT_MAC_CSR6_TTM BIT(22) /* Transmit threshold mode */
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/openbmc/qemu/include/hw/net/
H A Dnpcm_gmac.h148 /* Transmit End of Ring */
152 /* Transmit Buffer 2 Size */
154 /* Transmit Buffer 1 Size */
178 /* Transmit Process State */
180 /* Transmit States */
193 /* Transmit Process State */
214 /* Early transmit Interrupt */
224 /* Transmit Underflow */
228 /* Transmit Jabber Timeout */
230 /* Transmit Buffer Unavailable */
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H A Dnpcm7xx_emc.h107 /* Enable Transmit Descriptor Unavailable Interrupt */
109 /* Enable Transmit Completion Interrupt */
111 /* Enable Transmit Interrupt */
122 /* Transmit Bus Error Interrupt */
124 /* Transmit Descriptor Unavailable Interrupt */
126 /* Transmit Completion Interrupt */
128 /* Transmit Interrupt */
159 /* Transmit and receive descriptors */
180 /* Transmit interrupt enable */
209 /* Transmit interrupt */
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/openbmc/qemu/hw/net/fsl_etsec/
H A Dregisters.c42 {0x08C, "FIFO_TX_THR", "FIFO transmit threshold register", ACC_RW, 0x00000…
43 {0x098, "FIFO_TX_STARVE", "FIFO transmit starve register", ACC_RW, 0x00000…
44 {0x09C, "FIFO_TX_STARVE_SHUTOFF", "FIFO transmit starve shut-off register", ACC_RW, 0x00000…
46 /* eTSEC Transmit Control and Status Registers */
48 {0x100, "TCTRL", "Transmit control register", ACC_RW, 0x00000000},
49 {0x104, "TSTAT", "Transmit status register", ACC_W1C, 0x00000000},
51 {0x110, "TXIC", "Transmit interrupt coalescing register", ACC_RW, 0x00000000},
52 {0x114, "TQUEUE", "Transmit queue control register", ACC_RW, 0x00008000},
159 /* eTSEC, "Transmit", "and", Receive, Counters */
161 {0x680, "TR64", "Transmit and receive 64-byte frame counter ", ACC_RW, 0x0000000…
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/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-class-net-queues24 Indicates the number of transmit timeout events seen by this
25 network interface transmit queue.
41 Transmit Packet Steering packet processing flow for this
42 network device transmit queue. Possible values depend on the
51 into the Transmit Packet Steering packet processing flow for this
52 network device transmit queue. Possible values depend on the
62 of this particular network device transmit queue.
71 network device transmit queue.
79 on this network device transmit queue. This value is clamped
88 queued on this network device transmit queue. See
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac_dma.h16 #define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */
19 #define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
74 #define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
75 #define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */
85 #define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
91 #define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
92 #define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
110 #define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
118 #define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
123 #define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
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/openbmc/linux/include/soc/fsl/qe/
H A Dimmap_qe.h152 __be32 spitd; /* SPI transmit data register (cpu mode) */
242 __be16 utodr; /* UCCx transmit on demand register */
259 __be16 utodr; /* UCCx transmit on demand register */
273 __be32 utfb; /* UCC transmit FIFO base */
274 __be16 utfs; /* UCC transmit FIFO size */
276 __be16 utfet; /* UCC transmit FIFO emergency threshold */
278 __be16 utftt; /* UCC transmit FIFO transmit threshold */
280 __be16 utpt; /* UCC transmit polling timer */
328 __be16 uptirr1_0; /* Device 1 transmit internal rate 0 */
329 __be16 uptirr1_1; /* Device 1 transmit internal rate 1 */
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/openbmc/linux/include/net/caif/
H A Dcaif_layer.h38 * @CAIF_CTRLCMD_FLOW_OFF_IND: Flow Control is OFF, transmit function
41 * @CAIF_CTRLCMD_FLOW_ON_IND: Flow Control is ON, transmit function
82 * @CAIF_MODEMCMD_FLOW_ON_REQ: Flow Control is ON, transmit function
85 * @CAIF_MODEMCMD_FLOW_OFF_REQ: Flow Control is OFF, transmit function
121 * @transmit: Packet transmit funciton.
146 * layer->dn->transmit(layer->dn, info, packet);
182 * transmit() - Transmit Function (non-blocking).
183 * Contract: Each layer must implement a transmit function passing the
187 * transmit function. This means that the packet
189 * layer using dn->transmit().
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/openbmc/linux/drivers/net/wan/
H A Dhd64570.c89 static inline u16 next_desc(port_t *port, u16 desc, int transmit) in next_desc() argument
91 return (desc + 1) % (transmit ? port_to_card(port)->tx_ring_buffers in next_desc()
95 static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit) in desc_abs_number() argument
100 desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc. in desc_abs_number()
102 transmit * rx_buffs + desc; in desc_abs_number()
105 static inline u16 desc_offset(port_t *port, u16 desc, int transmit) in desc_offset() argument
108 return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc); in desc_offset()
112 int transmit) in desc_address() argument
116 + desc_offset(port, desc, transmit)); in desc_address()
119 + desc_offset(port, desc, transmit)); in desc_address()
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/openbmc/linux/Documentation/networking/
H A Dscaling.rst21 - XPS: Transmit Packet Steering
27 Contemporary NICs support multiple receive and transmit descriptor queues
395 XPS: Transmit Packet Steering
398 Transmit Packet Steering is a mechanism for intelligently selecting
399 which transmit queue to use when transmitting a packet on a multi-queue
402 to hardware transmit queue(s).
407 exclusively to a subset of CPUs, where the transmit completions for
412 transmit queue). Secondly, cache miss rate on transmit completion is
418 This mapping is used to pick transmit queue based on the receive
420 queues can be mapped to a set of transmit queues (many:many), although
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/openbmc/linux/sound/soc/ti/
H A Ddavinci-mcasp.h84 /* Transmit Buffer for Serializer n */
122 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
124 #define DITEN BIT(0) /* Transmit DIT mode enable/disable */
129 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
151 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
167 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
185 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
224 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
243 #define TXSERCLR BIT(10) /* Transmit Serializer Clear */
251 #define XRERR BIT(8) /* Transmit/Receive error */
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/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dimx-sata.yaml41 fsl,transmit-level-mV:
43 description: transmit voltage level, in millivolts.
45 fsl,transmit-boost-mdB:
47 description: transmit boost level, in milli-decibels.
49 fsl,transmit-atten-16ths:
51 description: transmit attenuation, in 16ths.
/openbmc/linux/sound/soc/pxa/
H A Dmmp-sspa.h25 #define SSPA_CTL_XFIG (1 << 15) /* Transmit Zeros when FIFO Empty */
28 #define SSPA_CTL_XFRLEN2(x) ((x) << 24) /* Transmit Frame Length in Phase 2 */
30 #define SSPA_CTL_XWDLEN2(x) ((x) << 21) /* Transmit Word Length in Phase 2 */
31 #define SSPA_CTL_XDATDLY(x) ((x) << 19) /* Transmit Data Delay */
33 #define SSPA_CTL_XSSZ2(x) ((x) << 16) /* Transmit Sample Audio Size */
35 #define SSPA_CTL_XFRLEN1(x) ((x) << 8) /* Transmit Frame Length in Phase 1 */
37 #define SSPA_CTL_XWDLEN1(x) ((x) << 5) /* Transmit Word Length in Phase 1 */
/openbmc/u-boot/include/linux/
H A Dimmap_qe.h185 u32 spitd; /* SPI transmit data register (cpu mode) */
281 u16 utodr; /* UCCx transmit on demand register */
383 u16 utodr; /* UCCx transmit on demand register */
397 u32 utfb; /* UCC transmit FIFO base */
398 u16 utfs; /* UCC transmit FIFO size */
400 u16 utfet; /* UCC transmit FIFO emergency threshold */
402 u16 utftt; /* UCC transmit FIFO transmit threshold */
404 u16 utpt; /* UCC transmit polling timer */
461 u16 uptirr1_0; /* Device 1 transmit internal rate 0 */
462 u16 uptirr1_1; /* Device 1 transmit internal rate 1 */
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/openbmc/linux/drivers/net/fddi/
H A Ddefza.h40 #define FZA_EVENT_FLUSH_TX 0x0400 /* transmit ring flush request */
51 #define FZA_EVENT_SMT_TX_POLL 0x0004 /* SMT frame transmit request */
53 #define FZA_EVENT_TX_DONE 0x0001 /* RMC transmit done ack */
159 #define FZA_MASK_FLUSH_TX 0x0400 /* transmit ring flush request */
170 #define FZA_MASK_SMT_TX_POLL 0x0004 /* SMT frame transmit request */
173 #define FZA_MASK_TX_DONE 0x0001 /* RMC transmit done acknowledge */
193 #define FZA_CONTROL_A_TX_POLL 0x0001 /* transmit poll */
279 #define FZA_RING_UNS_TX_UNDER 0x0000000c /* transmit underrun */
280 #define FZA_RING_UNS_TX_FAIL 0x0000000d /* transmit failure */
283 /* RMC (Ring Memory Control) transmit descriptor ring entry. */
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/openbmc/linux/drivers/net/ethernet/freescale/fman/
H A Dfman_mac.h90 /* 10GEC, mEMAC Transmit frame ECC error interrupt */
92 /* 10GEC, mEMAC Transmit FIFO underflow interrupt */
94 /* 10GEC, mEMAC Transmit FIFO overflow interrupt */
96 /* 10GEC Transmit frame error interrupt */
120 /* dTSEC Graceful transmit stop complete */
122 /* dTSEC Babbling transmit error */
124 /* dTSEC Transmit control (pause frame) interrupt */
126 /* dTSEC Transmit error */
132 /* dTSEC Transmit FIFO underrun */
142 /* dTSEC Internal data error on transmit */
/openbmc/linux/include/linux/
H A Dpxa2xx_ssp.h63 #define SSCR0_TUM BIT(23) /* Transmit FIFO underrun interrupt mask */
71 #define SSCR1_TIE BIT(1) /* Transmit FIFO Interrupt Enable */
75 #define SSCR1_MWDS BIT(5) /* Microwire Transmit Data Size */
78 #define SSSR_TNF BIT(2) /* Transmit FIFO Not Full */
81 #define SSSR_TFS BIT(5) /* Transmit FIFO Service Request */
88 #define SSSR_TFL_MASK GENMASK(11, 8) /* Transmit FIFO Level mask */
91 #define SSCR1_TFT GENMASK(9, 6) /* Transmit FIFO Threshold (mask) */
99 #define CE4100_SSSR_TFL_MASK GENMASK(9, 8) /* Transmit FIFO Level mask */
102 #define CE4100_SSCR1_TFT GENMASK(7, 6) /* Transmit FIFO Threshold (mask) */
119 #define QUARK_X1000_SSSR_TFL_MASK GENMASK(12, 8) /* Transmit FIFO Level mask */
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