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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dqcom,tcsr.yaml4 $id: http://devicetree.org/schemas/mfd/qcom,tcsr.yaml#
20 - qcom,msm8976-tcsr
21 - qcom,msm8998-tcsr
22 - qcom,qcs404-tcsr
23 - qcom,sc7180-tcsr
24 - qcom,sc7280-tcsr
25 - qcom,sc8280xp-tcsr
26 - qcom,sdm630-tcsr
27 - qcom,sdm845-tcsr
28 - qcom,sdx55-tcsr
[all …]
/openbmc/linux/Documentation/devicetree/bindings/hwlock/
H A Dqcom-hwspinlock.yaml21 - qcom,tcsr-mutex
24 - qcom,apq8084-tcsr-mutex
25 - qcom,ipq6018-tcsr-mutex
26 - qcom,msm8226-tcsr-mutex
27 - qcom,msm8994-tcsr-mutex
28 - const: qcom,tcsr-mutex
31 - qcom,msm8974-tcsr-mutex
32 - const: qcom,tcsr-mutex
51 compatible = "qcom,tcsr-mutex";
/openbmc/linux/drivers/soc/qcom/
H A Dqcom_gsbi.c114 struct regmap *tcsr; member
118 { .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064},
119 { .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064},
120 { .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960},
121 { .compatible = "qcom,tcsr-msm8660", .data = &config_msm8660},
145 /* get the tcsr node and setup the config and regmap */ in gsbi_probe()
146 gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr"); in gsbi_probe()
148 if (!IS_ERR(gsbi->tcsr)) { in gsbi_probe()
149 tcsr_node = of_parse_phandle(node, "syscon-tcsr", 0); in gsbi_probe()
155 dev_warn(&pdev->dev, "no matching TCSR\n"); in gsbi_probe()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sm8550-tcsr.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml#
7 title: Qualcomm TCSR Clock Controller on SM8550
13 Qualcomm TCSR clock control module provides the clocks, resets and
16 See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h
21 - const: qcom,sm8550-tcsr
48 compatible = "qcom,sm8550-tcsr", "syscon";
/openbmc/qemu/hw/timer/
H A Dnpcm7xx_timer.c122 static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr) in npcm7xx_tcsr_prescaler() argument
124 return extract32(tcsr, NPCM7XX_TCSR_PRESCALE_START, in npcm7xx_tcsr_prescaler()
133 ticks *= npcm7xx_tcsr_prescaler(t->tcsr); in npcm7xx_timer_count_to_ns()
145 npcm7xx_tcsr_prescaler(t->tcsr); in npcm7xx_timer_ns_to_count()
201 bool pending = (t->tcsr & NPCM7XX_TCSR_IE) && (tc->tisr & BIT(index)); in npcm7xx_timer_check_interrupt()
218 if (t->tcsr & NPCM7XX_TCSR_PERIODIC) { in npcm7xx_timer_reached_zero()
220 if (t->tcsr & NPCM7XX_TCSR_CEN) { in npcm7xx_timer_reached_zero()
224 t->tcsr &= ~(NPCM7XX_TCSR_CEN | NPCM7XX_TCSR_CACT); in npcm7xx_timer_reached_zero()
241 if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) { in npcm7xx_timer_restart()
250 if (t->tcsr & NPCM7XX_TCSR_CEN) { in npcm7xx_timer_read_tdr()
[all …]
H A Drenesas_tmr.c37 REG8(TCSR, 2)
38 FIELD(TCSR, OSA, 0, 2)
39 FIELD(TCSR, OSB, 2, 2)
40 FIELD(TCSR, ADTE, 4, 2)
219 ret = FIELD_DP8(ret, TCSR, OSA, in tmr_read()
220 FIELD_EX8(tmr->tcsr[ch], TCSR, OSA)); in tmr_read()
221 ret = FIELD_DP8(ret, TCSR, OSB, in tmr_read()
222 FIELD_EX8(tmr->tcsr[ch], TCSR, OSB)); in tmr_read()
225 ret = FIELD_DP8(ret, TCSR, ADTE, in tmr_read()
226 FIELD_EX8(tmr->tcsr[ch], TCSR, ADTE)); in tmr_read()
[all …]
/openbmc/linux/include/clocksource/
H A Dtimer-xilinx.h51 * @tcsr: The value of the TCSR register for this counter
59 u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr,
66 * @tcsr: The value of TCSR for this counter
71 u32 tlr, u32 tcsr);
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8660.dtsi150 syscon-tcsr = <&tcsr>;
176 syscon-tcsr = <&tcsr>;
202 syscon-tcsr = <&tcsr>;
237 syscon-tcsr = <&tcsr>;
271 syscon-tcsr = <&tcsr>;
296 syscon-tcsr = <&tcsr>;
645 tcsr: syscon@1a400000 { label
646 compatible = "qcom,tcsr-msm8660", "syscon";
H A Dqcom-ipq8064.dtsi781 syscon-tcsr = <&tcsr>;
820 syscon-tcsr = <&tcsr>;
857 syscon-tcsr = <&tcsr>;
893 syscon-tcsr = <&tcsr>;
936 syscon-tcsr = <&tcsr>;
995 syscon-tcsr = <&tcsr>;
1034 tcsr: syscon@1a400000 { label
1035 compatible = "qcom,tcsr-ipq8064", "syscon";
H A Dqcom-mdm9615.dtsi206 syscon-tcsr = <&tcsr>;
230 syscon-tcsr = <&tcsr>;
371 tcsr: syscon@1a400000 { label
372 compatible = "qcom,tcsr-mdm9615", "syscon";
H A Dqcom-msm8960.dtsi249 syscon-tcsr = <&tcsr>;
346 tcsr: syscon@1a400000 { label
347 compatible = "qcom,tcsr-msm8960", "syscon";
/openbmc/linux/drivers/hwspinlock/
H A Dqcom_hwspinlock.c116 { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex },
117 { .compatible = "qcom,apq8084-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
118 { .compatible = "qcom,ipq6018-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
119 { .compatible = "qcom,msm8226-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
120 { .compatible = "qcom,msm8974-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
121 { .compatible = "qcom,msm8994-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
/openbmc/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,gsbi.yaml57 syscon-tcsr:
60 Phandle of TCSR syscon node.Required if child uses dma.
106 syscon-tcsr = <&tcsr>;
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qusb2.c276 /* offset to PHY_CLK_SCHEME register in TCSR map */
418 * @tcsr: TCSR syscon register map
438 struct regmap *tcsr; member
796 * register in the TCSR so, if there's none, use the default in qusb2_phy_init()
807 if (qphy->tcsr) { in qusb2_phy_init()
808 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, in qusb2_phy_init()
1009 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, in qusb2_phy_probe()
1010 "qcom,tcsr-syscon"); in qusb2_phy_probe()
1011 if (IS_ERR(qphy->tcsr)) { in qusb2_phy_probe()
1012 dev_dbg(dev, "failed to lookup TCSR regmap\n"); in qusb2_phy_probe()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-ep.yaml49 description: Reference to a syscon representing TCSR followed by the two
55 - description: Syscon to TCSR system registers
206 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
/openbmc/linux/drivers/clk/qcom/
H A Dtcsrcc-sm8550.c14 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
169 { .compatible = "qcom,sar2130p-tcsr", .data = &tcsr_cc_sar2130p_desc },
170 { .compatible = "qcom,sm8550-tcsr", .data = &tcsr_cc_sm8550_desc },
/openbmc/qemu/include/hw/timer/
H A Dnpcm7xx_timer.h57 * @tcsr: The Timer Control and Status Register.
66 uint32_t tcsr; member
/openbmc/linux/Documentation/arch/mips/
H A Dingenic-tcu.rst19 different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
/openbmc/linux/drivers/pmdomain/qcom/
H A Dcpr.c236 struct regmap *tcsr; member
392 static void cpr_set_acc(struct regmap *tcsr, struct fuse_corner *f, in cpr_set_acc() argument
400 regmap_multi_reg_write(tcsr, f->accs, f->num_accs); in cpr_set_acc()
403 regmap_multi_reg_write(tcsr, f->accs, f->num_accs); in cpr_set_acc()
413 if (drv->tcsr && dir == DOWN) in cpr_pre_voltage()
414 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); in cpr_pre_voltage()
425 if (drv->tcsr && dir == UP) in cpr_post_voltage()
426 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); in cpr_post_voltage()
1538 regmap_multi_reg_write(drv->tcsr, acc_desc->config, in cpr_pd_attach_dev()
1543 regmap_update_bits(drv->tcsr, acc_desc->enable_reg, in cpr_pd_attach_dev()
[all …]
/openbmc/linux/drivers/pwm/
H A Dpwm-xilinx.c34 u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr, in xilinx_timer_tlr_cycles() argument
39 if (tcsr & TCSR_UDT) in xilinx_timer_tlr_cycles()
45 u32 tlr, u32 tcsr) in xilinx_timer_get_period() argument
49 if (tcsr & TCSR_UDT) in xilinx_timer_get_period()
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dipq5332.dtsi83 qcom,dload-mode = <&tcsr 0x6100>;
194 compatible = "qcom,tcsr-mutex";
199 tcsr: syscon@1937000 { label
200 compatible = "qcom,tcsr-ipq5332", "syscon";
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,qcs404-cdsp-pil.yaml83 Phandle reference to a syscon representing TCSR followed by the
154 qcom,halt-regs = <&tcsr 0x19004>;
/openbmc/linux/Documentation/devicetree/bindings/firmware/
H A Dqcom,scm.yaml96 - description: phandle to TCSR hardware block
98 description: TCSR hardware block
/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_tai.c242 u32 tcsr; in mvpp22_tai_gettimex64() local
260 tcsr = readl(base + MVPP22_TAI_TCSR); in mvpp22_tai_gettimex64()
261 if (tcsr & TCSR_CAPTURE_1_VALID) { in mvpp22_tai_gettimex64()
264 } else if (tcsr & TCSR_CAPTURE_0_VALID) { in mvpp22_tai_gettimex64()
/openbmc/linux/drivers/clk/ingenic/
H A Dtcu.c130 WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx); in ingenic_tcu_get_parent()
146 WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx); in ingenic_tcu_set_parent()
163 WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx); in ingenic_tcu_recalc_rate()
212 WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx); in ingenic_tcu_set_rate()

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