1*841fdd0aSRakesh Pillai# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*841fdd0aSRakesh Pillai%YAML 1.2
3*841fdd0aSRakesh Pillai---
4*841fdd0aSRakesh Pillai$id: http://devicetree.org/schemas/remoteproc/qcom,qcs404-cdsp-pil.yaml#
5*841fdd0aSRakesh Pillai$schema: http://devicetree.org/meta-schemas/core.yaml#
6*841fdd0aSRakesh Pillai
7*841fdd0aSRakesh Pillaititle: Qualcomm QCS404 CDSP Peripheral Image Loader
8*841fdd0aSRakesh Pillai
9*841fdd0aSRakesh Pillaimaintainers:
10*841fdd0aSRakesh Pillai  - Bjorn Andersson <bjorn.andersson@linaro.org>
11*841fdd0aSRakesh Pillai
12*841fdd0aSRakesh Pillaidescription:
13*841fdd0aSRakesh Pillai  This document defines the binding for a component that loads and boots firmware
14*841fdd0aSRakesh Pillai  on the Qualcomm Technology Inc. CDSP (Compute DSP).
15*841fdd0aSRakesh Pillai
16*841fdd0aSRakesh Pillaiproperties:
17*841fdd0aSRakesh Pillai  compatible:
18*841fdd0aSRakesh Pillai    enum:
19*841fdd0aSRakesh Pillai      - qcom,qcs404-cdsp-pil
20*841fdd0aSRakesh Pillai
21*841fdd0aSRakesh Pillai  reg:
22*841fdd0aSRakesh Pillai    maxItems: 1
23*841fdd0aSRakesh Pillai    description:
24*841fdd0aSRakesh Pillai      The base address and size of the qdsp6ss register
25*841fdd0aSRakesh Pillai
26*841fdd0aSRakesh Pillai  interrupts:
27*841fdd0aSRakesh Pillai    items:
28*841fdd0aSRakesh Pillai      - description: Watchdog interrupt
29*841fdd0aSRakesh Pillai      - description: Fatal interrupt
30*841fdd0aSRakesh Pillai      - description: Ready interrupt
31*841fdd0aSRakesh Pillai      - description: Handover interrupt
32*841fdd0aSRakesh Pillai      - description: Stop acknowledge interrupt
33*841fdd0aSRakesh Pillai
34*841fdd0aSRakesh Pillai  interrupt-names:
35*841fdd0aSRakesh Pillai    items:
36*841fdd0aSRakesh Pillai      - const: wdog
37*841fdd0aSRakesh Pillai      - const: fatal
38*841fdd0aSRakesh Pillai      - const: ready
39*841fdd0aSRakesh Pillai      - const: handover
40*841fdd0aSRakesh Pillai      - const: stop-ack
41*841fdd0aSRakesh Pillai
42*841fdd0aSRakesh Pillai  clocks:
43*841fdd0aSRakesh Pillai    items:
44*841fdd0aSRakesh Pillai      - description: XO clock
45*841fdd0aSRakesh Pillai      - description: SWAY clock
46*841fdd0aSRakesh Pillai      - description: TBU clock
47*841fdd0aSRakesh Pillai      - description: BIMC clock
48*841fdd0aSRakesh Pillai      - description: AHB AON clock
49*841fdd0aSRakesh Pillai      - description: Q6SS SLAVE clock
50*841fdd0aSRakesh Pillai      - description: Q6SS MASTER clock
51*841fdd0aSRakesh Pillai      - description: Q6 AXIM clock
52*841fdd0aSRakesh Pillai
53*841fdd0aSRakesh Pillai  clock-names:
54*841fdd0aSRakesh Pillai    items:
55*841fdd0aSRakesh Pillai      - const: xo
56*841fdd0aSRakesh Pillai      - const: sway
57*841fdd0aSRakesh Pillai      - const: tbu
58*841fdd0aSRakesh Pillai      - const: bimc
59*841fdd0aSRakesh Pillai      - const: ahb_aon
60*841fdd0aSRakesh Pillai      - const: q6ss_slave
61*841fdd0aSRakesh Pillai      - const: q6ss_master
62*841fdd0aSRakesh Pillai      - const: q6_axim
63*841fdd0aSRakesh Pillai
64*841fdd0aSRakesh Pillai  power-domains:
65*841fdd0aSRakesh Pillai    items:
66*841fdd0aSRakesh Pillai      - description: CX power domain
67*841fdd0aSRakesh Pillai
68*841fdd0aSRakesh Pillai  resets:
69*841fdd0aSRakesh Pillai    items:
70*841fdd0aSRakesh Pillai      - description: AOSS restart
71*841fdd0aSRakesh Pillai
72*841fdd0aSRakesh Pillai  reset-names:
73*841fdd0aSRakesh Pillai    items:
74*841fdd0aSRakesh Pillai      - const: restart
75*841fdd0aSRakesh Pillai
76*841fdd0aSRakesh Pillai  memory-region:
77*841fdd0aSRakesh Pillai    maxItems: 1
78*841fdd0aSRakesh Pillai    description: Reference to the reserved-memory for the Hexagon core
79*841fdd0aSRakesh Pillai
80*841fdd0aSRakesh Pillai  qcom,halt-regs:
81*841fdd0aSRakesh Pillai    $ref: /schemas/types.yaml#/definitions/phandle-array
82*841fdd0aSRakesh Pillai    description:
83*841fdd0aSRakesh Pillai      Phandle reference to a syscon representing TCSR followed by the
84*841fdd0aSRakesh Pillai      three offsets within syscon for q6, modem and nc halt registers.
85*841fdd0aSRakesh Pillai
86*841fdd0aSRakesh Pillai  qcom,smem-states:
87*841fdd0aSRakesh Pillai    $ref: /schemas/types.yaml#/definitions/phandle-array
88*841fdd0aSRakesh Pillai    description: States used by the AP to signal the Hexagon core
89*841fdd0aSRakesh Pillai    items:
90*841fdd0aSRakesh Pillai      - description: Stop the modem
91*841fdd0aSRakesh Pillai
92*841fdd0aSRakesh Pillai  qcom,smem-state-names:
93*841fdd0aSRakesh Pillai    description: The names of the state bits used for SMP2P output
94*841fdd0aSRakesh Pillai    items:
95*841fdd0aSRakesh Pillai      - const: stop
96*841fdd0aSRakesh Pillai
97*841fdd0aSRakesh Pillairequired:
98*841fdd0aSRakesh Pillai  - compatible
99*841fdd0aSRakesh Pillai  - reg
100*841fdd0aSRakesh Pillai  - interrupts
101*841fdd0aSRakesh Pillai  - interrupt-names
102*841fdd0aSRakesh Pillai  - clocks
103*841fdd0aSRakesh Pillai  - clock-names
104*841fdd0aSRakesh Pillai  - power-domains
105*841fdd0aSRakesh Pillai  - resets
106*841fdd0aSRakesh Pillai  - reset-names
107*841fdd0aSRakesh Pillai  - qcom,halt-regs
108*841fdd0aSRakesh Pillai  - memory-region
109*841fdd0aSRakesh Pillai  - qcom,smem-states
110*841fdd0aSRakesh Pillai  - qcom,smem-state-names
111*841fdd0aSRakesh Pillai
112*841fdd0aSRakesh PillaiadditionalProperties: false
113*841fdd0aSRakesh Pillai
114*841fdd0aSRakesh Pillaiexamples:
115*841fdd0aSRakesh Pillai  - |
116*841fdd0aSRakesh Pillai    #include <dt-bindings/interrupt-controller/arm-gic.h>
117*841fdd0aSRakesh Pillai    #include <dt-bindings/clock/qcom,gcc-qcs404.h>
118*841fdd0aSRakesh Pillai    #include <dt-bindings/power/qcom-rpmpd.h>
119*841fdd0aSRakesh Pillai    #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
120*841fdd0aSRakesh Pillai    remoteproc@b00000 {
121*841fdd0aSRakesh Pillai        compatible = "qcom,qcs404-cdsp-pil";
122*841fdd0aSRakesh Pillai        reg = <0x00b00000 0x4040>;
123*841fdd0aSRakesh Pillai
124*841fdd0aSRakesh Pillai        interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
125*841fdd0aSRakesh Pillai                              <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
126*841fdd0aSRakesh Pillai                              <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
127*841fdd0aSRakesh Pillai                              <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
128*841fdd0aSRakesh Pillai                              <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
129*841fdd0aSRakesh Pillai        interrupt-names = "wdog", "fatal", "ready",
130*841fdd0aSRakesh Pillai                          "handover", "stop-ack";
131*841fdd0aSRakesh Pillai
132*841fdd0aSRakesh Pillai        clocks = <&xo_board>,
133*841fdd0aSRakesh Pillai                 <&gcc GCC_CDSP_CFG_AHB_CLK>,
134*841fdd0aSRakesh Pillai                 <&gcc GCC_CDSP_TBU_CLK>,
135*841fdd0aSRakesh Pillai                 <&gcc GCC_BIMC_CDSP_CLK>,
136*841fdd0aSRakesh Pillai                 <&turingcc TURING_WRAPPER_AON_CLK>,
137*841fdd0aSRakesh Pillai                 <&turingcc TURING_Q6SS_AHBS_AON_CLK>,
138*841fdd0aSRakesh Pillai                 <&turingcc TURING_Q6SS_AHBM_AON_CLK>,
139*841fdd0aSRakesh Pillai                 <&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
140*841fdd0aSRakesh Pillai        clock-names = "xo",
141*841fdd0aSRakesh Pillai                      "sway",
142*841fdd0aSRakesh Pillai                      "tbu",
143*841fdd0aSRakesh Pillai                      "bimc",
144*841fdd0aSRakesh Pillai                      "ahb_aon",
145*841fdd0aSRakesh Pillai                      "q6ss_slave",
146*841fdd0aSRakesh Pillai                      "q6ss_master",
147*841fdd0aSRakesh Pillai                      "q6_axim";
148*841fdd0aSRakesh Pillai
149*841fdd0aSRakesh Pillai        power-domains = <&rpmhpd SDM845_CX>;
150*841fdd0aSRakesh Pillai
151*841fdd0aSRakesh Pillai        resets = <&gcc GCC_CDSP_RESTART>;
152*841fdd0aSRakesh Pillai        reset-names = "restart";
153*841fdd0aSRakesh Pillai
154*841fdd0aSRakesh Pillai        qcom,halt-regs = <&tcsr 0x19004>;
155*841fdd0aSRakesh Pillai
156*841fdd0aSRakesh Pillai        memory-region = <&cdsp_fw_mem>;
157*841fdd0aSRakesh Pillai
158*841fdd0aSRakesh Pillai        qcom,smem-states = <&cdsp_smp2p_out 0>;
159*841fdd0aSRakesh Pillai        qcom,smem-state-names = "stop";
160*841fdd0aSRakesh Pillai    };
161