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/openbmc/qemu/hw/audio/
H A Dhda-codec.c135 #define B_SIZE sizeof(st->buf)
136 #define B_MASK (sizeof(st->buf) - 1)
183 HDAAudioStream st[4]; member
193 static inline uint32_t hda_bytes_per_second(HDAAudioStream *st) in hda_bytes_per_second() argument
195 return 2 * (uint32_t)st->as.nchannels * (uint32_t)st->as.freq; in hda_bytes_per_second()
198 static inline void hda_timer_sync_adjust(HDAAudioStream *st, int64_t target_pos) in hda_timer_sync_adjust() argument
216 trace_hda_audio_adjust(st->node->name, target_pos); in hda_timer_sync_adjust()
217 st->buft_start += corr; in hda_timer_sync_adjust()
222 HDAAudioStream *st = opaque; in hda_audio_input_timer() local
226 int64_t uptime = now - st->buft_start; in hda_audio_input_timer()
[all …]
H A Dintel-hda.c180 IntelHDAStream st[8]; member
246 if (d->st[i].ctl & (1 << 26)) { in intel_hda_update_int_sts()
403 IntelHDAStream *st; in intel_hda_xfer() local
406 st = output ? d->st + 4 : d->st; in intel_hda_xfer()
408 if (stnr == ((st[s].ctl >> 20) & 0x0f)) { in intel_hda_xfer()
409 st = st + s; in intel_hda_xfer()
416 if (st->bpl == NULL) { in intel_hda_xfer()
421 s = st->bentries; in intel_hda_xfer()
424 if (copy > st->bsize - st->lpib) in intel_hda_xfer()
425 copy = st->bsize - st->lpib; in intel_hda_xfer()
[all …]
/openbmc/qemu/include/crypto/
H A Daes-round.h27 void aesenc_MC_gen(AESState *ret, const AESState *st);
28 void aesenc_MC_genrev(AESState *ret, const AESState *st);
30 static inline void aesenc_MC(AESState *r, const AESState *st, bool be) in aesenc_MC() argument
33 aesenc_MC_accel(r, st, be); in aesenc_MC()
35 aesenc_MC_gen(r, st); in aesenc_MC()
37 aesenc_MC_genrev(r, st); in aesenc_MC()
45 void aesenc_SB_SR_AK_gen(AESState *ret, const AESState *st,
47 void aesenc_SB_SR_AK_genrev(AESState *ret, const AESState *st,
50 static inline void aesenc_SB_SR_AK(AESState *r, const AESState *st, in aesenc_SB_SR_AK() argument
54 aesenc_SB_SR_AK_accel(r, st, rk, be); in aesenc_SB_SR_AK()
[all …]
/openbmc/qemu/hw/timer/
H A Dmss-timer.c60 static void timer_update_irq(struct Msf2Timer *st) in timer_update_irq() argument
64 isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); in timer_update_irq()
65 ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); in timer_update_irq()
66 qemu_set_irq(st->irq, (ier && isr)); in timer_update_irq()
70 static void timer_update(struct Msf2Timer *st) in timer_update() argument
74 if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) { in timer_update()
75 ptimer_stop(st->ptimer); in timer_update()
79 count = st->regs[R_TIM_LOADVAL]; in timer_update()
80 ptimer_set_limit(st->ptimer, count, 1); in timer_update()
81 ptimer_run(st->ptimer, 1); in timer_update()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dstm32mp157c.dtsi4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
112 compatible = "st,stm32mp157c-pd";
139 compatible = "st,stm32-timers";
146 compatible = "st,stm32-pwm";
151 compatible = "st,stm32h7-timer-trigger";
160 compatible = "st,stm32-timers";
167 compatible = "st,stm32-pwm";
172 compatible = "st,stm32h7-timer-trigger";
181 compatible = "st,stm32-timers";
188 compatible = "st,stm32-pwm";
[all …]
H A Dstih407-family.dtsi3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10 #include <dt-bindings/mfd/st-lpc.h>
13 #include <dt-bindings/interrupt-controller/irq-st.h>
50 st,syscfg = <&syscfg_core 0x8e0>;
122 compatible = "st,stih407-restart";
123 st,syscfg = <&syscfg_sbc_reg>;
128 compatible = "st,stih407-powerdown";
133 compatible = "st,stih407-softreset";
138 compatible = "st,stih407-picophyreset";
143 compatible = "st,stih407-sbc-syscfg", "syscon";
[all …]
H A Dstm32f429.dtsi78 compatible = "st,stm32-timer";
88 compatible = "st,stm32-timers";
95 compatible = "st,stm32-pwm";
100 compatible = "st,stm32-timer-trigger";
107 compatible = "st,stm32-timer";
117 compatible = "st,stm32-timers";
124 compatible = "st,stm32-pwm";
129 compatible = "st,stm32-timer-trigger";
136 compatible = "st,stm32-timer";
146 compatible = "st,stm32-timers";
[all …]
H A Dstih407-pinctrl.dtsi3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9 #include "st-pincfg.h"
51 compatible = "st,stih407-sbc-pinctrl";
52 st,syscfg = <&syscfg_sbc>;
65 st,bank-name = "PIO0";
73 st,bank-name = "PIO1";
81 st,bank-name = "PIO2";
89 st,bank-name = "PIO3";
97 st,bank-name = "PIO4";
106 st,bank-name = "PIO5";
[all …]
H A Dstm32f746.dtsi3 * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
65 compatible = "st,stm32-dwmac";
80 compatible = "st,stm32-fmc";
87 compatible = "st,stm32-qspi";
99 compatible = "st,stm32f7-usart", "st,stm32f7-uart";
115 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
118 st,syscfg = <&pwrcfg>;
125 compatible = "st,stm32f746-pinctrl";
133 compatible = "st,stm32-gpio";
136 st,bank-name = "GPIOA";
[all …]
H A Dstm32mp15-ddr.dtsi11 compatible = "st,stm32mp1-ddr";
30 st,mem-name = DDR_MEM_NAME;
31 st,mem-speed = <DDR_MEM_SPEED>;
32 st,mem-size = <DDR_MEM_SIZE>;
34 st,ctl-reg = <
62 st,ctl-timing = <
77 st,ctl-map = <
89 st,ctl-perf = <
109 st,phy-reg = <
123 st,phy-timing = <
[all …]
H A Dstm32mp157-u-boot.dtsi34 compatible = "st,stm32-stgen";
79 compatible = "st,stm32-gpio";
84 compatible = "st,stm32-gpio";
89 compatible = "st,stm32-gpio";
94 compatible = "st,stm32-gpio";
99 compatible = "st,stm32-gpio";
104 compatible = "st,stm32-gpio";
109 compatible = "st,stm32-gpio";
114 compatible = "st,stm32-gpio";
119 compatible = "st,stm32-gpio";
[all …]
H A Dstm32h743-pinctrl.dtsi2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
50 compatible = "st,stm32h743-pinctrl";
57 compatible = "st,stm32-gpio";
60 st,bank-name = "GPIOA";
66 compatible = "st,stm32-gpio";
69 st,bank-name = "GPIOB";
75 compatible = "st,stm32-gpio";
78 st,bank-name = "GPIOC";
84 compatible = "st,stm32-gpio";
87 st,bank-name = "GPIOD";
[all …]
H A Dstm32f429-disco-u-boot.dtsi4 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
35 compatible = "st,stm32-fmc";
40 st,syscfg = <&syscfg>;
41 st,swp_fmc = <1>;
49 st,sdram-control = /bits/ 8 <NO_COL_8
57 st,sdram-timing = /bits/ 8 <TMRD_3
63 st,sdram-refcount = < 1386 >;
90 compatible = "st,stm32-gpio";
95 compatible = "st,stm32-gpio";
100 compatible = "st,stm32-gpio";
[all …]
H A Dstih410.dtsi19 st,syscfg = <&syscfg_core 0x8e0>;
20 st,syscfg-eng = <&syscfg_opp 0x4 0x0>;
64 compatible = "st,stih407-usb2-phy";
66 st,syscfg = <&syscfg_core 0xf8 0xf4>;
75 compatible = "st,stih407-usb2-phy";
77 st,syscfg = <&syscfg_core 0xfc 0xf4>;
153 compatible = "st,sti-display-subsystem";
190 compatible = "st,stih407-compositor";
218 st,vtg = <&vtg_main>, <&vtg_aux>;
222 compatible = "st,stih407-tvout";
[all …]
H A Dstih407-clock.dtsi40 compatible = "st,clkgen-c32";
45 compatible = "st,stih407-clkgen-plla9";
58 compatible = "st,stih407-clkgen-a9-mux";
94 compatible = "st,clkgen-c32";
99 compatible = "st,clkgen-pll0";
107 compatible = "st,flexgen";
120 compatible = "st,quadfs-pll";
132 compatible = "st,clkgen-c32";
137 compatible = "st,clkgen-pll0";
146 compatible = "st,clkgen-pll1";
[all …]
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32mp1.txt8 RCC CLOCK = st,stm32mp1-rcc-clk
15 Please refer to ../mfd/st,stm32-rcc.txt for all the other properties common
20 - compatible: Should be "st,stm32mp1-rcc-clk"
22 - st,clksrc : The clock source in this order
30 - st,clkdiv : The div parameters in this order
51 - st,pll
53 with associated index 0 to 3 (st,pll@0 to st,pll@4)
90 - st,pkcs : used to configure the peripherals kernel clock selection
103 compatible = "st,stm32mp1-rcc-clk";
105 st,clksrc = < CLK_MPU_PLL1P
[all …]
H A Dst,stm32h7-rcc.txt11 "st,stm32h743-rcc"
25 - st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
36 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
40 st,syscfg = <&pwrcfg>;
55 st,clock-div = <2>;
56 st,clock-mult = <40>;
57 st,frac-status = <0>;
58 st,frac = <0>;
59 st,vcosel = <1>;
60 st,pllrge = <2>;
[all …]
/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dst,stm32mp1-ddr.txt1 ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
6 - compatible : Should be "st,stm32mp1-ddr"
18 - st,mem-name : name for DDR configuration, simple string for information
19 - st,mem-speed : DDR expected speed for the setting in MHz
20 - st,mem-size : DDR mem size in byte
25 - st,ctl-reg : controleur values depending of the DDR type
54 - st,ctl-timing : controleur values depending of frequency and timing parameter
70 - st,ctl-map : controleur values depending of address mapping
82 - st,ctl-perf : controleur values depending of performance and scheduling
104 - st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
[all …]
H A Dst,stm32-fmc.txt1 ST, stm32 flexible memory controller Drive
3 - compatible : "st,stm32-fmc"
9 - st,sdram-control : parameters for sdram configuration, in this order:
18 - st,sdram-timing: timings for sdram, in this order:
32 compatible = "st,stm32-fmc";
45 st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
47 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
53 st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
55 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
/openbmc/qemu/tests/tcg/i386/
H A Dtest-i386-fisttp.c19 __asm__ volatile ("fisttpl %0" : "=m" (res_32) : "t" (0x1p100L) : "st"); in main()
24 __asm__ volatile ("fisttpl %0" : "=m" (res_32) : "t" (-0x1p100L) : "st"); in main()
30 "st"); in main()
36 "st"); in main()
42 "st"); in main()
48 "t" (-__builtin_nanl("")) : "st"); in main()
54 "st"); in main()
59 __asm__ volatile ("fisttpll %0" : "=m" (res_64) : "t" (0x1p100L) : "st"); in main()
64 __asm__ volatile ("fisttpll %0" : "=m" (res_64) : "t" (-0x1p100L) : "st"); in main()
70 "st"); in main()
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/openbmc/u-boot/doc/device-tree-bindings/adc/
H A Dst,stm32-adc.txt25 "st,stm32f4-adc-core"
26 "st,stm32h7-adc-core"
27 "st,stm32mp1-adc-core"
57 "st,stm32f4-adc"
58 "st,stm32h7-adc"
59 "st,stm32mp1-adc"
66 - st,adc-channels: List of single-ended channels muxed for this ADC.
69 - st,adc-diff-channels: List of differential channels muxed for this ADC.
74 Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is required.
90 - st,min-sample-time-nsecs: Minimum sampling time in nanoseconds.
[all …]
/openbmc/qemu/host/include/i386/host/crypto/
H A Daes-round.h28 aesenc_MC_accel(AESState *ret, const AESState *st, bool be) in aesenc_MC_accel() argument
30 __m128i t = (__m128i)st->v; in aesenc_MC_accel()
46 aesenc_SB_SR_AK_accel(AESState *ret, const AESState *st, in aesenc_SB_SR_AK_accel() argument
49 __m128i t = (__m128i)st->v; in aesenc_SB_SR_AK_accel()
64 aesenc_SB_SR_MC_AK_accel(AESState *ret, const AESState *st, in aesenc_SB_SR_MC_AK_accel() argument
67 __m128i t = (__m128i)st->v; in aesenc_SB_SR_MC_AK_accel()
82 aesdec_IMC_accel(AESState *ret, const AESState *st, bool be) in aesdec_IMC_accel() argument
84 __m128i t = (__m128i)st->v; in aesdec_IMC_accel()
97 aesdec_ISB_ISR_AK_accel(AESState *ret, const AESState *st, in aesdec_ISB_ISR_AK_accel() argument
100 __m128i t = (__m128i)st->v; in aesdec_ISB_ISR_AK_accel()
[all …]
/openbmc/openbmc-test-automation/lib/
H A Dtftp_update_utils.py8 import state as st namespace
14 st.default_req_states plus epoch_seconds.
19 req_states = ["epoch_seconds"] + st.default_req_states
22 state = st.get_state(req_states=req_states, quiet=0)
41 state = st.get_state(req_states=['epoch_seconds'])
46 st.wait_for_comm_cycle(int(start_boot_seconds))
50 st.wait_state(
51 st.standby_match_state, wait_time="10 mins", interval="10 seconds"
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-graphics/suckless/
H A Dst_0.9.2.bb31 ALTERNATIVE:${PN} = "st st-256color"
33 ALTERNATIVE_LINK_NAME[st] = "${datadir}/terminfo/s/st"
35 ALTERNATIVE_LINK_NAME[st-256color] = "${datadir}/terminfo/s/st-256color"
37 … = "cpe-incorrect: The recipe used in the meta-openembedded is a different st package compared to …
/openbmc/qemu/hw/usb/
H A Ddev-uas.c347 UASStatus *st = g_new0(UASStatus, 1); in usb_uas_alloc_status() local
349 st->status.hdr.id = id; in usb_uas_alloc_status()
350 st->status.hdr.tag = cpu_to_be16(tag); in usb_uas_alloc_status()
351 st->length = sizeof(uas_iu_header); in usb_uas_alloc_status()
353 st->stream = tag; in usb_uas_alloc_status()
355 return st; in usb_uas_alloc_status()
361 UASStatus *st; in usb_uas_send_status_bh() local
364 while ((st = QTAILQ_FIRST(&uas->results)) != NULL) { in usb_uas_send_status_bh()
366 p = uas->status3[st->stream]; in usb_uas_send_status_bh()
367 uas->status3[st->stream] = NULL; in usb_uas_send_status_bh()
[all …]

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