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/openbmc/u-boot/drivers/video/
H A Dformike.c4 * LCD initialization via SPI
10 #include <spi.h>
21 static int spi_write_tag_val(struct spi_slave *spi, unsigned char tag, in spi_write_tag_val() argument
29 ret = spi_xfer(spi, 8, buf, NULL, flags); in spi_write_tag_val()
32 ret = spi_xfer(spi, 8, buf, NULL, flags); in spi_write_tag_val()
44 static void spi_write_dat(struct spi_slave *spi, unsigned int val) in spi_write_dat() argument
46 spi_write_tag_val(spi, TAG_WRITE|TAG_DATA, val); in spi_write_dat()
49 static void spi_write_com(struct spi_slave *spi, unsigned int addr) in spi_write_com() argument
51 spi_write_tag_val(spi, TAG_WRITE|TAG_COMMAND|TAG_ADDR_H, in spi_write_com()
53 spi_write_tag_val(spi, TAG_WRITE|TAG_COMMAND|TAG_ADDR_L, in spi_write_com()
[all …]
H A Dlg4573.c4 * LCD initialization via SPI
9 #include <spi.h>
13 static int lb043wv_spi_write_u16(struct spi_slave *spi, u16 val) in lb043wv_spi_write_u16() argument
21 ret = spi_xfer(spi, 16, &buf16, NULL, flags); in lb043wv_spi_write_u16()
28 static void lb043wv_spi_write_u16_array(struct spi_slave *spi, u16 *buff, in lb043wv_spi_write_u16_array() argument
34 lb043wv_spi_write_u16(spi, buff[i]); in lb043wv_spi_write_u16_array()
37 static void lb043wv_display_mode_settings(struct spi_slave *spi) in lb043wv_display_mode_settings() argument
75 lb043wv_spi_write_u16_array(spi, display_mode_settings, in lb043wv_display_mode_settings()
79 static void lb043wv_power_settings(struct spi_slave *spi) in lb043wv_power_settings() argument
106 lb043wv_spi_write_u16_array(spi, power_settings, in lb043wv_power_settings()
[all …]
/openbmc/u-boot/drivers/spi/
H A DKconfig1 menuconfig SPI config
2 bool "SPI Support"
4 if SPI
7 bool "Enable Driver Model for SPI drivers"
10 Enable driver model for SPI. The SPI slave interface
12 the SPI uclass. Drivers provide methods to access the SPI
14 include/spi.h. The existing spi_slave structure is attached
20 bool "SPI memory extension"
22 Enable this option if you want to enable the SPI memory extension.
23 This extension is meant to simplify interaction with SPI memories
[all …]
H A Dmpc8xxx_spi.c10 #include <spi.h>
50 volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi; in spi_init() local
53 * SPI pins on the MPC83xx are not muxed, so all we do is initialize in spi_init()
56 spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN; in spi_init()
57 spi->mode = (spi->mode & 0xfff0ffff) | BIT(16); /* Use SYSCLK / 8 in spi_init()
59 spi->event = 0xffffffff; /* Clear all SPI events */ in spi_init()
60 spi->mask = 0x00000000; /* Mask all SPI interrupts */ in spi_init()
61 spi->com = 0; /* LST bit doesn't do anything, so disregard */ in spi_init()
77 volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi; in spi_xfer() local
89 spi->event = 0xffffffff; /* Clear all SPI events */ in spi_xfer()
[all …]
/openbmc/u-boot/drivers/mtd/spi/
H A DKconfig1 menu "SPI Flash Support"
4 bool "Enable Driver Model for SPI flash"
7 Enable driver model for SPI flash. This SPI flash interface
9 implemented by the SPI flash uclass. There is one standard
10 SPI flash driver which knows how to probe most chips
14 during the transition parent. SPI and SPI flash must be
19 bool "Support sandbox SPI flash device"
23 provided instead. Drivers can be connected up to the sandbox SPI
24 bus (see CONFIG_SANDBOX_SPI) and SPI traffic will be routed to this
25 device. Typically the contents of the emulated SPI flash device is
[all …]
H A Dsf.c3 * SPI flash interface
10 #include <spi.h>
12 static int spi_flash_read_write(struct spi_slave *spi, in spi_flash_read_write() argument
23 ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); in spi_flash_read_write()
28 ret = spi_xfer(spi, data_len * 8, data_out, data_in, in spi_flash_read_write()
38 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, in spi_flash_cmd_read() argument
41 return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len); in spi_flash_cmd_read()
44 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len) in spi_flash_cmd() argument
46 return spi_flash_cmd_read(spi, &cmd, 1, response, len); in spi_flash_cmd()
49 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, in spi_flash_cmd_write() argument
[all …]
H A DMakefile7 spi-nor-y := sf_probe.o spi-nor-ids.o
12 spi-nor-y += spi-nor-tiny.o
14 spi-nor-y += spi-nor-core.o
17 spi-nor-y += spi-nor-core.o
20 obj-$(CONFIG_SPI_FLASH) += spi-nor.o
/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-bus.txt1 SPI (Serial Peripheral Interface) busses
3 SPI busses can be described with a node for the SPI master device
4 and a set of child nodes for each SPI slave on the bus. For this
5 discussion, it is assumed that the system's SPI controller is in
6 SPI master mode. This binding does not describe SPI controllers
9 The SPI master node requires the following properties:
11 address on the SPI bus.
13 - compatible - name of SPI bus controller following generic names
16 No other properties are required in the SPI bus node. It is assumed
17 that a driver for an SPI bus device will understand that it is an SPI bus.
[all …]
H A Dsoft-spi.txt1 Soft SPI
3 The soft SPI bus implementation allows the use of GPIO pins to simulate a
4 SPI bus. No SPI host is required for this to work. The down-side is that the
5 performance will typically be much lower than a real SPI bus.
7 The soft SPI node requires the following properties:
10 compatible: "spi-gpio"
11 cs-gpios: GPIOs to use for SPI chip select (output)
12 gpio-sck: GPIO to use for SPI clock (output)
14 gpio-mosi: GPIO to use for SPI MOSI line (output)
15 gpio-miso: GPIO to use for SPI MISO line (input)
[all …]
H A Dspi-atcspi200.txt1 Andestech ATCSPI200 SPI controller Device Tree Bindings
3 ATCSPI200 is a Serial Peripheral Interface (SPI) controller
4 which serves as a SPI master or a SPI slave.
11 - #address-cells: <1>, as required by generic SPI binding.
12 - #size-cells: <0>, also as required by generic SPI binding.
15 - spi-max-frequency: Maximum SPI clocking speed of device in Hz.
22 spi: spi@f0b00000 {
31 compatible = "spi-flash";
32 spi-max-frequency = <50000000>;
34 spi-cpol;
[all …]
H A Dspi-ath79.txt1 Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
4 - compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
6 - #address-cells: <1>, as required by generic SPI binding.
7 - #size-cells: <0>, also as required by generic SPI binding.
9 Child nodes as per the generic SPI binding.
13 spi@1f000000 {
14 compatible = "qca,ar9132-spi", "qca,ar7100-spi";
H A Dspi-stm32-qspi.txt6 - reg : 1. Physical base address and size of SPI registers map.
8 - spi-max-frequency : Max supported spi frequency.
13 - spi-max-frequency : Max supported spi frequency.
14 - spi-tx-bus-width : Bus width (number of lines) for writing (1-4)
15 - spi-rx-bus-width : Bus width (number of lines) for reading (1-4)
26 spi-max-frequency = <108000000>;
32 compatible = "micron,n25q128a13", "spi-flash";
33 spi-max-frequency = <108000000>;
34 spi-tx-bus-width = <4>;
35 spi-rx-bus-width = <4>;
/openbmc/openbmc/meta-ampere/meta-jefferson/recipes-ampere/platform/ampere-utils/
H A Dampere_flash_bios.sh8 # $device_sellect : 1 - Host Main SPI Nor
9 # 2 - Host Second SPI Nor
14 # BMC_GPIOW6_SPI0_PROGRAM_SEL (GPIO 182): 1 => BMC owns SPI bus for upgrading
15 # 0 => HOST owns SPI bus for upgrading
17 # BMC_GPIOW7_SPI0_BACKUP_SEL (GPIO 183) : 0 => to switch SPI0_CS0_FL1_L to secondary SPI Nor d…
18 # 1 => to switch SPI0_CS0_FL0_L to primary SPI Nor dev…
28 echo 1e630000.spi > /sys/bus/platform/drivers/spi-aspeed-smc/unbind
31 echo 1e630000.spi > /sys/bus/platform/drivers/spi-aspeed-smc/bind
37 echo "Fail to probe the Host SPI-NOR device"
49 echo " DEV_SEL 1 is Primary SPI (by default), 2 is Second SPI"
[all …]
/openbmc/openbmc/meta-ampere/meta-mitchell/recipes-ampere/platform/ampere-utils/
H A Dampere_flash_bios.sh8 # $device_sellect : 1 - Host Main SPI Nor
9 # 2 - Host Second SPI Nor
14 # BMC_GPIOW6_SPI0_PROGRAM_SEL (GPIO 182): 1 => BMC owns SPI bus for upgrading
15 # 0 => HOST owns SPI bus for upgrading
17 # BMC_GPIOW7_SPI0_BACKUP_SEL (GPIO 183) : 1 => to switch SPI_CS0_L to primary SPI Nor device
18 # 0 => to switch SPI_CS0_L to second SPI Nor device
29 echo 1e630000.spi > /sys/bus/platform/drivers/spi-aspeed-smc/unbind
32 echo 1e630000.spi > /sys/bus/platform/drivers/spi-aspeed-smc/bind
38 echo "Fail to probe the Host SPI-NOR device"
50 echo " DEV_SEL 1 is Primary SPI (by default), 2 is Second SPI"
[all …]
/openbmc/u-boot/include/
H A Dspi.h3 * Common SPI Interface: Controller-specific definitions
14 /* SPI mode flags */
46 * struct dm_spi_platdata - platform data for all SPI slaves
48 * This describes a SPI slave, a child device of the SPI bus. To obtain this
57 * @mode: SPI mode to use for this device (see SPI mode flags)
68 * struct spi_slave - Representation of a SPI slave
70 * For driver model this is the per-child data used by the SPI bus. It can
71 * be accessed using dev_get_parent_priv() on the slave device. The SPI uclass
80 * @dev: SPI slave device
85 * driver model this is the sequence number of the SPI
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-ls2080a-qds.dts29 compatible = "spi-flash";
30 spi-max-frequency = <3000000>;
31 spi-cpol;
32 spi-cpha;
38 compatible = "spi-flash";
39 spi-max-frequency = <3000000>;
40 spi-cpol;
41 spi-cpha;
47 compatible = "spi-flash";
48 spi-max-frequency = <3000000>;
[all …]
H A Dast2600-bletchley.dts91 spi-max-frequency = <50000000>;
92 spi-tx-bus-width = <2>;
93 spi-rx-bus-width = <2>;
98 spi-max-frequency = <50000000>;
99 spi-tx-bus-width = <2>;
100 spi-rx-bus-width = <2>;
105 spi-max-frequency = <50000000>;
106 spi-tx-bus-width = <2>;
107 spi-rx-bus-width = <2>;
121 spi-max-frequency = <50000000>;
[all …]
H A Dast2600-gb200nvl-bmc-nvidia.dts70 compatible = "spi-flash", "sst,w25q256";
72 spi-max-frequency = <50000000>;
73 spi-tx-bus-width = <4>;
74 spi-rx-bus-width = <4>;
78 compatible = "spi-flash", "sst,w25q256";
80 spi-max-frequency = <50000000>;
81 spi-tx-bus-width = <4>;
82 spi-rx-bus-width = <4>;
86 compatible = "spi-flash", "sst,w25q256";
88 spi-max-frequency = <50000000>;
[all …]
H A Dfsl-ls1046a-qds.dtsi27 compatible = "spi-flash";
28 spi-max-frequency = <1000000>; /* input clock */
29 spi-cpol;
30 spi-cpha;
37 compatible = "spi-flash";
38 spi-max-frequency = <3500000>;
39 spi-cpol;
40 spi-cpha;
47 compatible = "spi-flash";
48 spi-max-frequency = <3500000>;
[all …]
/openbmc/openbmc/meta-ampere/meta-jade/recipes-ampere/platform/ampere-utils/
H A Dampere_flash_bios.sh24 HOST_SPI=/sys/bus/platform/drivers/spi-aspeed-smc/1e630000.spi
27 echo 1e630000.spi > /sys/bus/platform/drivers/spi-aspeed-smc/unbind
33 echo 1e630000.spi > /sys/bus/platform/drivers/spi-aspeed-smc/bind
39 echo "Fail to probe Host SPI-NOR device"
95 # Switch the host SPI bus to BMC"
96 echo "--- Switch the host SPI bus to BMC."
98 echo "ERROR: Switch the host SPI bus to BMC. Please check gpio state"
102 # Switch the host SPI bus (between primary and secondary)
105 echo "Run update primary Host SPI-NOR"
106 gpioset $(gpiofind spi0-backup-sel)=0 # Primary SPI
[all …]
/openbmc/u-boot/doc/driver-model/
H A DMIGRATION.txt59 drivers/spi/cf_spi.c
60 drivers/spi/fsl_espi.c
61 drivers/spi/lpc32xx_ssp.c
62 drivers/spi/mpc8xx_spi.c
63 drivers/spi/mpc8xxx_spi.c
64 drivers/spi/mxs_spi.c
65 drivers/spi/sh_qspi.c
66 drivers/spi/sh_spi.c
67 drivers/spi/soft_spi_legacy.c
73 drivers/spi/atcspi200_spi.c
[all …]
/openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/flash/phosphor-software-manager/
H A Dbios-update10 # SPI Get Link name
11 SPI_DEV=$(find /sys/bus/spi/devices/ -type l -exec sh -c 'readlink "$1" | grep -q "1e631000.spi" &&…
12 SPI_PATH="/sys/bus/spi/drivers/spi-nor"
17 # bmc-spi-mux-select-0: 1:BMC / 0:CPU
18 set_gpio bmc-spi-mux-select-0 1
25 # bmc-spi-mux-select-0: 1:BMC / 0:CPU
26 set_gpio bmc-spi-mux-select-0 0
58 #Flip GPIO to access SPI flash used by host.
59 echo "Set GPIO $GPIO to access SPI flash from BMC used by host"
62 #Bind spi driver to access flash
[all …]
/openbmc/u-boot/drivers/mmc/
H A Dmmc_spi.c2 * generic mmc spi driver
12 #include <spi.h>
17 /* MMC/SD in SPI mode reports R1 status always */
41 /* MMC SPI commands start with a start bit "0" and a transmit bit "1" */
55 struct spi_slave *spi = mmc->priv; in mmc_spi_sendcmd() local
66 spi_xfer(spi, sizeof(cmdo) * 8, cmdo, NULL, 0); in mmc_spi_sendcmd()
68 spi_xfer(spi, 1 * 8, NULL, &r1, 0); in mmc_spi_sendcmd()
79 struct spi_slave *spi = mmc->priv; in mmc_spi_readdata() local
86 spi_xfer(spi, 1 * 8, NULL, &r1, 0); in mmc_spi_readdata()
92 spi_xfer(spi, bsize * 8, NULL, buf, 0); in mmc_spi_readdata()
[all …]
/openbmc/qemu/include/hw/ssi/
H A Dpnv_spi.h2 * QEMU PowerPC SPI model
8 * This model Supports a connection to a single SPI responder.
9 * Introduced for P10 to provide access to SPI seeproms, TPM, flash device
12 * All SPI function control is mapped into the SPI register space to enable
15 * SPI Controller has sequencer and shift engine. The SPI shift engine
18 * registers and the SPI sequencer implements the main control logic.
28 #define TYPE_PNV_SPI "pnv-spi"
34 #define TYPE_PNV_SPI_BUS "spi"
44 /* SPI object number */
67 /* SPI registers */
/openbmc/u-boot/doc/SPI/
H A Dstatus.txt1 Status on SPI subsystem:
4 SPI COMMAND (common/cmd_sf, cmd_spi):
7 SPI FLASH (drivers/mtd/spi):
8 - sf_probe.c: SPI flash probing code.
9 - sf_ops.c: SPI flash operations code.
10 - sf.c: SPI flash interface, which interacts controller driver.
17 - Dual flash connection topology support(accessing two spi flash memories with single cs)
20 SPI DRIVERS (drivers/spi):

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