xref: /openbmc/qemu/include/hw/ssi/pnv_spi.h (revision b4cb930e)
129318db1SChalapathi V /*
229318db1SChalapathi V  * QEMU PowerPC SPI model
329318db1SChalapathi V  *
429318db1SChalapathi V  * Copyright (c) 2024, IBM Corporation.
529318db1SChalapathi V  *
629318db1SChalapathi V  * SPDX-License-Identifier: GPL-2.0-or-later
729318db1SChalapathi V  *
829318db1SChalapathi V  * This model Supports a connection to a single SPI responder.
929318db1SChalapathi V  * Introduced for P10 to provide access to SPI seeproms, TPM, flash device
1029318db1SChalapathi V  * and an ADC controller.
11*b4cb930eSChalapathi V  *
12*b4cb930eSChalapathi V  * All SPI function control is mapped into the SPI register space to enable
13*b4cb930eSChalapathi V  * full control by firmware.
14*b4cb930eSChalapathi V  *
15*b4cb930eSChalapathi V  * SPI Controller has sequencer and shift engine. The SPI shift engine
16*b4cb930eSChalapathi V  * performs serialization and de-serialization according to the control by
17*b4cb930eSChalapathi V  * the sequencer and according to the setup defined in the configuration
18*b4cb930eSChalapathi V  * registers and the SPI sequencer implements the main control logic.
1929318db1SChalapathi V  */
2029318db1SChalapathi V 
2129318db1SChalapathi V #ifndef PPC_PNV_SPI_H
2229318db1SChalapathi V #define PPC_PNV_SPI_H
2329318db1SChalapathi V 
2429318db1SChalapathi V #include "hw/ssi/ssi.h"
2529318db1SChalapathi V #include "hw/sysbus.h"
2629318db1SChalapathi V 
2729318db1SChalapathi V #define TYPE_PNV_SPI "pnv-spi"
2829318db1SChalapathi V OBJECT_DECLARE_SIMPLE_TYPE(PnvSpi, PNV_SPI)
2929318db1SChalapathi V 
3029318db1SChalapathi V #define PNV_SPI_REG_SIZE 8
3129318db1SChalapathi V #define PNV_SPI_REGS 7
3229318db1SChalapathi V 
3329318db1SChalapathi V #define TYPE_PNV_SPI_BUS "pnv-spi-bus"
3429318db1SChalapathi V typedef struct PnvSpi {
3529318db1SChalapathi V     SysBusDevice parent_obj;
3629318db1SChalapathi V 
3729318db1SChalapathi V     SSIBus *ssi_bus;
3829318db1SChalapathi V     qemu_irq *cs_line;
3929318db1SChalapathi V     MemoryRegion    xscom_spic_regs;
4029318db1SChalapathi V     /* SPI object number */
4129318db1SChalapathi V     uint32_t        spic_num;
42*b4cb930eSChalapathi V     uint8_t         transfer_len;
43*b4cb930eSChalapathi V     uint8_t         responder_select;
44*b4cb930eSChalapathi V     /* To verify if shift_n1 happens prior to shift_n2 */
45*b4cb930eSChalapathi V     bool            shift_n1_done;
46*b4cb930eSChalapathi V     /* Loop counter for branch operation opcode Ex/Fx */
47*b4cb930eSChalapathi V     uint8_t         loop_counter_1;
48*b4cb930eSChalapathi V     uint8_t         loop_counter_2;
49*b4cb930eSChalapathi V     /* N1/N2_bits specifies the size of the N1/N2 segment of a frame in bits.*/
50*b4cb930eSChalapathi V     uint8_t         N1_bits;
51*b4cb930eSChalapathi V     uint8_t         N2_bits;
52*b4cb930eSChalapathi V     /* Number of bytes in a payload for the N1/N2 frame segment.*/
53*b4cb930eSChalapathi V     uint8_t         N1_bytes;
54*b4cb930eSChalapathi V     uint8_t         N2_bytes;
55*b4cb930eSChalapathi V     /* Number of N1/N2 bytes marked for transmit */
56*b4cb930eSChalapathi V     uint8_t         N1_tx;
57*b4cb930eSChalapathi V     uint8_t         N2_tx;
58*b4cb930eSChalapathi V     /* Number of N1/N2 bytes marked for receive */
59*b4cb930eSChalapathi V     uint8_t         N1_rx;
60*b4cb930eSChalapathi V     uint8_t         N2_rx;
6129318db1SChalapathi V 
6229318db1SChalapathi V     /* SPI registers */
6329318db1SChalapathi V     uint64_t        regs[PNV_SPI_REGS];
6429318db1SChalapathi V     uint8_t         seq_op[PNV_SPI_REG_SIZE];
6529318db1SChalapathi V     uint64_t        status;
6629318db1SChalapathi V } PnvSpi;
6729318db1SChalapathi V #endif /* PPC_PNV_SPI_H */
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