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/openbmc/linux/arch/arm64/crypto/
H A Dsm4-ce-asm.h12 sm4e b0.4s, v24.4s; \
13 sm4e b0.4s, v25.4s; \
14 sm4e b0.4s, v26.4s; \
15 sm4e b0.4s, v27.4s; \
16 sm4e b0.4s, v28.4s; \
17 sm4e b0.4s, v29.4s; \
18 sm4e b0.4s, v30.4s; \
19 sm4e b0.4s, v31.4s; \
20 rev64 b0.4s, b0.4s; \
29 sm4e b0.4s, v24.4s; \
[all …]
/openbmc/linux/arch/m68k/ifpsp060/
H A DMISC34 freal.s : 2.4
36 x_fovfl.s : 2.16
37 x_funfl.s : 2.19
38 x_funsupp.s : 2.27
39 x_effadd.s : 2.21
40 x_foperr.s : 2.9
41 x_fsnan.s : 2.12
42 x_finex.s : 2.14
43 x_fdz.s : 2.5
44 x_fline.s : 2.5
[all …]
/openbmc/qemu/hw/scsi/
H A Desp.c46 static void esp_raise_irq(ESPState *s) in esp_raise_irq() argument
48 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { in esp_raise_irq()
49 s->rregs[ESP_RSTAT] |= STAT_INT; in esp_raise_irq()
50 qemu_irq_raise(s->irq); in esp_raise_irq()
55 static void esp_lower_irq(ESPState *s) in esp_lower_irq() argument
57 if (s->rregs[ESP_RSTAT] & STAT_INT) { in esp_lower_irq()
58 s->rregs[ESP_RSTAT] &= ~STAT_INT; in esp_lower_irq()
59 qemu_irq_lower(s->irq); in esp_lower_irq()
64 static void esp_raise_drq(ESPState *s) in esp_raise_drq() argument
66 if (!(s->drq_state)) { in esp_raise_drq()
[all …]
H A Dlsi53c895a.c332 static inline int lsi_irq_on_rsl(LSIState *s) in lsi_irq_on_rsl() argument
334 return (s->sien0 & LSI_SIST0_RSL) && (s->scid & LSI_SCID_RRE); in lsi_irq_on_rsl()
337 static lsi_request *get_pending_req(LSIState *s) in get_pending_req() argument
341 QTAILQ_FOREACH(p, &s->queue, next) { in get_pending_req()
349 static void lsi_soft_reset(LSIState *s) in lsi_soft_reset() argument
352 s->carry = 0; in lsi_soft_reset()
354 s->msg_action = LSI_MSG_ACTION_COMMAND; in lsi_soft_reset()
355 s->msg_len = 0; in lsi_soft_reset()
356 s->waiting = LSI_NOWAIT; in lsi_soft_reset()
357 s->dsa = 0; in lsi_soft_reset()
[all …]
/openbmc/qemu/scripts/
H A Dmeson-buildoptions.sh3 printf "%s\n" ' --audio-drv-list=CHOICES Set audio driver list [default] (choices: alsa/co'
4 printf "%s\n" ' reaudio/default/dsound/jack/oss/pa/pipewire/sdl/s'
5 printf "%s\n" ' ndio)'
6 printf "%s\n" ' --bindir=VALUE Executable directory [bin]'
7 printf "%s\n" ' --block-drv-ro-whitelist=VALUE'
8 printf "%s\n" ' set block driver read-only whitelist (by default'
9 printf "%s\n" ' affects only QEMU, not tools like qemu-img)'
10 printf "%s\n" ' --block-drv-rw-whitelist=VALUE'
11 printf "%s\n" ' set block driver read-write whitelist (by default'
12 printf "%s\n" ' affects only QEMU, not tools like qemu-img)'
[all …]
/openbmc/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-interrupt-decodes.c60 /* Skipping gmx_rx_int_en.s.reserved_29_63 */ in __cvmx_interrupt_gmxx_rxx_int_en_enable()
61 gmx_rx_int_en.s.hg2cc = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
62 gmx_rx_int_en.s.hg2fld = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
63 gmx_rx_int_en.s.undat = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
64 gmx_rx_int_en.s.uneop = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
65 gmx_rx_int_en.s.unsop = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
66 gmx_rx_int_en.s.bad_term = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
67 gmx_rx_int_en.s.bad_seq = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
68 gmx_rx_int_en.s.rem_fault = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
69 gmx_rx_int_en.s.loc_fault = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
[all …]
/openbmc/qemu/hw/audio/
H A Dsb16.c160 ldebug ("%s:%s:%d:%s:dmasize=%d:freq=%d:const=%d:speaker=%d\n",
172 static void speaker (SB16State *s, int on) in speaker() argument
174 s->speaker = on; in speaker()
175 /* AUD_enable (s->voice, on); */ in speaker()
178 static void control (SB16State *s, int hold) in control() argument
180 int dma = s->use_hdma ? s->hdma : s->dma; in control()
181 IsaDma *isa_dma = s->use_hdma ? s->isa_hdma : s->isa_dma; in control()
183 s->dma_running = hold; in control()
185 ldebug ("hold %d high %d dma %d\n", hold, s->use_hdma, dma); in control()
189 AUD_set_active_out (s->voice, 1); in control()
[all …]
H A Dwm8750.c70 static inline void wm8750_in_load(WM8750State *s) in wm8750_in_load() argument
72 if (s->idx_in + s->req_in <= sizeof(s->data_in)) in wm8750_in_load()
74 s->idx_in = MAX(0, (int) sizeof(s->data_in) - s->req_in); in wm8750_in_load()
75 AUD_read(*s->in[0], s->data_in + s->idx_in, in wm8750_in_load()
76 sizeof(s->data_in) - s->idx_in); in wm8750_in_load()
79 static inline void wm8750_out_flush(WM8750State *s) in wm8750_out_flush() argument
82 while (sent < s->idx_out) in wm8750_out_flush()
83 sent += AUD_write(*s->out[0], s->data_out + sent, s->idx_out - sent) in wm8750_out_flush()
84 ?: s->idx_out; in wm8750_out_flush()
85 s->idx_out = 0; in wm8750_out_flush()
[all …]
/openbmc/qemu/hw/i2c/
H A Dnpcm7xx_smbus.c164 #define NPCM7XX_SMBUS_ENABLED(s) ((s)->ctl2 & NPCM7XX_SMBCTL2_ENABLE) argument
165 #define NPCM7XX_SMBUS_FIFO_ENABLED(s) ((s)->fif_ctl & \ argument
200 static void npcm7xx_smbus_update_irq(NPCM7xxSMBusState *s) in npcm7xx_smbus_update_irq() argument
204 if (s->ctl1 & NPCM7XX_SMBCTL1_INTEN) { in npcm7xx_smbus_update_irq()
205 level = !!((s->ctl1 & NPCM7XX_SMBCTL1_NMINTE && in npcm7xx_smbus_update_irq()
206 s->st & NPCM7XX_SMBST_NMATCH) || in npcm7xx_smbus_update_irq()
207 (s->st & NPCM7XX_SMBST_BER) || in npcm7xx_smbus_update_irq()
208 (s->st & NPCM7XX_SMBST_NEGACK) || in npcm7xx_smbus_update_irq()
209 (s->st & NPCM7XX_SMBST_SDAST) || in npcm7xx_smbus_update_irq()
210 (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE && in npcm7xx_smbus_update_irq()
[all …]
H A Dpm_smbus.c68 static void smb_transaction(PMSMBus *s) in smb_transaction() argument
70 uint8_t prot = (s->smb_ctl >> 2) & 0x07; in smb_transaction()
71 uint8_t read = s->smb_addr & 0x01; in smb_transaction()
72 uint8_t cmd = s->smb_cmd; in smb_transaction()
73 uint8_t addr = s->smb_addr >> 1; in smb_transaction()
74 I2CBus *bus = s->smbus; in smb_transaction()
79 if ((s->smb_stat & STS_DEV_ERR) != 0) { in smb_transaction()
100 ret = smbus_write_byte(bus, addr, cmd, s->smb_data0); in smb_transaction()
110 (s->smb_data1 << 8) | s->smb_data0); in smb_transaction()
126 ret = i2c_send(bus, s->smb_data1); in smb_transaction()
[all …]
/openbmc/qemu/hw/net/
H A Dlan9118.c344 static void lan9118_update(lan9118_state *s) in lan9118_update() argument
349 level = (s->int_sts & s->int_en) != 0; in lan9118_update()
351 s->irq_cfg |= IRQ_INT; in lan9118_update()
353 s->irq_cfg &= ~IRQ_INT; in lan9118_update()
355 if ((s->irq_cfg & IRQ_EN) == 0) { in lan9118_update()
358 if ((s->irq_cfg & (IRQ_TYPE | IRQ_POL)) != (IRQ_TYPE | IRQ_POL)) { in lan9118_update()
364 qemu_set_irq(s->irq, level); in lan9118_update()
367 static void lan9118_mac_changed(lan9118_state *s) in lan9118_mac_changed() argument
369 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); in lan9118_mac_changed()
372 static void lan9118_reload_eeprom(lan9118_state *s) in lan9118_reload_eeprom() argument
[all …]
H A Ddp8393x.c150 static uint32_t dp8393x_cdp(dp8393xState *s) in dp8393x_cdp() argument
152 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP]; in dp8393x_cdp()
155 static uint32_t dp8393x_crba(dp8393xState *s) in dp8393x_crba() argument
157 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]; in dp8393x_crba()
160 static uint32_t dp8393x_crda(dp8393xState *s) in dp8393x_crda() argument
162 return (s->regs[SONIC_URDA] << 16) | in dp8393x_crda()
163 (s->regs[SONIC_CRDA] & SONIC_DESC_ADDR); in dp8393x_crda()
166 static uint32_t dp8393x_rbwc(dp8393xState *s) in dp8393x_rbwc() argument
168 return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]; in dp8393x_rbwc()
171 static uint32_t dp8393x_rrp(dp8393xState *s) in dp8393x_rrp() argument
[all …]
H A Dpcnet.c65 #define CSR_INIT(S) !!(((S)->csr[0])&0x0001) argument
66 #define CSR_STRT(S) !!(((S)->csr[0])&0x0002) argument
67 #define CSR_STOP(S) !!(((S)->csr[0])&0x0004) argument
68 #define CSR_TDMD(S) !!(((S)->csr[0])&0x0008) argument
69 #define CSR_TXON(S) !!(((S)->csr[0])&0x0010) argument
70 #define CSR_RXON(S) !!(((S)->csr[0])&0x0020) argument
71 #define CSR_INEA(S) !!(((S)->csr[0])&0x0040) argument
72 #define CSR_BSWP(S) !!(((S)->csr[3])&0x0004) argument
73 #define CSR_LAPPEN(S) !!(((S)->csr[3])&0x0020) argument
74 #define CSR_DXSUFLO(S) !!(((S)->csr[3])&0x0040) argument
[all …]
/openbmc/qemu/tests/qtest/
H A Dam53c974-test.c17 QTestState *s = qtest_init( in test_cmdfifo_underflow_ok() local
21 qtest_outl(s, 0xcf8, 0x80001004); in test_cmdfifo_underflow_ok()
22 qtest_outw(s, 0xcfc, 0x01); in test_cmdfifo_underflow_ok()
23 qtest_outl(s, 0xcf8, 0x8000100e); in test_cmdfifo_underflow_ok()
24 qtest_outl(s, 0xcfc, 0x8a000000); in test_cmdfifo_underflow_ok()
25 qtest_outl(s, 0x8a09, 0x42000000); in test_cmdfifo_underflow_ok()
26 qtest_outl(s, 0x8a0d, 0x00); in test_cmdfifo_underflow_ok()
27 qtest_outl(s, 0x8a0b, 0x1000); in test_cmdfifo_underflow_ok()
28 qtest_quit(s); in test_cmdfifo_underflow_ok()
34 QTestState *s = qtest_init( in test_cmdfifo_underflow2_ok() local
[all …]
/openbmc/qemu/hw/ide/
H A Dcore.c82 static void ide_dummy_transfer_stop(IDEState *s);
113 static void ide_identify_size(IDEState *s) in ide_identify_size() argument
115 uint16_t *p = (uint16_t *)s->identify_data; in ide_identify_size()
116 int64_t nb_sectors_lba28 = s->nb_sectors; in ide_identify_size()
122 put_le16(p + 100, s->nb_sectors); in ide_identify_size()
123 put_le16(p + 101, s->nb_sectors >> 16); in ide_identify_size()
124 put_le16(p + 102, s->nb_sectors >> 32); in ide_identify_size()
125 put_le16(p + 103, s->nb_sectors >> 48); in ide_identify_size()
128 static void ide_identify(IDEState *s) in ide_identify() argument
132 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master; in ide_identify()
[all …]
/openbmc/qemu/hw/arm/
H A Dstrongarm.c108 StrongARMPICState *s = opaque; in strongarm_pic_update() local
111 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq); in strongarm_pic_update()
112 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq); in strongarm_pic_update()
117 StrongARMPICState *s = opaque; in strongarm_pic_set_irq() local
120 s->pending |= 1 << irq; in strongarm_pic_set_irq()
122 s->pending &= ~(1 << irq); in strongarm_pic_set_irq()
125 strongarm_pic_update(s); in strongarm_pic_set_irq()
131 StrongARMPICState *s = opaque; in strongarm_pic_mem_read() local
135 return s->pending & ~s->is_fiq & s->enabled; in strongarm_pic_mem_read()
137 return s->enabled; in strongarm_pic_mem_read()
[all …]
H A Domap1.c47 qemu_log_mask(LOG_GUEST_ERROR, "%s: %d-bit register %#08" HWADDR_PRIx "\n", in omap_log_badwidth()
206 struct omap_mpu_timer_s *s = opaque; in omap_mpu_timer_read() local
214 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; in omap_mpu_timer_read()
220 return omap_timer_read(s); in omap_mpu_timer_read()
230 struct omap_mpu_timer_s *s = opaque; in omap_mpu_timer_write() local
239 omap_timer_sync(s); in omap_mpu_timer_write()
240 s->enable = (value >> 5) & 1; in omap_mpu_timer_write()
241 s->ptv = (value >> 2) & 7; in omap_mpu_timer_write()
242 s->ar = (value >> 1) & 1; in omap_mpu_timer_write()
243 s->st = value & 1; in omap_mpu_timer_write()
[all …]
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvvk.c.inc25 static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
27 if (CHECK(s, a)) { \
29 gen_helper_##NAME, s); \
34 static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a)
36 return opivv_check(s, a) &&
37 s->cfg_ptr->ext_zvbc == true &&
38 s->sew == MO_64;
45 static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
47 if (CHECK(s, a)) { \
49 gen_helper_##NAME, s); \
[all …]
/openbmc/qemu/hw/char/
H A Dserial.c106 static void serial_xmit(SerialState *s);
108 static inline void recv_fifo_put(SerialState *s, uint8_t chr) in recv_fifo_put() argument
111 if (!fifo8_is_full(&s->recv_fifo)) { in recv_fifo_put()
112 fifo8_push(&s->recv_fifo, chr); in recv_fifo_put()
114 s->lsr |= UART_LSR_OE; in recv_fifo_put()
118 static void serial_update_irq(SerialState *s) in serial_update_irq() argument
122 if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) { in serial_update_irq()
124 } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) { in serial_update_irq()
125 /* Note that(s->ier & UART_IER_RDI) can mask this interrupt, in serial_update_irq()
129 } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) && in serial_update_irq()
[all …]
/openbmc/qemu/hw/sd/
H A Dsdhci.c50 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) in DECLARE_INSTANCE_CHECKER()
52 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); in DECLARE_INSTANCE_CHECKER()
56 static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, in sdhci_check_capab_freq_range() argument
59 if (s->sd_spec_version >= 3) { in sdhci_check_capab_freq_range()
67 error_setg(errp, "SD %s clock frequency can have value" in sdhci_check_capab_freq_range()
74 static void sdhci_check_capareg(SDHCIState *s, Error **errp) in sdhci_check_capareg() argument
76 uint64_t msk = s->capareg; in sdhci_check_capareg()
80 switch (s->sd_spec_version) { in sdhci_check_capareg()
82 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); in sdhci_check_capareg()
86 val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); in sdhci_check_capareg()
[all …]
/openbmc/qemu/target/i386/tcg/
H A Dtranslate.c104 uint8_t vex_v; /* vex vvvv register, without 1's complement. */
180 #define PE(S) true argument
181 #define CPL(S) 3 argument
182 #define IOPL(S) 0 argument
183 #define SVME(S) false argument
184 #define GUEST(S) false argument
186 #define PE(S) (((S)->flags & HF_PE_MASK) != 0) argument
187 #define CPL(S) ((S)->cpl) argument
188 #define IOPL(S) ((S)->iopl) argument
189 #define SVME(S) (((S)->flags & HF_SVME_MASK) != 0) argument
[all …]
H A Demit.c.inc68 static void gen_JMP_m(DisasContext *s, X86DecodedInsn *decode);
69 static void gen_JMP(DisasContext *s, X86DecodedInsn *decode);
76 static void gen_NM_exception(DisasContext *s)
78 gen_exception(s, EXCP07_PREX);
81 static void gen_lea_modrm(DisasContext *s, X86DecodedInsn *decode)
86 ea = gen_lea_modrm_1(s, *mem, decode->e.vex_class == 12);
97 tcg_gen_add_tl(s->A0, ea, ofs);
98 ea = s->A0;
101 gen_lea_v_seg(s, ea, mem->def_seg, s->override);
208 static void gen_load_sse(DisasContext *s, TCGv temp, MemOp ot, int dest_ofs, bool aligned)
[all …]
/openbmc/qemu/hw/net/can/
H A Dctucan_core.c66 frame->can_dlc = can_dlc2len(frame_form_w.s.dlc); in ctucan_buff2frame()
71 ide = frame_form_w.s.ide; in ctucan_buff2frame()
73 frame->can_id = (identifier_w.s.identifier_base << 18) | in ctucan_buff2frame()
74 identifier_w.s.identifier_ext; in ctucan_buff2frame()
77 frame->can_id = identifier_w.s.identifier_base; in ctucan_buff2frame()
80 if (frame_form_w.s.esi_rsv) { in ctucan_buff2frame()
84 if (frame_form_w.s.rtr) { in ctucan_buff2frame()
88 if (frame_form_w.s.fdf) { /*CAN FD*/ in ctucan_buff2frame()
90 if (frame_form_w.s.brs) { in ctucan_buff2frame()
118 frame_form_w.s.rwcnt = (bytes_cnt >> 2) - 1; in ctucan_frame2buff()
[all …]
/openbmc/qemu/hw/timer/
H A Dnrf51_timer.c28 static uint32_t ns_to_ticks(NRF51TimerState *s, int64_t ns) in ns_to_ticks() argument
30 uint32_t freq = TIMER_CLK_FREQ >> s->prescaler; in ns_to_ticks()
35 static int64_t ticks_to_ns(NRF51TimerState *s, uint32_t ticks) in ticks_to_ns() argument
37 uint32_t freq = TIMER_CLK_FREQ >> s->prescaler; in ticks_to_ns()
43 static uint32_t update_counter(NRF51TimerState *s, int64_t now) in update_counter() argument
45 uint32_t ticks = ns_to_ticks(s, now - s->update_counter_ns); in update_counter()
47 s->counter = (s->counter + ticks) % BIT(bitwidths[s->bitmode]); in update_counter()
53 s->update_counter_ns += ticks_to_ns(s, ticks); in update_counter()
57 /* Assumes s->counter is up-to-date */
58 static void rearm_timer(NRF51TimerState *s, int64_t now) in rearm_timer() argument
[all …]
/openbmc/qemu/hw/misc/
H A Dmos6522.c49 static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti,
51 static void mos6522_timer2_update(MOS6522State *s, MOS6522Timer *ti,
54 static void mos6522_update_irq(MOS6522State *s) in mos6522_update_irq() argument
56 if (s->ifr & s->ier) { in mos6522_update_irq()
57 qemu_irq_raise(s->irq); in mos6522_update_irq()
59 qemu_irq_lower(s->irq); in mos6522_update_irq()
65 MOS6522State *s = MOS6522(opaque); in mos6522_set_irq() local
66 int last_level = !!(s->last_irq_levels & (1 << n)); in mos6522_set_irq()
67 uint8_t last_ifr = s->ifr; in mos6522_set_irq()
87 ctrl = (s->pcr & CA2_CTRL_MASK) >> CA2_CTRL_SHIFT; in mos6522_set_irq()
[all …]

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