Lines Matching full:s
50 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) in DECLARE_INSTANCE_CHECKER()
52 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); in DECLARE_INSTANCE_CHECKER()
56 static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, in sdhci_check_capab_freq_range() argument
59 if (s->sd_spec_version >= 3) { in sdhci_check_capab_freq_range()
67 error_setg(errp, "SD %s clock frequency can have value" in sdhci_check_capab_freq_range()
74 static void sdhci_check_capareg(SDHCIState *s, Error **errp) in sdhci_check_capareg() argument
76 uint64_t msk = s->capareg; in sdhci_check_capareg()
80 switch (s->sd_spec_version) { in sdhci_check_capareg()
82 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); in sdhci_check_capareg()
86 val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); in sdhci_check_capareg()
90 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3); in sdhci_check_capareg()
96 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); in sdhci_check_capareg()
100 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); in sdhci_check_capareg()
109 val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); in sdhci_check_capareg()
114 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); in sdhci_check_capareg()
118 val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); in sdhci_check_capareg()
122 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); in sdhci_check_capareg()
126 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); in sdhci_check_capareg()
130 val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); in sdhci_check_capareg()
134 val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); in sdhci_check_capareg()
140 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); in sdhci_check_capareg()
144 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1); in sdhci_check_capareg()
148 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); in sdhci_check_capareg()
154 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); in sdhci_check_capareg()
157 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); in sdhci_check_capareg()
159 if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) { in sdhci_check_capareg()
164 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); in sdhci_check_capareg()
166 if (sdhci_check_capab_freq_range(s, "base", val, errp)) { in sdhci_check_capareg()
171 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); in sdhci_check_capareg()
176 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s)); in sdhci_check_capareg()
179 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); in sdhci_check_capareg()
183 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); in sdhci_check_capareg()
187 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); in sdhci_check_capareg()
191 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33); in sdhci_check_capareg()
195 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30); in sdhci_check_capareg()
199 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18); in sdhci_check_capareg()
205 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version); in sdhci_check_capareg()
213 static uint8_t sdhci_slotint(SDHCIState *s) in sdhci_slotint() argument
215 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || in sdhci_slotint()
216 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || in sdhci_slotint()
217 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); in sdhci_slotint()
221 static bool sdhci_update_irq(SDHCIState *s) in sdhci_update_irq() argument
223 bool pending = sdhci_slotint(s); in sdhci_update_irq()
225 qemu_set_irq(s->irq, pending); in sdhci_update_irq()
232 SDHCIState *s = (SDHCIState *)opaque; in sdhci_raise_insertion_irq() local
234 if (s->norintsts & SDHC_NIS_REMOVE) { in sdhci_raise_insertion_irq()
235 timer_mod(s->insert_timer, in sdhci_raise_insertion_irq()
238 s->prnsts = 0x1ff0000; in sdhci_raise_insertion_irq()
239 if (s->norintstsen & SDHC_NISEN_INSERT) { in sdhci_raise_insertion_irq()
240 s->norintsts |= SDHC_NIS_INSERT; in sdhci_raise_insertion_irq()
242 sdhci_update_irq(s); in sdhci_raise_insertion_irq()
248 SDHCIState *s = (SDHCIState *)dev; in sdhci_set_inserted() local
251 if ((s->norintsts & SDHC_NIS_REMOVE) && level) { in sdhci_set_inserted()
253 timer_mod(s->insert_timer, in sdhci_set_inserted()
257 s->prnsts = 0x1ff0000; in sdhci_set_inserted()
258 if (s->norintstsen & SDHC_NISEN_INSERT) { in sdhci_set_inserted()
259 s->norintsts |= SDHC_NIS_INSERT; in sdhci_set_inserted()
262 s->prnsts = 0x1fa0000; in sdhci_set_inserted()
263 s->pwrcon &= ~SDHC_POWER_ON; in sdhci_set_inserted()
264 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; in sdhci_set_inserted()
265 if (s->norintstsen & SDHC_NISEN_REMOVE) { in sdhci_set_inserted()
266 s->norintsts |= SDHC_NIS_REMOVE; in sdhci_set_inserted()
269 sdhci_update_irq(s); in sdhci_set_inserted()
275 SDHCIState *s = (SDHCIState *)dev; in sdhci_set_readonly() local
277 if (s->wp_inverted) { in sdhci_set_readonly()
282 s->prnsts &= ~SDHC_WRITE_PROTECT; in sdhci_set_readonly()
285 s->prnsts |= SDHC_WRITE_PROTECT; in sdhci_set_readonly()
289 static void sdhci_reset(SDHCIState *s) in sdhci_reset() argument
291 DeviceState *dev = DEVICE(s); in sdhci_reset()
293 timer_del(s->insert_timer); in sdhci_reset()
294 timer_del(s->transfer_timer); in sdhci_reset()
301 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); in sdhci_reset()
304 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); in sdhci_reset()
305 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); in sdhci_reset()
307 s->data_count = 0; in sdhci_reset()
308 s->stopped_state = sdhc_not_stopped; in sdhci_reset()
309 s->pending_insert_state = false; in sdhci_reset()
319 SDHCIState *s = (SDHCIState *)dev; in sdhci_poweron_reset() local
321 sdhci_reset(s); in sdhci_poweron_reset()
323 if (s->pending_insert_quirk) { in sdhci_poweron_reset()
324 s->pending_insert_state = true; in sdhci_poweron_reset()
332 static void sdhci_send_command(SDHCIState *s) in sdhci_send_command() argument
339 s->errintsts = 0; in sdhci_send_command()
340 s->acmd12errsts = 0; in sdhci_send_command()
341 request.cmd = s->cmdreg >> 8; in sdhci_send_command()
342 request.arg = s->argument; in sdhci_send_command()
345 rlen = sdbus_do_command(&s->sdbus, &request, response); in sdhci_send_command()
347 if (s->cmdreg & SDHC_CMD_RESPONSE) { in sdhci_send_command()
349 s->rspreg[0] = ldl_be_p(response); in sdhci_send_command()
350 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; in sdhci_send_command()
351 trace_sdhci_response4(s->rspreg[0]); in sdhci_send_command()
353 s->rspreg[0] = ldl_be_p(&response[11]); in sdhci_send_command()
354 s->rspreg[1] = ldl_be_p(&response[7]); in sdhci_send_command()
355 s->rspreg[2] = ldl_be_p(&response[3]); in sdhci_send_command()
356 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | in sdhci_send_command()
358 trace_sdhci_response16(s->rspreg[3], s->rspreg[2], in sdhci_send_command()
359 s->rspreg[1], s->rspreg[0]); in sdhci_send_command()
363 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { in sdhci_send_command()
364 s->errintsts |= SDHC_EIS_CMDTIMEOUT; in sdhci_send_command()
365 s->norintsts |= SDHC_NIS_ERR; in sdhci_send_command()
369 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && in sdhci_send_command()
370 (s->norintstsen & SDHC_NISEN_TRSCMP) && in sdhci_send_command()
371 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { in sdhci_send_command()
372 s->norintsts |= SDHC_NIS_TRSCMP; in sdhci_send_command()
376 if (s->norintstsen & SDHC_NISEN_CMDCMP) { in sdhci_send_command()
377 s->norintsts |= SDHC_NIS_CMDCMP; in sdhci_send_command()
380 sdhci_update_irq(s); in sdhci_send_command()
382 if (!timeout && (s->blksize & BLOCK_SIZE_MASK) && in sdhci_send_command()
383 (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { in sdhci_send_command()
384 s->data_count = 0; in sdhci_send_command()
385 sdhci_data_transfer(s); in sdhci_send_command()
389 static void sdhci_end_transfer(SDHCIState *s) in sdhci_end_transfer() argument
392 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { in sdhci_end_transfer()
399 sdbus_do_command(&s->sdbus, &request, response); in sdhci_end_transfer()
401 s->rspreg[3] = ldl_be_p(response); in sdhci_end_transfer()
404 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | in sdhci_end_transfer()
408 if (s->norintstsen & SDHC_NISEN_TRSCMP) { in sdhci_end_transfer()
409 s->norintsts |= SDHC_NIS_TRSCMP; in sdhci_end_transfer()
412 sdhci_update_irq(s); in sdhci_end_transfer()
419 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */
420 static void sdhci_read_block_from_card(SDHCIState *s) in sdhci_read_block_from_card() argument
422 const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK; in sdhci_read_block_from_card()
424 if ((s->trnmod & SDHC_TRNS_MULTI) && in sdhci_read_block_from_card()
425 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { in sdhci_read_block_from_card()
429 if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { in sdhci_read_block_from_card()
431 sdbus_read_data(&s->sdbus, s->fifo_buffer, blk_size); in sdhci_read_block_from_card()
434 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { in sdhci_read_block_from_card()
436 s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK; in sdhci_read_block_from_card()
437 s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK; in sdhci_read_block_from_card()
438 s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ | in sdhci_read_block_from_card()
444 s->prnsts |= SDHC_DATA_AVAILABLE; in sdhci_read_block_from_card()
445 if (s->norintstsen & SDHC_NISEN_RBUFRDY) { in sdhci_read_block_from_card()
446 s->norintsts |= SDHC_NIS_RBUFRDY; in sdhci_read_block_from_card()
450 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || in sdhci_read_block_from_card()
451 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { in sdhci_read_block_from_card()
452 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; in sdhci_read_block_from_card()
456 * If stop at block gap request was set and it's not the last block of in sdhci_read_block_from_card()
459 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && in sdhci_read_block_from_card()
460 s->blkcnt != 1) { in sdhci_read_block_from_card()
461 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; in sdhci_read_block_from_card()
462 if (s->norintstsen & SDHC_EISEN_BLKGAP) { in sdhci_read_block_from_card()
463 s->norintsts |= SDHC_EIS_BLKGAP; in sdhci_read_block_from_card()
468 sdhci_update_irq(s); in sdhci_read_block_from_card()
471 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */
472 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) in sdhci_read_dataport() argument
478 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { in sdhci_read_dataport()
484 assert(s->data_count < s->buf_maxsz); in sdhci_read_dataport()
485 value |= s->fifo_buffer[s->data_count] << i * 8; in sdhci_read_dataport()
486 s->data_count++; in sdhci_read_dataport()
488 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) { in sdhci_read_dataport()
489 trace_sdhci_read_dataport(s->data_count); in sdhci_read_dataport()
490 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ in sdhci_read_dataport()
491 s->data_count = 0; /* next buff read must start at position [0] */ in sdhci_read_dataport()
493 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { in sdhci_read_dataport()
494 s->blkcnt--; in sdhci_read_dataport()
498 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || in sdhci_read_dataport()
499 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || in sdhci_read_dataport()
501 (s->stopped_state == sdhc_gap_read && in sdhci_read_dataport()
502 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { in sdhci_read_dataport()
503 sdhci_end_transfer(s); in sdhci_read_dataport()
505 sdhci_read_block_from_card(s); in sdhci_read_dataport()
515 static void sdhci_write_block_to_card(SDHCIState *s) in sdhci_write_block_to_card() argument
517 if (s->prnsts & SDHC_SPACE_AVAILABLE) { in sdhci_write_block_to_card()
518 if (s->norintstsen & SDHC_NISEN_WBUFRDY) { in sdhci_write_block_to_card()
519 s->norintsts |= SDHC_NIS_WBUFRDY; in sdhci_write_block_to_card()
521 sdhci_update_irq(s); in sdhci_write_block_to_card()
525 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { in sdhci_write_block_to_card()
526 if (s->blkcnt == 0) { in sdhci_write_block_to_card()
529 s->blkcnt--; in sdhci_write_block_to_card()
533 sdbus_write_data(&s->sdbus, s->fifo_buffer, s->blksize & BLOCK_SIZE_MASK); in sdhci_write_block_to_card()
536 s->prnsts |= SDHC_SPACE_AVAILABLE; in sdhci_write_block_to_card()
539 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || in sdhci_write_block_to_card()
540 ((s->trnmod & SDHC_TRNS_MULTI) && in sdhci_write_block_to_card()
541 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { in sdhci_write_block_to_card()
542 sdhci_end_transfer(s); in sdhci_write_block_to_card()
543 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { in sdhci_write_block_to_card()
544 s->norintsts |= SDHC_NIS_WBUFRDY; in sdhci_write_block_to_card()
548 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && in sdhci_write_block_to_card()
549 s->blkcnt > 0) { in sdhci_write_block_to_card()
550 s->prnsts &= ~SDHC_DOING_WRITE; in sdhci_write_block_to_card()
551 if (s->norintstsen & SDHC_EISEN_BLKGAP) { in sdhci_write_block_to_card()
552 s->norintsts |= SDHC_EIS_BLKGAP; in sdhci_write_block_to_card()
554 sdhci_end_transfer(s); in sdhci_write_block_to_card()
557 sdhci_update_irq(s); in sdhci_write_block_to_card()
561 * Write @size bytes of @value data to host controller @s Buffer Data Port
564 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) in sdhci_write_dataport() argument
569 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { in sdhci_write_dataport()
575 assert(s->data_count < s->buf_maxsz); in sdhci_write_dataport()
576 s->fifo_buffer[s->data_count] = value & 0xFF; in sdhci_write_dataport()
577 s->data_count++; in sdhci_write_dataport()
579 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) { in sdhci_write_dataport()
580 trace_sdhci_write_dataport(s->data_count); in sdhci_write_dataport()
581 s->data_count = 0; in sdhci_write_dataport()
582 s->prnsts &= ~SDHC_SPACE_AVAILABLE; in sdhci_write_dataport()
583 if (s->prnsts & SDHC_DOING_WRITE) { in sdhci_write_dataport()
584 sdhci_write_block_to_card(s); in sdhci_write_dataport()
595 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) in sdhci_sdma_transfer_multi_blocks() argument
599 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; in sdhci_sdma_transfer_multi_blocks()
600 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12); in sdhci_sdma_transfer_multi_blocks()
601 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); in sdhci_sdma_transfer_multi_blocks()
603 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) { in sdhci_sdma_transfer_multi_blocks()
613 if ((s->sdmasysad % boundary_chk) == 0) { in sdhci_sdma_transfer_multi_blocks()
617 s->prnsts |= SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE; in sdhci_sdma_transfer_multi_blocks()
618 if (s->trnmod & SDHC_TRNS_READ) { in sdhci_sdma_transfer_multi_blocks()
619 s->prnsts |= SDHC_DOING_READ; in sdhci_sdma_transfer_multi_blocks()
620 while (s->blkcnt) { in sdhci_sdma_transfer_multi_blocks()
621 if (s->data_count == 0) { in sdhci_sdma_transfer_multi_blocks()
622 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); in sdhci_sdma_transfer_multi_blocks()
624 begin = s->data_count; in sdhci_sdma_transfer_multi_blocks()
626 s->data_count = boundary_count + begin; in sdhci_sdma_transfer_multi_blocks()
629 s->data_count = block_size; in sdhci_sdma_transfer_multi_blocks()
631 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { in sdhci_sdma_transfer_multi_blocks()
632 s->blkcnt--; in sdhci_sdma_transfer_multi_blocks()
635 dma_memory_write(s->dma_as, s->sdmasysad, &s->fifo_buffer[begin], in sdhci_sdma_transfer_multi_blocks()
636 s->data_count - begin, MEMTXATTRS_UNSPECIFIED); in sdhci_sdma_transfer_multi_blocks()
637 s->sdmasysad += s->data_count - begin; in sdhci_sdma_transfer_multi_blocks()
638 if (s->data_count == block_size) { in sdhci_sdma_transfer_multi_blocks()
639 s->data_count = 0; in sdhci_sdma_transfer_multi_blocks()
646 s->prnsts |= SDHC_DOING_WRITE; in sdhci_sdma_transfer_multi_blocks()
647 while (s->blkcnt) { in sdhci_sdma_transfer_multi_blocks()
648 begin = s->data_count; in sdhci_sdma_transfer_multi_blocks()
650 s->data_count = boundary_count + begin; in sdhci_sdma_transfer_multi_blocks()
653 s->data_count = block_size; in sdhci_sdma_transfer_multi_blocks()
656 dma_memory_read(s->dma_as, s->sdmasysad, &s->fifo_buffer[begin], in sdhci_sdma_transfer_multi_blocks()
657 s->data_count - begin, MEMTXATTRS_UNSPECIFIED); in sdhci_sdma_transfer_multi_blocks()
658 s->sdmasysad += s->data_count - begin; in sdhci_sdma_transfer_multi_blocks()
659 if (s->data_count == block_size) { in sdhci_sdma_transfer_multi_blocks()
660 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); in sdhci_sdma_transfer_multi_blocks()
661 s->data_count = 0; in sdhci_sdma_transfer_multi_blocks()
662 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { in sdhci_sdma_transfer_multi_blocks()
663 s->blkcnt--; in sdhci_sdma_transfer_multi_blocks()
672 if (s->blkcnt == 0) { in sdhci_sdma_transfer_multi_blocks()
673 sdhci_end_transfer(s); in sdhci_sdma_transfer_multi_blocks()
675 if (s->norintstsen & SDHC_NISEN_DMA) { in sdhci_sdma_transfer_multi_blocks()
676 s->norintsts |= SDHC_NIS_DMA; in sdhci_sdma_transfer_multi_blocks()
678 sdhci_update_irq(s); in sdhci_sdma_transfer_multi_blocks()
683 static void sdhci_sdma_transfer_single_block(SDHCIState *s) in sdhci_sdma_transfer_single_block() argument
685 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK; in sdhci_sdma_transfer_single_block()
687 if (s->trnmod & SDHC_TRNS_READ) { in sdhci_sdma_transfer_single_block()
688 sdbus_read_data(&s->sdbus, s->fifo_buffer, datacnt); in sdhci_sdma_transfer_single_block()
689 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt, in sdhci_sdma_transfer_single_block()
692 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt, in sdhci_sdma_transfer_single_block()
694 sdbus_write_data(&s->sdbus, s->fifo_buffer, datacnt); in sdhci_sdma_transfer_single_block()
696 s->blkcnt--; in sdhci_sdma_transfer_single_block()
698 sdhci_end_transfer(s); in sdhci_sdma_transfer_single_block()
708 static void get_adma_description(SDHCIState *s, ADMADescr *dscr) in get_adma_description() argument
712 hwaddr entry_addr = (hwaddr)s->admasysaddr; in get_adma_description()
713 switch (SDHC_DMA_TYPE(s->hostctl1)) { in get_adma_description()
715 dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2), in get_adma_description()
728 dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1), in get_adma_description()
741 dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1, in get_adma_description()
743 dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2, in get_adma_description()
746 dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8, in get_adma_description()
757 static void sdhci_do_adma(SDHCIState *s) in sdhci_do_adma() argument
760 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; in sdhci_do_adma()
766 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN && !s->blkcnt) { in sdhci_do_adma()
768 sdhci_end_transfer(s); in sdhci_do_adma()
773 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; in sdhci_do_adma()
775 get_adma_description(s, &dscr); in sdhci_do_adma()
780 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; in sdhci_do_adma()
781 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; in sdhci_do_adma()
784 if (s->errintstsen & SDHC_EISEN_ADMAERR) { in sdhci_do_adma()
785 s->errintsts |= SDHC_EIS_ADMAERR; in sdhci_do_adma()
786 s->norintsts |= SDHC_NIS_ERR; in sdhci_do_adma()
789 sdhci_update_irq(s); in sdhci_do_adma()
797 s->prnsts |= SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE; in sdhci_do_adma()
798 if (s->trnmod & SDHC_TRNS_READ) { in sdhci_do_adma()
799 s->prnsts |= SDHC_DOING_READ; in sdhci_do_adma()
801 if (s->data_count == 0) { in sdhci_do_adma()
802 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); in sdhci_do_adma()
804 begin = s->data_count; in sdhci_do_adma()
806 s->data_count = length + begin; in sdhci_do_adma()
809 s->data_count = block_size; in sdhci_do_adma()
812 res = dma_memory_write(s->dma_as, dscr.addr, in sdhci_do_adma()
813 &s->fifo_buffer[begin], in sdhci_do_adma()
814 s->data_count - begin, in sdhci_do_adma()
819 dscr.addr += s->data_count - begin; in sdhci_do_adma()
820 if (s->data_count == block_size) { in sdhci_do_adma()
821 s->data_count = 0; in sdhci_do_adma()
822 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { in sdhci_do_adma()
823 s->blkcnt--; in sdhci_do_adma()
824 if (s->blkcnt == 0) { in sdhci_do_adma()
831 s->prnsts |= SDHC_DOING_WRITE; in sdhci_do_adma()
833 begin = s->data_count; in sdhci_do_adma()
835 s->data_count = length + begin; in sdhci_do_adma()
838 s->data_count = block_size; in sdhci_do_adma()
841 res = dma_memory_read(s->dma_as, dscr.addr, in sdhci_do_adma()
842 &s->fifo_buffer[begin], in sdhci_do_adma()
843 s->data_count - begin, in sdhci_do_adma()
848 dscr.addr += s->data_count - begin; in sdhci_do_adma()
849 if (s->data_count == block_size) { in sdhci_do_adma()
850 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); in sdhci_do_adma()
851 s->data_count = 0; in sdhci_do_adma()
852 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { in sdhci_do_adma()
853 s->blkcnt--; in sdhci_do_adma()
854 if (s->blkcnt == 0) { in sdhci_do_adma()
862 s->data_count = 0; in sdhci_do_adma()
863 if (s->errintstsen & SDHC_EISEN_ADMAERR) { in sdhci_do_adma()
865 s->errintsts |= SDHC_EIS_ADMAERR; in sdhci_do_adma()
866 s->norintsts |= SDHC_NIS_ERR; in sdhci_do_adma()
868 sdhci_update_irq(s); in sdhci_do_adma()
870 s->admasysaddr += dscr.incr; in sdhci_do_adma()
874 s->admasysaddr = dscr.addr; in sdhci_do_adma()
875 trace_sdhci_adma("link", s->admasysaddr); in sdhci_do_adma()
878 s->admasysaddr += dscr.incr; in sdhci_do_adma()
883 trace_sdhci_adma("interrupt", s->admasysaddr); in sdhci_do_adma()
884 if (s->norintstsen & SDHC_NISEN_DMA) { in sdhci_do_adma()
885 s->norintsts |= SDHC_NIS_DMA; in sdhci_do_adma()
888 if (sdhci_update_irq(s) && !(dscr.attr & SDHC_ADMA_ATTR_END)) { in sdhci_do_adma()
895 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && in sdhci_do_adma()
896 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { in sdhci_do_adma()
899 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && in sdhci_do_adma()
900 s->blkcnt != 0)) { in sdhci_do_adma()
902 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | in sdhci_do_adma()
904 if (s->errintstsen & SDHC_EISEN_ADMAERR) { in sdhci_do_adma()
906 s->errintsts |= SDHC_EIS_ADMAERR; in sdhci_do_adma()
907 s->norintsts |= SDHC_NIS_ERR; in sdhci_do_adma()
910 sdhci_update_irq(s); in sdhci_do_adma()
912 sdhci_end_transfer(s); in sdhci_do_adma()
919 timer_mod(s->transfer_timer, in sdhci_do_adma()
927 SDHCIState *s = (SDHCIState *)opaque; in sdhci_data_transfer() local
929 if (s->trnmod & SDHC_TRNS_DMA) { in sdhci_data_transfer()
930 switch (SDHC_DMA_TYPE(s->hostctl1)) { in sdhci_data_transfer()
932 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { in sdhci_data_transfer()
933 sdhci_sdma_transfer_single_block(s); in sdhci_data_transfer()
935 sdhci_sdma_transfer_multi_blocks(s); in sdhci_data_transfer()
940 if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) { in sdhci_data_transfer()
945 sdhci_do_adma(s); in sdhci_data_transfer()
948 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) { in sdhci_data_transfer()
953 sdhci_do_adma(s); in sdhci_data_transfer()
956 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) || in sdhci_data_transfer()
957 !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) { in sdhci_data_transfer()
962 sdhci_do_adma(s); in sdhci_data_transfer()
969 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { in sdhci_data_transfer()
970 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | in sdhci_data_transfer()
972 sdhci_read_block_from_card(s); in sdhci_data_transfer()
974 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | in sdhci_data_transfer()
976 sdhci_write_block_to_card(s); in sdhci_data_transfer()
981 static bool sdhci_can_issue_command(SDHCIState *s) in sdhci_can_issue_command() argument
983 if (!SDHC_CLOCK_IS_ON(s->clkcon) || in sdhci_can_issue_command()
984 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && in sdhci_can_issue_command()
985 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || in sdhci_can_issue_command()
986 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && in sdhci_can_issue_command()
987 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { in sdhci_can_issue_command()
999 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) in sdhci_buff_access_is_sequential() argument
1001 if ((s->data_count & 0x3) != byte_num) { in sdhci_buff_access_is_sequential()
1010 static void sdhci_resume_pending_transfer(SDHCIState *s) in sdhci_resume_pending_transfer() argument
1012 timer_del(s->transfer_timer); in sdhci_resume_pending_transfer()
1013 sdhci_data_transfer(s); in sdhci_resume_pending_transfer()
1018 SDHCIState *s = (SDHCIState *)opaque; in sdhci_read() local
1021 if (timer_pending(s->transfer_timer)) { in sdhci_read()
1022 sdhci_resume_pending_transfer(s); in sdhci_read()
1027 ret = s->sdmasysad; in sdhci_read()
1030 ret = s->blksize | (s->blkcnt << 16); in sdhci_read()
1033 ret = s->argument; in sdhci_read()
1036 ret = s->trnmod | (s->cmdreg << 16); in sdhci_read()
1039 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; in sdhci_read()
1042 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { in sdhci_read()
1043 ret = sdhci_read_dataport(s, size); in sdhci_read()
1049 ret = s->prnsts; in sdhci_read()
1051 sdbus_get_dat_lines(&s->sdbus)); in sdhci_read()
1053 sdbus_get_cmd_line(&s->sdbus)); in sdhci_read()
1056 ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) | in sdhci_read()
1057 (s->wakcon << 24); in sdhci_read()
1060 ret = s->clkcon | (s->timeoutcon << 16); in sdhci_read()
1063 ret = s->norintsts | (s->errintsts << 16); in sdhci_read()
1066 ret = s->norintstsen | (s->errintstsen << 16); in sdhci_read()
1069 ret = s->norintsigen | (s->errintsigen << 16); in sdhci_read()
1072 ret = s->acmd12errsts | (s->hostctl2 << 16); in sdhci_read()
1075 ret = (uint32_t)s->capareg; in sdhci_read()
1078 ret = (uint32_t)(s->capareg >> 32); in sdhci_read()
1081 ret = (uint32_t)s->maxcurr; in sdhci_read()
1084 ret = (uint32_t)(s->maxcurr >> 32); in sdhci_read()
1087 ret = s->admaerr; in sdhci_read()
1090 ret = (uint32_t)s->admasysaddr; in sdhci_read()
1093 ret = (uint32_t)(s->admasysaddr >> 32); in sdhci_read()
1096 ret = (s->version << 16) | sdhci_slotint(s); in sdhci_read()
1110 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) in sdhci_blkgap_write() argument
1112 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { in sdhci_blkgap_write()
1115 s->blkgap = value & SDHC_STOP_AT_GAP_REQ; in sdhci_blkgap_write()
1117 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && in sdhci_blkgap_write()
1118 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { in sdhci_blkgap_write()
1119 if (s->stopped_state == sdhc_gap_read) { in sdhci_blkgap_write()
1120 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; in sdhci_blkgap_write()
1121 sdhci_read_block_from_card(s); in sdhci_blkgap_write()
1123 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; in sdhci_blkgap_write()
1124 sdhci_write_block_to_card(s); in sdhci_blkgap_write()
1126 s->stopped_state = sdhc_not_stopped; in sdhci_blkgap_write()
1127 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { in sdhci_blkgap_write()
1128 if (s->prnsts & SDHC_DOING_READ) { in sdhci_blkgap_write()
1129 s->stopped_state = sdhc_gap_read; in sdhci_blkgap_write()
1130 } else if (s->prnsts & SDHC_DOING_WRITE) { in sdhci_blkgap_write()
1131 s->stopped_state = sdhc_gap_write; in sdhci_blkgap_write()
1136 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) in sdhci_reset_write() argument
1140 sdhci_reset(s); in sdhci_reset_write()
1143 s->prnsts &= ~SDHC_CMD_INHIBIT; in sdhci_reset_write()
1144 s->norintsts &= ~SDHC_NIS_CMDCMP; in sdhci_reset_write()
1147 s->data_count = 0; in sdhci_reset_write()
1148 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | in sdhci_reset_write()
1151 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); in sdhci_reset_write()
1152 s->stopped_state = sdhc_not_stopped; in sdhci_reset_write()
1153 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | in sdhci_reset_write()
1162 SDHCIState *s = (SDHCIState *)opaque; in sdhci_write() local
1168 if (timer_pending(s->transfer_timer)) { in sdhci_write()
1169 sdhci_resume_pending_transfer(s); in sdhci_write()
1174 if (!TRANSFERRING_DATA(s->prnsts)) { in sdhci_write()
1175 s->sdmasysad = (s->sdmasysad & mask) | value; in sdhci_write()
1176 MASKED_WRITE(s->sdmasysad, mask, value); in sdhci_write()
1178 if (!(mask & 0xFF000000) && s->blkcnt && in sdhci_write()
1179 (s->blksize & BLOCK_SIZE_MASK) && in sdhci_write()
1180 SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) { in sdhci_write()
1181 if (s->trnmod & SDHC_TRNS_MULTI) { in sdhci_write()
1182 sdhci_sdma_transfer_multi_blocks(s); in sdhci_write()
1184 sdhci_sdma_transfer_single_block(s); in sdhci_write()
1190 if (!TRANSFERRING_DATA(s->prnsts)) { in sdhci_write()
1191 uint16_t blksize = s->blksize; in sdhci_write()
1197 MASKED_WRITE(s->blksize, mask, extract32(value, 0, 15)); in sdhci_write()
1198 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); in sdhci_write()
1201 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { in sdhci_write()
1202 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " in sdhci_write()
1203 "the maximum buffer 0x%x\n", __func__, s->blksize, in sdhci_write()
1204 s->buf_maxsz); in sdhci_write()
1206 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); in sdhci_write()
1211 * the previous one, reset the data pointer of s->fifo_buffer[] in sdhci_write()
1212 * so that s->fifo_buffer[] can be filled in using the new block in sdhci_write()
1215 if (blksize != s->blksize) { in sdhci_write()
1216 s->data_count = 0; in sdhci_write()
1222 MASKED_WRITE(s->argument, mask, value); in sdhci_write()
1229 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { in sdhci_write()
1234 if (s->prnsts & SDHC_DATA_INHIBIT) { in sdhci_write()
1238 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); in sdhci_write()
1239 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); in sdhci_write()
1242 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { in sdhci_write()
1246 sdhci_send_command(s); in sdhci_write()
1249 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { in sdhci_write()
1250 sdhci_write_dataport(s, value >> shift, size); in sdhci_write()
1255 sdhci_blkgap_write(s, value >> 16); in sdhci_write()
1257 MASKED_WRITE(s->hostctl1, mask, value); in sdhci_write()
1258 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); in sdhci_write()
1259 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); in sdhci_write()
1260 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || in sdhci_write()
1261 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { in sdhci_write()
1262 s->pwrcon &= ~SDHC_POWER_ON; in sdhci_write()
1267 sdhci_reset_write(s, value >> 24); in sdhci_write()
1269 MASKED_WRITE(s->clkcon, mask, value); in sdhci_write()
1270 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); in sdhci_write()
1271 if (s->clkcon & SDHC_CLOCK_INT_EN) { in sdhci_write()
1272 s->clkcon |= SDHC_CLOCK_INT_STABLE; in sdhci_write()
1274 s->clkcon &= ~SDHC_CLOCK_INT_STABLE; in sdhci_write()
1278 if (s->norintstsen & SDHC_NISEN_CARDINT) { in sdhci_write()
1281 s->norintsts &= mask | ~value; in sdhci_write()
1282 s->errintsts &= (mask >> 16) | ~(value >> 16); in sdhci_write()
1283 if (s->errintsts) { in sdhci_write()
1284 s->norintsts |= SDHC_NIS_ERR; in sdhci_write()
1286 s->norintsts &= ~SDHC_NIS_ERR; in sdhci_write()
1288 sdhci_update_irq(s); in sdhci_write()
1291 MASKED_WRITE(s->norintstsen, mask, value); in sdhci_write()
1292 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); in sdhci_write()
1293 s->norintsts &= s->norintstsen; in sdhci_write()
1294 s->errintsts &= s->errintstsen; in sdhci_write()
1295 if (s->errintsts) { in sdhci_write()
1296 s->norintsts |= SDHC_NIS_ERR; in sdhci_write()
1298 s->norintsts &= ~SDHC_NIS_ERR; in sdhci_write()
1304 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { in sdhci_write()
1305 assert(s->pending_insert_quirk); in sdhci_write()
1306 s->norintsts |= SDHC_NIS_INSERT; in sdhci_write()
1307 s->pending_insert_state = false; in sdhci_write()
1309 sdhci_update_irq(s); in sdhci_write()
1312 MASKED_WRITE(s->norintsigen, mask, value); in sdhci_write()
1313 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); in sdhci_write()
1314 sdhci_update_irq(s); in sdhci_write()
1317 MASKED_WRITE(s->admaerr, mask, value); in sdhci_write()
1320 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | in sdhci_write()
1324 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | in sdhci_write()
1328 s->acmd12errsts |= value; in sdhci_write()
1329 s->errintsts |= (value >> 16) & s->errintstsen; in sdhci_write()
1330 if (s->acmd12errsts) { in sdhci_write()
1331 s->errintsts |= SDHC_EIS_CMD12ERR; in sdhci_write()
1333 if (s->errintsts) { in sdhci_write()
1334 s->norintsts |= SDHC_NIS_ERR; in sdhci_write()
1336 sdhci_update_irq(s); in sdhci_write()
1339 MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX); in sdhci_write()
1340 if (s->uhs_mode >= UHS_I) { in sdhci_write()
1341 MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16); in sdhci_write()
1343 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) { in sdhci_write()
1344 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V); in sdhci_write()
1346 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V); in sdhci_write()
1394 static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) in sdhci_init_readonly_registers() argument
1398 switch (s->sd_spec_version) { in sdhci_init_readonly_registers()
1405 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); in sdhci_init_readonly_registers()
1407 sdhci_check_capareg(s, errp); in sdhci_init_readonly_registers()
1415 void sdhci_initfn(SDHCIState *s) in sdhci_initfn() argument
1417 qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); in sdhci_initfn()
1419 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, in sdhci_initfn()
1420 sdhci_raise_insertion_irq, s); in sdhci_initfn()
1421 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, in sdhci_initfn()
1422 sdhci_data_transfer, s); in sdhci_initfn()
1424 s->io_ops = &sdhci_mmio_le_ops; in sdhci_initfn()
1427 void sdhci_uninitfn(SDHCIState *s) in sdhci_uninitfn() argument
1429 timer_free(s->insert_timer); in sdhci_uninitfn()
1430 timer_free(s->transfer_timer); in sdhci_uninitfn()
1432 g_free(s->fifo_buffer); in sdhci_uninitfn()
1433 s->fifo_buffer = NULL; in sdhci_uninitfn()
1436 void sdhci_common_realize(SDHCIState *s, Error **errp) in sdhci_common_realize() argument
1440 switch (s->endianness) { in sdhci_common_realize()
1442 /* s->io_ops is little endian by default */ in sdhci_common_realize()
1445 if (s->io_ops != &sdhci_mmio_le_ops) { in sdhci_common_realize()
1449 s->io_ops = &sdhci_mmio_be_ops; in sdhci_common_realize()
1456 sdhci_init_readonly_registers(s, errp); in sdhci_common_realize()
1461 s->buf_maxsz = sdhci_get_fifolen(s); in sdhci_common_realize()
1462 s->fifo_buffer = g_malloc0(s->buf_maxsz); in sdhci_common_realize()
1464 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", in sdhci_common_realize()
1468 void sdhci_common_unrealize(SDHCIState *s) in sdhci_common_unrealize() argument
1477 g_free(s->fifo_buffer); in sdhci_common_unrealize()
1478 s->fifo_buffer = NULL; in sdhci_common_unrealize()
1483 SDHCIState *s = opaque; in sdhci_pending_insert_vmstate_needed() local
1485 return s->pending_insert_state; in sdhci_pending_insert_vmstate_needed()
1564 SDHCIState *s = SYSBUS_SDHCI(obj); in sdhci_sysbus_init() local
1566 sdhci_initfn(s); in sdhci_sysbus_init()
1571 SDHCIState *s = SYSBUS_SDHCI(obj); in sdhci_sysbus_finalize() local
1573 if (s->dma_mr) { in sdhci_sysbus_finalize()
1574 object_unparent(OBJECT(s->dma_mr)); in sdhci_sysbus_finalize()
1577 sdhci_uninitfn(s); in sdhci_sysbus_finalize()
1583 SDHCIState *s = SYSBUS_SDHCI(dev); in sdhci_sysbus_realize() local
1586 sdhci_common_realize(s, errp); in sdhci_sysbus_realize()
1591 if (s->dma_mr) { in sdhci_sysbus_realize()
1592 s->dma_as = &s->sysbus_dma_as; in sdhci_sysbus_realize()
1593 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma"); in sdhci_sysbus_realize()
1596 s->dma_as = &address_space_memory; in sdhci_sysbus_realize()
1599 sysbus_init_irq(sbd, &s->irq); in sdhci_sysbus_realize()
1601 sysbus_init_mmio(sbd, &s->iomem); in sdhci_sysbus_realize()
1606 SDHCIState *s = SYSBUS_SDHCI(dev); in sdhci_sysbus_unrealize() local
1608 sdhci_common_unrealize(s); in sdhci_sysbus_unrealize()
1610 if (s->dma_mr) { in sdhci_sysbus_unrealize()
1611 address_space_destroy(s->dma_as); in sdhci_sysbus_unrealize()
1659 SDHCIState *s = SYSBUS_SDHCI(opaque); in usdhc_read() local
1673 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3); in usdhc_read()
1675 if (s->hostctl1 & SDHC_CTRL_8BITBUS) { in usdhc_read()
1679 if (s->hostctl1 & SDHC_CTRL_4BITBUS) { in usdhc_read()
1684 ret |= (uint32_t)s->blkgap << 16; in usdhc_read()
1685 ret |= (uint32_t)s->wakcon << 24; in usdhc_read()
1692 if (s->clkcon & SDHC_CLOCK_INT_STABLE) { in usdhc_read()
1698 ret = s->vendor_spec; in usdhc_read()
1716 SDHCIState *s = SYSBUS_SDHCI(opaque); in usdhc_write() local
1729 s->vendor_spec = value; in usdhc_write()
1730 switch (s->vendor) { in usdhc_write()
1733 s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF; in usdhc_write()
1735 s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF; in usdhc_write()
1745 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL) in usdhc_write()
1764 * and here's what SDCHI spec expects those offsets to be: in usdhc_write()
1824 value |= (uint16_t)s->pwrcon << 8; in usdhc_write()
1841 * sdhci_send_command(s) which we don't want. in usdhc_write()
1844 s->trnmod = value & UINT16_MAX; in usdhc_write()
1852 * cached value from s->trnmod and let the SDHCI in usdhc_write()
1855 sdhci_write(opaque, offset, val | s->trnmod, size); in usdhc_write()
1888 SDHCIState *s = SYSBUS_SDHCI(obj); in imx_usdhc_init() local
1890 s->io_ops = &usdhc_mmio_ops; in imx_usdhc_init()
1891 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; in imx_usdhc_init()
1947 SDHCIState *s = SYSBUS_SDHCI(obj); in sdhci_s3c_init() local
1949 s->io_ops = &sdhci_s3c_mmio_ops; in sdhci_s3c_init()