/openbmc/linux/drivers/pci/pcie/ |
H A D | ptm.c | 13 * If the next upstream device supports PTM, return it; otherwise return 14 * NULL. PTM Messages are local, so both link partners must support it. 21 * Switch Downstream Ports are not permitted to have a PTM in pci_upstream_ptm() 22 * capability; their PTM behavior is controlled by the Upstream in pci_upstream_ptm() 36 * Find the PTM Capability (if present) and extract the information we need 41 u16 ptm; in pci_ptm_init() local 48 ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM); in pci_ptm_init() 49 if (!ptm) in pci_ptm_init() 52 dev->ptm_cap = ptm; in pci_ptm_init() 55 pci_read_config_dword(dev, ptm + PCI_PTM_CAP, &cap); in pci_ptm_init() [all …]
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H A D | Kconfig | 134 This enables PCI Express Precision Time Measurement (PTM) 137 This is only useful if you have devices that support PTM, but it
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H A D | Makefile | 14 obj-$(CONFIG_PCIE_PTM) += ptm.o
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/openbmc/linux/Documentation/ABI/testing/ |
H A D | sysfs-bus-coresight-devices-etm3x | 1 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_source 11 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_idx 18 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_acctype 29 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_range 37 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_single 45 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_start 53 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_stop 61 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_idx 67 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_event 74 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_val [all …]
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/openbmc/qemu/hw/pci-host/ |
H A D | ppc4xx_pci.c | 59 struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS]; member 87 * PCI Target Map (PTM) registers specify which PCI addresses are translated to 149 pci->ptm[0].ms = value; in ppc4xx_pci_reg_write4() 152 pci->ptm[0].la = value; in ppc4xx_pci_reg_write4() 155 pci->ptm[1].ms = value; in ppc4xx_pci_reg_write4() 158 pci->ptm[1].la = value; in ppc4xx_pci_reg_write4() 216 value = pci->ptm[0].ms; in ppc4xx_pci_reg_read4() 219 value = pci->ptm[0].la; in ppc4xx_pci_reg_read4() 222 value = pci->ptm[1].ms; in ppc4xx_pci_reg_read4() 225 value = pci->ptm[1].la; in ppc4xx_pci_reg_read4() [all …]
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/openbmc/linux/arch/arm/boot/dts/hisilicon/ |
H A D | hip04.dtsi | 732 ptm@0,e3c7c000 { 748 ptm@0,e3c7d000 { 764 ptm@0,e3c7e000 { 780 ptm@0,e3c7f000 { 796 ptm@0,e3cbc000 { 812 ptm@0,e3cbd000 { 828 ptm@0,e3cbe000 { 844 ptm@0,e3cbf000 { 860 ptm@0,e3cfc000 { 876 ptm@0,e3cfd000 { [all …]
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/openbmc/linux/drivers/net/ethernet/intel/igc/ |
H A D | igc_ptp.c | 885 * PCIe PTM: 887 * 1. We have an way to convert the timestamps in the PTM messages 891 * 2. We have PTM enabled in the path from the device to the PCIe root port. 898 /* FIXME: it was noticed that enabling support for PCIe PTM in in igc_is_crosststamp_supported() 926 netdev_err(netdev, "PTM Error: Root port timeout\n"); in igc_ptm_log_error() 929 netdev_err(netdev, "PTM Error: Bad response, PTM Response Data expected\n"); in igc_ptm_log_error() 932 netdev_err(netdev, "PTM Error: T4 minus T1 overflow\n"); in igc_ptm_log_error() 935 netdev_err(netdev, "PTM Error: 1588 timer adjusted during first PTM cycle\n"); in igc_ptm_log_error() 938 netdev_err(netdev, "PTM Error: 1588 timer adjusted during non-first PTM cycle\n"); in igc_ptm_log_error() 941 netdev_err(netdev, "PTM Error: Unknown error (%#x)\n", ptm_stat); in igc_ptm_log_error() [all …]
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H A D | igc_defines.h | 558 /* PCIe PTM Control */ 559 #define IGC_PTM_CTRL_START_NOW BIT(29) /* Start PTM Now */ 560 #define IGC_PTM_CTRL_EN BIT(30) /* Enable PTM */ 561 #define IGC_PTM_CTRL_TRIG BIT(31) /* PTM Cycle trigger */ 566 #define IGC_PTM_CYC_TIME_DEFAULT 5 /* Default PTM cycle time */ 567 #define IGC_PTM_TIMEOUT_DEFAULT 255 /* Default timeout for PTM errors */ 577 /* PCIe PTM Status */ 578 #define IGC_PTM_STAT_VALID BIT(0) /* PTM Status */ 580 #define IGC_PTM_STAT_BAD_PTM_RES BIT(2) /* PTM Response msg instead of PTM Response Data */ 582 #define IGC_PTM_STAT_ADJUST_1ST BIT(4) /* 1588 timer adjusted during 1st PTM cycle */ [all …]
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H A D | igc_regs.h | 264 #define IGC_PTM_CTRL 0x12540 /* PTM Control */ 265 #define IGC_PTM_STAT 0x12544 /* PTM Status */ 266 #define IGC_PTM_CYCLE_CTRL 0x1254C /* PTM Cycle Control */ 268 /* PTM Time registers */ 276 #define IGC_PTM_PREV_T4M1 0x12578 /* T4 Minus T1 on previous PTM Cycle */ 277 #define IGC_PTM_CURR_T4M1 0x1257C /* T4 Minus T1 on this PTM Cycle */ 278 #define IGC_PTM_PREV_T3M2 0x12580 /* T3 Minus T2 on previous PTM Cycle */ 279 #define IGC_PTM_TDELAY 0x12594 /* PTM PCIe Link Delay */
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/openbmc/linux/arch/sh/include/cpu-sh4/cpu/ |
H A D | sh7724.h | 65 /* PTM */ 148 /* LCDC (PTC/PTD/PTE/PTF/PTM/PTR) */ 159 /* SCIF0 (PTF/PTM) */ 220 /* VOU (PTL/PTM/PTN*/ 227 /* MSIOF0 (PTL/PTM) */
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H A D | sh7757.h | 54 /* PTM */ 180 /* PTM (mobule: LBSC, IIC) */
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/openbmc/linux/Documentation/devicetree/bindings/arm/ |
H A D | arm,coresight-etm.yaml | 91 Must be present if the system accesses ETM/PTM management registers via 128 ptm@2201c000 { 144 ptm@2201d000 {
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/openbmc/linux/tools/include/linux/ |
H A D | coresight-pmu.h | 28 * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore, 29 * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
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/openbmc/linux/include/linux/ |
H A D | coresight-pmu.h | 28 * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore, 29 * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
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/openbmc/linux/scripts/kconfig/ |
H A D | conf.c | 181 int ptm = 33; /* probability of tristate = m */ in conf_set_all_new_symbols() local 207 ptm = pby / 2; in conf_set_all_new_symbols() 208 pty = pby - ptm; in conf_set_all_new_symbols() 212 ptm = p[1]; in conf_set_all_new_symbols() 213 pby = pty + ptm; in conf_set_all_new_symbols() 218 ptm = p[2]; in conf_set_all_new_symbols() 222 if (pty + ptm > 100) { in conf_set_all_new_symbols() 252 else if (cnt < pty + ptm) in conf_set_all_new_symbols()
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/openbmc/linux/Documentation/trace/coresight/ |
H A D | coresight.rst | 41 | # ETM # ::::: | # PTM # ::::: ::::: @ | 77 ; PTM = Program Trace Macrocell 89 the basic tracing functionality, enabling components such ETM/PTM, funnel, 99 PTM: 157 replicator 20030000.tpiu 2201c000.ptm 2203c000.etm 2203e000.etm 158 20010000.etb 20040000.funnel 2201d000.ptm 2203d000.etm 351 replicator 20030000.tpiu 2201c000.ptm 2203c000.etm 2203e000.etm 352 20010000.etb 20040000.funnel 2201d000.ptm 2203d000.etm 365 root:/sys/bus/coresight/devices# echo 1 > 2201c000.ptm/enable_source 366 root:/sys/bus/coresight/devices# cat 2201c000.ptm/enable_source [all …]
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/openbmc/u-boot/scripts/kconfig/ |
H A D | confdata.c | 1124 int i, cnt, pby, pty, ptm; /* pby: probability of bool = y in conf_set_all_new_symbols() local 1126 * ptm: probability of tristate = m in conf_set_all_new_symbols() 1129 pby = 50; pty = ptm = 33; /* can't go as the default in switch-case in conf_set_all_new_symbols() 1153 pby = p[0]; ptm = pby/2; pty = pby-ptm; in conf_set_all_new_symbols() 1156 pty = p[0]; ptm = p[1]; pby = pty + ptm; in conf_set_all_new_symbols() 1159 pby = p[0]; pty = p[1]; ptm = p[2]; in conf_set_all_new_symbols() 1163 if( pty+ptm > 100 ) { in conf_set_all_new_symbols() 1197 else if (cnt < (pty+ptm)) in conf_set_all_new_symbols()
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/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | ti,k3-am654-cpts.yaml | 30 Measurement (PTM). 36 - PCIe subsystem CPTS for PTM support
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/openbmc/linux/drivers/hwtracing/coresight/ |
H A D | coresight-etm3x-core.c | 349 * Possible to have cores with PTM (supports ret stack) and ETM in etm_parse_event_config() 1000 /* PTM 1.0 */ 1001 CS_AMBA_ID_DATA(0x000bb950, "PTM 1.0"), 1002 /* PTM 1.1 */ 1003 CS_AMBA_ID_DATA(0x000bb95f, "PTM 1.1"), 1004 /* PTM 1.1 Qualcomm */ 1005 CS_AMBA_ID_DATA(0x000b006f, "PTM 1.1"),
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H A D | coresight-etm.h | 145 * @mode: controls various modes supported by this ETM/PTM. 216 * @arch: ETM/PTM version number.
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/openbmc/qemu/hw/misc/ |
H A D | sifive_u_otp.c | 87 return s->ptm; in sifive_u_otp_read() 141 s->ptm = val32; in sifive_u_otp_write()
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/openbmc/qemu/include/hw/misc/ |
H A D | sifive_u_otp.h | 76 uint32_t ptm; member
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/openbmc/linux/tools/testing/selftests/tc-testing/tc-tests/qdiscs/ |
H A D | cake.json | 303 "name": "Create CAKE with memlimit and ptm flag", 314 "cmdUnderTest": "$TC qdisc add dev $DUMMY handle 1: root cake memlimit 10000 ptm", 317 …iffserv3 triple-isolate nonat nowash no-ack-filter split-gso rtt 100ms raw ptm overhead 0 memlimit…
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/openbmc/linux/drivers/net/ethernet/intel/ |
H A D | Kconfig | 315 bool "Support HW cross-timestamp on platforms with PTM support" 320 with PCIe PTM support. The cross-timestamp is available through
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/openbmc/u-boot/board/renesas/ecovec/ |
H A D | ecovec.c | 73 /* SCIF0 (PTF, PTM) */ in board_init()
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