xref: /openbmc/linux/drivers/pci/pcie/Kconfig (revision 7ae9fb1b7ecbb5d85d07857943f677fd1a559b18)
17328c8f4SBjorn Helgaas# SPDX-License-Identifier: GPL-2.0
21da177e4SLinus Torvalds#
31da177e4SLinus Torvalds# PCI Express Port Bus Configuration
41da177e4SLinus Torvalds#
51da177e4SLinus Torvaldsconfig PCIEPORTBUS
6d47af0bcSEzequiel Garcia	bool "PCI Express Port Bus support"
7*e67ad935SAlbert Zhou	default y if USB4
81da177e4SLinus Torvalds	help
98f55ed3fSHou Zhiqiang	  This enables PCI Express Port Bus support. Users can then enable
108f55ed3fSHou Zhiqiang	  support for Native Hot-Plug, Advanced Error Reporting, Power
118f55ed3fSHou Zhiqiang	  Management Events, and Downstream Port Containment.
121da177e4SLinus Torvalds
131da177e4SLinus Torvalds#
141da177e4SLinus Torvalds# Include service Kconfig here
151da177e4SLinus Torvalds#
161da177e4SLinus Torvaldsconfig HOTPLUG_PCI_PCIE
17c10cc483SBjorn Helgaas	bool "PCI Express Hotplug driver"
181da177e4SLinus Torvalds	depends on HOTPLUG_PCI && PCIEPORTBUS
19*e67ad935SAlbert Zhou	default y if USB4
201da177e4SLinus Torvalds	help
21*e67ad935SAlbert Zhou	  Say Y here if you have a motherboard that supports PCIe native
22*e67ad935SAlbert Zhou	  hotplug.
23*e67ad935SAlbert Zhou
24*e67ad935SAlbert Zhou	  Thunderbolt/USB4 PCIe tunneling depends on native PCIe hotplug.
251da177e4SLinus Torvalds
261da177e4SLinus Torvalds	  When in doubt, say N.
271da177e4SLinus Torvalds
284696b828SBjorn Helgaasconfig PCIEAER
290b15f1e3SBjorn Helgaas	bool "PCI Express Advanced Error Reporting support"
304696b828SBjorn Helgaas	depends on PCIEPORTBUS
314696b828SBjorn Helgaas	select RAS
324696b828SBjorn Helgaas	help
334696b828SBjorn Helgaas	  This enables PCI Express Root Port Advanced Error Reporting
344696b828SBjorn Helgaas	  (AER) driver support. Error reporting messages sent to Root
354696b828SBjorn Helgaas	  Port will be handled by PCI Express AER driver.
364696b828SBjorn Helgaas
374696b828SBjorn Helgaasconfig PCIEAER_INJECT
380b15f1e3SBjorn Helgaas	tristate "PCI Express error injection support"
394696b828SBjorn Helgaas	depends on PCIEAER
409ae05225SThomas Gleixner	select GENERIC_IRQ_INJECTION
414696b828SBjorn Helgaas	help
424696b828SBjorn Helgaas	  This enables PCI Express Root Port Advanced Error Reporting
434696b828SBjorn Helgaas	  (AER) software error injector.
444696b828SBjorn Helgaas
450b15f1e3SBjorn Helgaas	  Debugging AER code is quite difficult because it is hard
460b15f1e3SBjorn Helgaas	  to trigger various real hardware errors. Software-based
474696b828SBjorn Helgaas	  error injection can fake almost all kinds of errors with the
484696b828SBjorn Helgaas	  help of a user space helper tool aer-inject, which can be
494696b828SBjorn Helgaas	  gotten from:
50602a4edaSYicong Yang	     https://git.kernel.org/cgit/linux/kernel/git/gong.chen/aer-inject.git/
514696b828SBjorn Helgaas
524696b828SBjorn Helgaas#
534696b828SBjorn Helgaas# PCI Express ECRC
544696b828SBjorn Helgaas#
554696b828SBjorn Helgaasconfig PCIE_ECRC
564696b828SBjorn Helgaas	bool "PCI Express ECRC settings control"
574696b828SBjorn Helgaas	depends on PCIEAER
584696b828SBjorn Helgaas	help
594696b828SBjorn Helgaas	  Used to override firmware/bios settings for PCI Express ECRC
604696b828SBjorn Helgaas	  (transaction layer end-to-end CRC checking).
614696b828SBjorn Helgaas
624696b828SBjorn Helgaas	  When in doubt, say N.
637d715a6cSShaohua Li
647d715a6cSShaohua Li#
657d715a6cSShaohua Li# PCI Express ASPM
667d715a6cSShaohua Li#
677d715a6cSShaohua Liconfig PCIEASPM
686a108a14SDavid Rientjes	bool "PCI Express ASPM control" if EXPERT
69ea5f9fc5SMatthew Garrett	default y
707d715a6cSShaohua Li	help
71ea5f9fc5SMatthew Garrett	  This enables OS control over PCI Express ASPM (Active State
72ea5f9fc5SMatthew Garrett	  Power Management) and Clock Power Management. ASPM supports
73ea5f9fc5SMatthew Garrett	  state L0/L0s/L1.
747d715a6cSShaohua Li
75d56641c7SP. Christeas	  ASPM is initially set up by the firmware. With this option enabled,
76ea5f9fc5SMatthew Garrett	  Linux can modify this state in order to disable ASPM on known-bad
77ea5f9fc5SMatthew Garrett	  hardware or configurations and enable it when known-safe.
78ea5f9fc5SMatthew Garrett
79ea5f9fc5SMatthew Garrett	  ASPM can be disabled or enabled at runtime via
80ea5f9fc5SMatthew Garrett	  /sys/module/pcie_aspm/parameters/policy
81ea5f9fc5SMatthew Garrett
82ea5f9fc5SMatthew Garrett	  When in doubt, say Y.
83cc73176cSAndreas Ziegler
84ad71c962SMatthew Garrettchoice
85ad71c962SMatthew Garrett	prompt "Default ASPM policy"
86ad71c962SMatthew Garrett	default PCIEASPM_DEFAULT
87ad71c962SMatthew Garrett	depends on PCIEASPM
88ad71c962SMatthew Garrett
89ad71c962SMatthew Garrettconfig PCIEASPM_DEFAULT
90ad71c962SMatthew Garrett	bool "BIOS default"
91ad71c962SMatthew Garrett	depends on PCIEASPM
92ad71c962SMatthew Garrett	help
93ad71c962SMatthew Garrett	  Use the BIOS defaults for PCI Express ASPM.
94ad71c962SMatthew Garrett
95ad71c962SMatthew Garrettconfig PCIEASPM_POWERSAVE
96ad71c962SMatthew Garrett	bool "Powersave"
97ad71c962SMatthew Garrett	depends on PCIEASPM
98ad71c962SMatthew Garrett	help
99ad71c962SMatthew Garrett	  Enable PCI Express ASPM L0s and L1 where possible, even if the
100ad71c962SMatthew Garrett	  BIOS did not.
101ad71c962SMatthew Garrett
102b2103ccbSRajat Jainconfig PCIEASPM_POWER_SUPERSAVE
103b2103ccbSRajat Jain	bool "Power Supersave"
104b2103ccbSRajat Jain	depends on PCIEASPM
105b2103ccbSRajat Jain	help
106b2103ccbSRajat Jain	  Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where
107b2103ccbSRajat Jain	  possible. This would result in higher power savings while staying in L1
108b2103ccbSRajat Jain	  where the components support it.
109b2103ccbSRajat Jain
110ad71c962SMatthew Garrettconfig PCIEASPM_PERFORMANCE
111ad71c962SMatthew Garrett	bool "Performance"
112ad71c962SMatthew Garrett	depends on PCIEASPM
113ad71c962SMatthew Garrett	help
114ad71c962SMatthew Garrett	  Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
115ad71c962SMatthew Garrettendchoice
116ad71c962SMatthew Garrett
117c7f48656SRafael J. Wysockiconfig PCIE_PME
118c7f48656SRafael J. Wysocki	def_bool y
119fbb988beSRafael J. Wysocki	depends on PCIEPORTBUS && PM
12026e51571SKeith Busch
12126e51571SKeith Buschconfig PCIE_DPC
1220b15f1e3SBjorn Helgaas	bool "PCI Express Downstream Port Containment support"
123eed85ff4SKeith Busch	depends on PCIEPORTBUS && PCIEAER
12426e51571SKeith Busch	help
12526e51571SKeith Busch	  This enables PCI Express Downstream Port Containment (DPC)
12626e51571SKeith Busch	  driver support.  DPC events from Root and Downstream ports
12726e51571SKeith Busch	  will be handled by the DPC driver.  If your system doesn't
12826e51571SKeith Busch	  have this capability or you do not want to use this feature,
12926e51571SKeith Busch	  it is safe to answer N.
1309bb04a0cSJonathan Yong
1319bb04a0cSJonathan Yongconfig PCIE_PTM
1320b15f1e3SBjorn Helgaas	bool "PCI Express Precision Time Measurement support"
1339bb04a0cSJonathan Yong	help
1349bb04a0cSJonathan Yong	  This enables PCI Express Precision Time Measurement (PTM)
1359bb04a0cSJonathan Yong	  support.
1369bb04a0cSJonathan Yong
1379bb04a0cSJonathan Yong	  This is only useful if you have devices that support PTM, but it
1389bb04a0cSJonathan Yong	  is safe to enable even if you don't.
1392078e1e7SKeith Busch
140ac1c8e35SKuppuswamy Sathyanarayananconfig PCIE_EDR
141ac1c8e35SKuppuswamy Sathyanarayanan	bool "PCI Express Error Disconnect Recover support"
142ac1c8e35SKuppuswamy Sathyanarayanan	depends on PCIE_DPC && ACPI
143ac1c8e35SKuppuswamy Sathyanarayanan	help
144ac1c8e35SKuppuswamy Sathyanarayanan	  This option adds Error Disconnect Recover support as specified
145ac1c8e35SKuppuswamy Sathyanarayanan	  in the Downstream Port Containment Related Enhancements ECN to
146ac1c8e35SKuppuswamy Sathyanarayanan	  the PCI Firmware Specification r3.2.  Enable this if you want to
147ac1c8e35SKuppuswamy Sathyanarayanan	  support hybrid DPC model which uses both firmware and OS to
148ac1c8e35SKuppuswamy Sathyanarayanan	  implement DPC.
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