18a9fd832SMathieu Poirier /* SPDX-License-Identifier: GPL-2.0 */ 20bcbf2e3SMathieu Poirier /* 30bcbf2e3SMathieu Poirier * Copyright(C) 2015 Linaro Limited. All rights reserved. 40bcbf2e3SMathieu Poirier * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 50bcbf2e3SMathieu Poirier */ 60bcbf2e3SMathieu Poirier 70bcbf2e3SMathieu Poirier #ifndef _LINUX_CORESIGHT_PMU_H 80bcbf2e3SMathieu Poirier #define _LINUX_CORESIGHT_PMU_H 90bcbf2e3SMathieu Poirier 10*aa19bb4cSMike Leach #include <linux/bits.h> 11*aa19bb4cSMike Leach 120bcbf2e3SMathieu Poirier #define CORESIGHT_ETM_PMU_NAME "cs_etm" 130bcbf2e3SMathieu Poirier 1453abf3feSLeo Yan /* 15338a588eSMike Leach * The legacy Trace ID system based on fixed calculation from the cpu 16338a588eSMike Leach * number. This has been replaced by drivers using a dynamic allocation 17338a588eSMike Leach * system - but need to retain the legacy algorithm for backward comparibility 18338a588eSMike Leach * in certain situations:- 19338a588eSMike Leach * a) new perf running on older systems that generate the legacy mapping 20338a588eSMike Leach * b) older tools that may not update at the same time as the kernel. 21338a588eSMike Leach */ 22338a588eSMike Leach #define CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) (0x10 + (cpu * 2)) 23338a588eSMike Leach 24338a588eSMike Leach /* 2553abf3feSLeo Yan * Below are the definition of bit offsets for perf option, and works as 2653abf3feSLeo Yan * arbitrary values for all ETM versions. 2753abf3feSLeo Yan * 2853abf3feSLeo Yan * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore, 2953abf3feSLeo Yan * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and 3053abf3feSLeo Yan * directly use below macros as config bits. 3153abf3feSLeo Yan */ 322d693ed4SJames Clark #define ETM_OPT_BRANCH_BROADCAST 8 330bcbf2e3SMathieu Poirier #define ETM_OPT_CYCACC 12 3482500a81SMathieu Poirier #define ETM_OPT_CTXTID 14 3588f11864SSuzuki K Poulose #define ETM_OPT_CTXTID2 15 360bcbf2e3SMathieu Poirier #define ETM_OPT_TS 28 37b97971beSMike Leach #define ETM_OPT_RETSTK 29 380bcbf2e3SMathieu Poirier 39df770ff0SMike Leach /* ETMv4 CONFIGR programming bits for the ETM OPTs */ 402d693ed4SJames Clark #define ETM4_CFG_BIT_BB 3 41df770ff0SMike Leach #define ETM4_CFG_BIT_CYCACC 4 4282500a81SMathieu Poirier #define ETM4_CFG_BIT_CTXTID 6 4388f11864SSuzuki K Poulose #define ETM4_CFG_BIT_VMID 7 44df770ff0SMike Leach #define ETM4_CFG_BIT_TS 11 45df770ff0SMike Leach #define ETM4_CFG_BIT_RETSTK 12 4688f11864SSuzuki K Poulose #define ETM4_CFG_BIT_VMID_OPT 15 47df770ff0SMike Leach 48*aa19bb4cSMike Leach /* 49*aa19bb4cSMike Leach * Interpretation of the PERF_RECORD_AUX_OUTPUT_HW_ID payload. 50*aa19bb4cSMike Leach * Used to associate a CPU with the CoreSight Trace ID. 51*aa19bb4cSMike Leach * [07:00] - Trace ID - uses 8 bits to make value easy to read in file. 52*aa19bb4cSMike Leach * [59:08] - Unused (SBZ) 53*aa19bb4cSMike Leach * [63:60] - Version 54*aa19bb4cSMike Leach */ 55*aa19bb4cSMike Leach #define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0) 56*aa19bb4cSMike Leach #define CS_AUX_HW_ID_VERSION_MASK GENMASK_ULL(63, 60) 57*aa19bb4cSMike Leach 58*aa19bb4cSMike Leach #define CS_AUX_HW_ID_CURR_VERSION 0 59*aa19bb4cSMike Leach 600bcbf2e3SMathieu Poirier #endif 61