10fa9e329SBin Meng /* 20fa9e329SBin Meng * QEMU SiFive U OTP (One-Time Programmable) Memory interface 30fa9e329SBin Meng * 40fa9e329SBin Meng * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 50fa9e329SBin Meng * 60fa9e329SBin Meng * This program is free software; you can redistribute it and/or modify it 70fa9e329SBin Meng * under the terms and conditions of the GNU General Public License, 80fa9e329SBin Meng * version 2 or later, as published by the Free Software Foundation. 90fa9e329SBin Meng * 100fa9e329SBin Meng * This program is distributed in the hope it will be useful, but WITHOUT 110fa9e329SBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 120fa9e329SBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 130fa9e329SBin Meng * more details. 140fa9e329SBin Meng * 150fa9e329SBin Meng * You should have received a copy of the GNU General Public License along with 160fa9e329SBin Meng * this program. If not, see <http://www.gnu.org/licenses/>. 170fa9e329SBin Meng */ 180fa9e329SBin Meng 190fa9e329SBin Meng #ifndef HW_SIFIVE_U_OTP_H 200fa9e329SBin Meng #define HW_SIFIVE_U_OTP_H 21*7a5951f6SMarkus Armbruster 22*7a5951f6SMarkus Armbruster #include "hw/sysbus.h" 230fa9e329SBin Meng 240fa9e329SBin Meng #define SIFIVE_U_OTP_PA 0x00 250fa9e329SBin Meng #define SIFIVE_U_OTP_PAIO 0x04 260fa9e329SBin Meng #define SIFIVE_U_OTP_PAS 0x08 270fa9e329SBin Meng #define SIFIVE_U_OTP_PCE 0x0C 280fa9e329SBin Meng #define SIFIVE_U_OTP_PCLK 0x10 290fa9e329SBin Meng #define SIFIVE_U_OTP_PDIN 0x14 300fa9e329SBin Meng #define SIFIVE_U_OTP_PDOUT 0x18 310fa9e329SBin Meng #define SIFIVE_U_OTP_PDSTB 0x1C 320fa9e329SBin Meng #define SIFIVE_U_OTP_PPROG 0x20 330fa9e329SBin Meng #define SIFIVE_U_OTP_PTC 0x24 340fa9e329SBin Meng #define SIFIVE_U_OTP_PTM 0x28 350fa9e329SBin Meng #define SIFIVE_U_OTP_PTM_REP 0x2C 360fa9e329SBin Meng #define SIFIVE_U_OTP_PTR 0x30 370fa9e329SBin Meng #define SIFIVE_U_OTP_PTRIM 0x34 380fa9e329SBin Meng #define SIFIVE_U_OTP_PWE 0x38 390fa9e329SBin Meng 40a54d2591SGreen Wan #define SIFIVE_U_OTP_PWE_EN (1 << 0) 41a54d2591SGreen Wan 420fa9e329SBin Meng #define SIFIVE_U_OTP_PCE_EN (1 << 0) 430fa9e329SBin Meng 440fa9e329SBin Meng #define SIFIVE_U_OTP_PDSTB_EN (1 << 0) 450fa9e329SBin Meng 460fa9e329SBin Meng #define SIFIVE_U_OTP_PTRIM_EN (1 << 0) 470fa9e329SBin Meng 480fa9e329SBin Meng #define SIFIVE_U_OTP_PA_MASK 0xfff 490fa9e329SBin Meng #define SIFIVE_U_OTP_NUM_FUSES 0x1000 5051b6c1bbSGreen Wan #define SIFIVE_U_OTP_FUSE_WORD 4 510fa9e329SBin Meng #define SIFIVE_U_OTP_SERIAL_ADDR 0xfc 520fa9e329SBin Meng 530fa9e329SBin Meng #define SIFIVE_U_OTP_REG_SIZE 0x1000 540fa9e329SBin Meng 550fa9e329SBin Meng #define TYPE_SIFIVE_U_OTP "riscv.sifive.u.otp" 560fa9e329SBin Meng 57ac900edeSEduardo Habkost typedef struct SiFiveUOTPState SiFiveUOTPState; 58e38d3c5cSEduardo Habkost DECLARE_INSTANCE_CHECKER(SiFiveUOTPState, SIFIVE_U_OTP, 59e38d3c5cSEduardo Habkost TYPE_SIFIVE_U_OTP) 600fa9e329SBin Meng 61ac900edeSEduardo Habkost struct SiFiveUOTPState { 620fa9e329SBin Meng /*< private >*/ 630fa9e329SBin Meng SysBusDevice parent_obj; 640fa9e329SBin Meng 650fa9e329SBin Meng /*< public >*/ 660fa9e329SBin Meng MemoryRegion mmio; 670fa9e329SBin Meng uint32_t pa; 680fa9e329SBin Meng uint32_t paio; 690fa9e329SBin Meng uint32_t pas; 700fa9e329SBin Meng uint32_t pce; 710fa9e329SBin Meng uint32_t pclk; 720fa9e329SBin Meng uint32_t pdin; 730fa9e329SBin Meng uint32_t pdstb; 740fa9e329SBin Meng uint32_t pprog; 750fa9e329SBin Meng uint32_t ptc; 760fa9e329SBin Meng uint32_t ptm; 770fa9e329SBin Meng uint32_t ptm_rep; 780fa9e329SBin Meng uint32_t ptr; 790fa9e329SBin Meng uint32_t ptrim; 800fa9e329SBin Meng uint32_t pwe; 810fa9e329SBin Meng uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES]; 82a54d2591SGreen Wan uint32_t fuse_wo[SIFIVE_U_OTP_NUM_FUSES]; 830fa9e329SBin Meng /* config */ 840fa9e329SBin Meng uint32_t serial; 8551b6c1bbSGreen Wan BlockBackend *blk; 86ac900edeSEduardo Habkost }; 870fa9e329SBin Meng 880fa9e329SBin Meng #endif /* HW_SIFIVE_U_OTP_H */ 89