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/openbmc/linux/include/dt-bindings/reset/
H A Dimx8mq-reset.h31 #define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */
32 #define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */
33 #define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */
34 #define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */
35 #define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */
36 #define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */
37 #define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */
38 #define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */
39 #define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */
40 #define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/freescale/imx8mn/sys/
H A Dddrc.json7 "Compat": "i.MX8MN"
14 "Compat": "i.MX8MN"
21 "Compat": "i.MX8MN"
28 "Compat": "i.MX8MN"
35 "Compat": "i.MX8MN"
H A Dmetrics.json8 "Compat": "i.MX8MN"
16 "Compat": "i.MX8MN"
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-var-som-symphony.dts15 model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";
16 compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn";
H A Dimx8mn-tqma8mqnl.dtsi9 model = "TQ-Systems i.MX8MN TQMa8MxNL";
118 /* V_0V85_GPU / DRAM: shall be equal to BUCK1 for i.MX8MN */
H A Dimx8mn-var-som.dtsi11 model = "Variscite VAR-SOM-MX8MN module";
12 compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
H A Dimx8mn-tqma8mqnl-mba8mx.dts12 model = "TQ-Systems GmbH i.MX8MN TQMa8MxNL on MBa8Mx";
H A Dimx8mn-venice-gw7902.dts16 model = "Gateworks Venice GW7902 i.MX8MN board";
/openbmc/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mn-disp-blk-ctrl.yaml7 title: NXP i.MX8MN DISP blk-ctrl
13 The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to
/openbmc/linux/drivers/interconnect/imx/
H A DKconfig12 tristate "i.MX8MN interconnect driver"
H A Dimx8mn.c3 * Interconnect framework driver for i.MX8MN SoC
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dfsl.yaml1000 - description: i.MX8MN based Boards
1003 - beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit
1004 - bsh,imx8mn-bsh-smm-s2 # i.MX8MN BSH SystemMaster S2
1005 - bsh,imx8mn-bsh-smm-s2pro # i.MX8MN BSH SystemMaster S2 PRO
1006 - fsl,imx8mn-ddr3l-evk # i.MX8MN DDR3L EVK Board
1007 - fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
1008 - fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
1012 - description: Variscite VAR-SOM-MX8MN based boards
1014 - const: variscite,var-som-mx8mn-symphony
1015 - const: variscite,var-som-mx8mn
[all …]
/openbmc/linux/drivers/clk/imx/
H A DKconfig78 Build the driver for i.MX8MN CCM Clock Driver
H A Dclk-imx8mn.c601 dev_err(dev, "failed to register hws for i.MX8MN\n"); in imx8mn_clocks_probe()
638 MODULE_DESCRIPTION("NXP i.MX8MN clock driver");
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dfsl,imx7-src.yaml20 <dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ, i.MX8MM and i.MX8MN,
/openbmc/linux/Documentation/devicetree/bindings/nvmem/
H A Dimx-ocotp.yaml15 i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN i.MX8MP and i.MX93 SoCs.
/openbmc/linux/drivers/media/platform/nxp/imx8-isi/
H A Dimx8-isi-gasket.c13 * i.MX8MN and i.MX8MP gasket
H A Dimx8-isi-core.c248 /* For i.MX8QXP C0 and i.MX8MN ISI IER version */
H A Dimx8-isi-hw.c338 * reserved in the i.MX8MN reference manual. in mxc_isi_channel_set_control()
/openbmc/linux/drivers/soc/imx/
H A Dsoc-imx8m.c193 .name = "i.MX8MN",
/openbmc/linux/drivers/pinctrl/freescale/
H A Dpinctrl-imx8mn.c353 MODULE_DESCRIPTION("NXP i.MX8MN pinctrl driver");
/openbmc/linux/drivers/perf/
H A Dfsl_imx8_ddr_perf.c77 .identifier = "i.MX8MN",