Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24 |
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#
188d070d |
| 10-Apr-2023 |
Hao Luo <m202171776@hust.edu.cn> |
clk: imx: clk-imx8mn: fix memory leak in imx8mn_clocks_probe
Use devm_of_iomap() instead of of_iomap() to automatically handle the unused ioremap region.
If any error occurs, regions allocated by k
clk: imx: clk-imx8mn: fix memory leak in imx8mn_clocks_probe
Use devm_of_iomap() instead of of_iomap() to automatically handle the unused ioremap region.
If any error occurs, regions allocated by kzalloc() will leak, but using devm_kzalloc() instead will automatically free the memory using devm_kfree().
Fixes: daeb14545514 ("clk: imx: imx8mn: Switch to clk_hw based API") Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Hao Luo <m202171776@hust.edu.cn> Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230411015107.2645-1-m202171776@hust.edu.cn Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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Revision tags: v6.1.23, v6.1.22 |
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#
46a97443 |
| 23-Mar-2023 |
Adam Ford <aford173@gmail.com> |
clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate
By default the display pixel clock needs to be evenly divide down from the video_pll_out clock which rules out a significant number of resolution
clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate
By default the display pixel clock needs to be evenly divide down from the video_pll_out clock which rules out a significant number of resolution and refresh rates.
The current clock tree looks something like:
video_pll 594000000 video_pll_bypass 594000000 video_pll_out 594000000 disp_pixel 148500000 disp_pixel_clk 148500000
Now that composite-8m supports determine_rate, we can allow disp_pixel to set the parent rate which then switches every clock in the chain to a new frequency when disp_pixel cannot evenly divide from video_pll_out.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230323230127.120883-5-aford173@gmail.com
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Revision tags: v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4 |
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#
2d5513bf |
| 04-Jan-2023 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: remove clk_count of imx_register_uart_clocks
The clk count has been get with of_clk_get_parent_count, there is no need to pass clk_count from users.
Signed-off-by: Peng Fan <peng.fan@nxp.
clk: imx: remove clk_count of imx_register_uart_clocks
The clk count has been get with of_clk_get_parent_count, there is no need to pass clk_count from users.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230104110032.1220721-4-peng.fan@oss.nxp.com
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Revision tags: v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79 |
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#
8178e245 |
| 13-Nov-2022 |
Dario Binacchi <dario.binacchi@amarulasolutions.com> |
clk: imx: rename imx_obtain_fixed_clk_hw() to imx_get_clk_hw_by_name()
The imx_obtain_fixed_clk_hw name was wrong and misleading. Renaming it to imx_get_clk_hw_by_name clarifies the purpose of the f
clk: imx: rename imx_obtain_fixed_clk_hw() to imx_get_clk_hw_by_name()
The imx_obtain_fixed_clk_hw name was wrong and misleading. Renaming it to imx_get_clk_hw_by_name clarifies the purpose of the function, and will allow it to be used not only for fixed rate clocks but also in wider contexts.
No functional changes intended.
The replacements were made with the following command:
grep -rl 'imx_obtain_fixed_clk_hw' ./ | \ xargs sed -i 's/imx_obtain_fixed_clk_hw/imx_get_clk_hw_by_name/g'
Tested on a BSH SystemMaster (SMM) S2 board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20221113180839.1625832-1-dario.binacchi@amarulasolutions.com
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#
2626cf67 |
| 17-Nov-2022 |
Dario Binacchi <dario.binacchi@amarulasolutions.com> |
clk: imx8mn: fix imx8mn_enet_phy_sels clocks list
According to the "Clock Root" table of the reference manual (document IMX8MNRM Rev 2, 07/2022):
Clock Root offset Source Select (C
clk: imx8mn: fix imx8mn_enet_phy_sels clocks list
According to the "Clock Root" table of the reference manual (document IMX8MNRM Rev 2, 07/2022):
Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX]) ... ... ... ENET_PHY_REF_CLK_ROOT 0xAA80 000 - 24M_REF_CLK 001 - SYSTEM_PLL2_DIV20 010 - SYSTEM_PLL2_DIV8 011 - SYSTEM_PLL2_DIV5 100 - SYSTEM_PLL2_DIV2 101 - AUDIO_PLL1_CLK 110 - VIDEO_PLL_CLK 111 - AUDIO_PLL2_CLK ... ... ...
while the imx8mn_enet_phy_sels list didn't contained audio_pll1_out for source select bits 101b.
Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20221117113637.1978703-6-dario.binacchi@amarulasolutions.com
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#
34d99674 |
| 17-Nov-2022 |
Dario Binacchi <dario.binacchi@amarulasolutions.com> |
clk: imx8mn: fix imx8mn_sai2_sels clocks list
According to the "Clock Root" table of the reference manual (document IMX8MNRM Rev 2, 07/2022):
Clock Root offset Source Select (CCM_TARGE
clk: imx8mn: fix imx8mn_sai2_sels clocks list
According to the "Clock Root" table of the reference manual (document IMX8MNRM Rev 2, 07/2022):
Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX]) ... ... ... SAI2_CLK_ROOT 0xA600 000 - 24M_REF_CLK 001 - AUDIO_PLL1_CLK 010 - AUDIO_PLL2_CLK 011 - VIDEO_PLL_CLK 100 - SYSTEM_PLL1_DIV6 110 - EXT_CLK_2 111 - EXT_CLK_3 ... ... ...
while the imx8mn_sai2_sels list contained clk_ext3 and clk_ext4 for source select bits 110b and 111b.
Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20221117113637.1978703-5-dario.binacchi@amarulasolutions.com
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#
bedcf9d1 |
| 17-Nov-2022 |
Dario Binacchi <dario.binacchi@amarulasolutions.com> |
clk: imx: rename video_pll1 to video_pll
Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's rename "video_pll1" to "video_pll" to be c
clk: imx: rename video_pll1 to video_pll
Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's rename "video_pll1" to "video_pll" to be consistent with the RM and avoid misunderstandings.
The IMX8MN_VIDEO_PLL1* constants have not been removed to ensure backward compatibility of the patch.
No functional changes intended.
Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20221117113637.1978703-4-dario.binacchi@amarulasolutions.com
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#
e7fa365f |
| 17-Nov-2022 |
Dario Binacchi <dario.binacchi@amarulasolutions.com> |
clk: imx: replace osc_hdmi with dummy
There is no occurrence of the hdmi oscillator in the reference manual (document IMX8MNRM Rev 2, 07/2022). Further, if we consider the indexes 76-81 and 134 of t
clk: imx: replace osc_hdmi with dummy
There is no occurrence of the hdmi oscillator in the reference manual (document IMX8MNRM Rev 2, 07/2022). Further, if we consider the indexes 76-81 and 134 of the "Clock Root" table of chapter 5 of the RM, there is no entry for the source select bits 101b, which is the setting referenced by "osc_hdmi". Fix by renaming "osc_hdmi" with "dummy", a clock which has already been used for missing source select bits.
Tested on the BSH SystemMaster (SMM) S2 board.
Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20221117113637.1978703-3-dario.binacchi@amarulasolutions.com
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#
a429c60b |
| 17-Nov-2022 |
Dario Binacchi <dario.binacchi@amarulasolutions.com> |
clk: imx8mn: rename vpu_pll to m7_alt_pll
The IMX8MN platform does not have any video processing unit (VPU), and indeed in the reference manual (document IMX8MNRM Rev 2, 07/2022) there is no occurre
clk: imx8mn: rename vpu_pll to m7_alt_pll
The IMX8MN platform does not have any video processing unit (VPU), and indeed in the reference manual (document IMX8MNRM Rev 2, 07/2022) there is no occurrence of its pll. From an analysis of the code and the RM itself, I think vpu pll is used instead of m7 alternate pll, probably for copy and paste of code taken from modules of similar architectures.
As an example for all, if we consider the second row of the "Clock Root" table of chapter 5 (Clocks and Power Management) of the RM:
Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX]) ... ... ... ARM_M7_CLK_ROOT 0x8080 000 - 24M_REF_CLK 001 - SYSTEM_PLL2_DIV5 010 - SYSTEM_PLL2_DIV4 011 - M7_ALT_PLL_CLK 100 - SYSTEM_PLL1_CLK 101 - AUDIO_PLL1_CLK 110 - VIDEO_PLL_CLK 111 - SYSTEM_PLL3_CLK ... ... ...
but in the source code, the imx8mn_m7_sels clocks list contains vpu_pll for the source select bits 011b.
So, let's rename "vpu_pll" to "m7_alt_pll" to be consistent with the RM.
The IMX8MN_VPU_* constants have not been removed to ensure backward compatibility of the patch.
No functional changes intended.
Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20221117113637.1978703-2-dario.binacchi@amarulasolutions.com
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Revision tags: v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30 |
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#
ce0fc2f0 |
| 17-Mar-2022 |
Alvin Šipraga <alsi@bang-olufsen.dk> |
clk: imx8mn: add GPT support
Add support for the General Purpose Timer (GPT) clocks on the i.MX8MN. The i.MX8MN GPT IP block is the same as on the i.MX8MM, on which this patch is based.
Signed-off-
clk: imx8mn: add GPT support
Add support for the General Purpose Timer (GPT) clocks on the i.MX8MN. The i.MX8MN GPT IP block is the same as on the i.MX8MM, on which this patch is based.
Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220317223600.175894-2-alvin@pqrs.dk Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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Revision tags: v5.15.29, v5.15.28 |
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#
56fddc69 |
| 10-Mar-2022 |
Jacky Bai <ping.bai@nxp.com> |
clk: imx: Remove the snvs clock
The SNVS moudule is not used only by the linux, it may also used by other SW component is secure world. No sense to populate it in linux, so remove it.
Signed-off-by
clk: imx: Remove the snvs clock
The SNVS moudule is not used only by the linux, it may also used by other SW component is secure world. No sense to populate it in linux, so remove it.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220310093404.236966-1-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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Revision tags: v5.15.27, v5.15.26 |
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#
19565ea1 |
| 28-Feb-2022 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: add mcore_booted module paratemter
Add mcore_booted boot parameter which could simplify AMP clock management. To i.MX8M, there is CCM(clock control Module) to generate clock root clock, an
clk: imx: add mcore_booted module paratemter
Add mcore_booted boot parameter which could simplify AMP clock management. To i.MX8M, there is CCM(clock control Module) to generate clock root clock, anatop(analog PLL module) to generate PLL, and CCGR (clock gating) to gate clocks to peripherals. As below: anatop->ccm->ccgr->peripheral
Linux handles the clock management and the auxiliary core is under control of Linux. Although there is per hardware domain control for CCGR and CCM, auxiliary core normally only use CCGR hardware domain control to avoid linux gate off the clk to peripherals and leave CCM ana anatop to Linux.
Per NXP hardware design, because CCGR already support gate to peripherals, and clk root gate power leakage is negligible. So when in AMP case, we could not register the clk root gate.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220228124112.3974242-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
38ce00ad |
| 25-Feb-2022 |
Peng Fan <peng.fan@nxp.com> |
clk: imx8mn: remove SYS PLL 1/2 clock gates
Remove the PLL 1/2 gates as it make AMP clock management harder without obvious benifit.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Ves
clk: imx8mn: remove SYS PLL 1/2 clock gates
Remove the PLL 1/2 gates as it make AMP clock management harder without obvious benifit.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220225081733.2294166-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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Revision tags: v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3 |
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#
570727e9 |
| 17-Nov-2021 |
Adam Ford <aford173@gmail.com> |
clk: imx8mn: Fix imx8mn_clko1_sels
When attempting to use sys_pll1_80m as the parent for clko1, the system hangs. This is due to the fact that the source select for sys_pll1_80m was incorrectly poi
clk: imx8mn: Fix imx8mn_clko1_sels
When attempting to use sys_pll1_80m as the parent for clko1, the system hangs. This is due to the fact that the source select for sys_pll1_80m was incorrectly pointing to m7_alt_pll_clk, which doesn't yet exist.
According to Rev 3 of the TRM, The imx8mn_clko1_sels also incorrectly references an osc_27m which does not exist, nor does an entry for source select bits 010b. Fix both by inserting a dummy clock into the missing space in the table and renaming the incorrectly name clock with dummy.
Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20211117133202.775633-1-aford173@gmail.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
e459a89d |
| 17-Nov-2021 |
Adam Ford <aford173@gmail.com> |
clk: imx8mn: Fix imx8mn_clko1_sels
[ Upstream commit 570727e9acfac1c2330a01dd5e1272e9c3acec08 ]
When attempting to use sys_pll1_80m as the parent for clko1, the system hangs. This is due to the fa
clk: imx8mn: Fix imx8mn_clko1_sels
[ Upstream commit 570727e9acfac1c2330a01dd5e1272e9c3acec08 ]
When attempting to use sys_pll1_80m as the parent for clko1, the system hangs. This is due to the fact that the source select for sys_pll1_80m was incorrectly pointing to m7_alt_pll_clk, which doesn't yet exist.
According to Rev 3 of the TRM, The imx8mn_clko1_sels also incorrectly references an osc_27m which does not exist, nor does an entry for source select bits 010b. Fix both by inserting a dummy clock into the missing space in the table and renaming the incorrectly name clock with dummy.
Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20211117133202.775633-1-aford173@gmail.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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Revision tags: v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61 |
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#
86842d25 |
| 19-Aug-2021 |
Marek Vasut <marex@denx.de> |
clk: imx8mn: Add M7 core clock
Add missing M7 core clock entry to the iMX8MN clock driver.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Fabio E
clk: imx8mn: Add M7 core clock
Add missing M7 core clock entry to the iMX8MN clock driver.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Cc: Abel Vesa <abel.vesa@nxp.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Link: https://lore.kernel.org/r/20210819202036.2084782-1-marex@denx.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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Revision tags: v5.10.60 |
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#
d36207b8 |
| 10-Aug-2021 |
Ahmad Fatoum <a.fatoum@pengutronix.de> |
clk: imx8m: fix clock tree update of TF-A managed clocks
On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the SiP and
clk: imx8m: fix clock tree update of TF-A managed clocks
On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the SiP and then does clk_set_parent on the DDR muxes to synchronize the clock tree.
Since 936c383673b9 ("clk: imx: fix composite peripheral flags"), these TF-A managed muxes have SET_PARENT_GATE set, which results in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY:
echo 25000000 > userspace/set_freq imx8m-ddrc-devfreq 3d400000.memory-controller: failed to set dram_apb parent: -16
Fix this by adding a new i.MX composite flag for firmware managed clocks, which clears SET_PARENT_GATE.
This is safe to do, because updating the Linux clock tree to reflect reality will always be glitch-free.
Fixes: 936c383673b9 ("clk: imx: fix composite peripheral flags") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210810151432.9228-1-a.fatoum@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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Revision tags: v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49 |
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8ee749ec |
| 28-Jun-2021 |
Lucas Stach <l.stach@pengutronix.de> |
clk: imx8mn: use correct mux type for clkout path
The mux in the clkout path needs the current selected parent to be enabled for the switch to work. Use the correct mux type to have the clk framewor
clk: imx8mn: use correct mux type for clkout path
The mux in the clkout path needs the current selected parent to be enabled for the switch to work. Use the correct mux type to have the clk framework take care of this requirement.
Fixes: af4df655040 ("clk: imx8mn: add clkout1/2 support") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210628211554.2510238-2-l.stach@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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Revision tags: v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24 |
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#
379c9a24 |
| 13-Mar-2021 |
Adam Ford <aford173@gmail.com> |
clk: imx: Fix reparenting of UARTs not associated with stdout
Most if not all i.MX SoC's call a function which enables all UARTS. This is a problem for users who need to re-parent the clock source,
clk: imx: Fix reparenting of UARTs not associated with stdout
Most if not all i.MX SoC's call a function which enables all UARTS. This is a problem for users who need to re-parent the clock source, because any attempt to change the parent results in an busy error due to the fact that the clocks have been enabled already.
clk: failed to reparent uart1 to sys_pll1_80m: -16
Instead of pre-initializing all UARTS, scan the device tree to see which UART clocks are associated to stdout, and only enable those UART clocks if it's needed early. This will move initialization of the remaining clocks until after the parenting of the clocks.
When the clocks are shutdown, this mechanism will also disable any clocks that were pre-initialized.
Fixes: 9461f7b33d11c ("clk: fix CLK_SET_RATE_GATE with clock rate protection") Suggested-by: Aisheng Dong <aisheng.dong@nxp.com> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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Revision tags: v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14 |
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3af4df65 |
| 25-Jan-2021 |
Lucas Stach <l.stach@pengutronix.de> |
clk: imx8mn: add clkout1/2 support
clkout1 and clkout2 allow to supply clocks from the SoC to the board, which is used by some board designs to provide reference clocks.
Signed-off-by: Lucas Stach
clk: imx8mn: add clkout1/2 support
clkout1 and clkout2 allow to supply clocks from the SoC to the board, which is used by some board designs to provide reference clocks.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v5.10 |
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8f8a3230 |
| 03-Nov-2020 |
Krzysztof Kozlowski <krzk@kernel.org> |
clk: imx8mn: drop of_match_ptr from of_device_id table
The driver can match only via the DT table so the table should be always used and the of_match_ptr does not have any sense (this also allows AC
clk: imx8mn: drop of_match_ptr from of_device_id table
The driver can match only via the DT table so the table should be always used and the of_match_ptr does not have any sense (this also allows ACPI matching via PRP0001, even though it might be not relevant here). This fixes compile warning (!CONFIG_OF && !CONFIG_MODULES):
drivers/clk/imx/clk-imx8mn.c:592:34: warning: ‘imx8mn_clk_of_match’ defined but not used [-Wunused-const-variable=]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
926bf912 |
| 10-Aug-2021 |
Ahmad Fatoum <a.fatoum@pengutronix.de> |
clk: imx8m: fix clock tree update of TF-A managed clocks
[ Upstream commit d36207b848a6490e14664e2197a1c8ab51d8148e ]
On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service for DDR frequ
clk: imx8m: fix clock tree update of TF-A managed clocks
[ Upstream commit d36207b848a6490e14664e2197a1c8ab51d8148e ]
On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the SiP and then does clk_set_parent on the DDR muxes to synchronize the clock tree.
Since 936c383673b9 ("clk: imx: fix composite peripheral flags"), these TF-A managed muxes have SET_PARENT_GATE set, which results in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY:
echo 25000000 > userspace/set_freq imx8m-ddrc-devfreq 3d400000.memory-controller: failed to set dram_apb parent: -16
Fix this by adding a new i.MX composite flag for firmware managed clocks, which clears SET_PARENT_GATE.
This is safe to do, because updating the Linux clock tree to reflect reality will always be glitch-free.
Fixes: 936c383673b9 ("clk: imx: fix composite peripheral flags") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210810151432.9228-1-a.fatoum@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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#
9e33e261 |
| 13-Mar-2021 |
Adam Ford <aford173@gmail.com> |
clk: imx: Fix reparenting of UARTs not associated with stdout
[ Upstream commit 379c9a24cc239000b1dec53db02fe17a86947423 ]
Most if not all i.MX SoC's call a function which enables all UARTS. This i
clk: imx: Fix reparenting of UARTs not associated with stdout
[ Upstream commit 379c9a24cc239000b1dec53db02fe17a86947423 ]
Most if not all i.MX SoC's call a function which enables all UARTS. This is a problem for users who need to re-parent the clock source, because any attempt to change the parent results in an busy error due to the fact that the clocks have been enabled already.
clk: failed to reparent uart1 to sys_pll1_80m: -16
Instead of pre-initializing all UARTS, scan the device tree to see which UART clocks are associated to stdout, and only enable those UART clocks if it's needed early. This will move initialization of the remaining clocks until after the parenting of the clocks.
When the clocks are shutdown, this mechanism will also disable any clocks that were pre-initialized.
Fixes: 9461f7b33d11c ("clk: fix CLK_SET_RATE_GATE with clock rate protection") Suggested-by: Aisheng Dong <aisheng.dong@nxp.com> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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#
c277ca15 |
| 01-Nov-2020 |
Peng Fan <peng.fan@nxp.com> |
clk: imx8m: fix bus critical clk registration
noc/axi/ahb are bus clk, not peripheral clk. Since peripheral clk has a limitation that for peripheral clock slice, IP clock slices must be stopped to c
clk: imx8m: fix bus critical clk registration
noc/axi/ahb are bus clk, not peripheral clk. Since peripheral clk has a limitation that for peripheral clock slice, IP clock slices must be stopped to change the clock source.
However if the bus clk is marked as critical clk peripheral, the assigned clock parent operation will fail.
So we added CLK_SET_PARENT_GATE flag to avoid glitch.
And add imx8m_clk_hw_composite_bus_critical for bus critical clock usage
Fixes: 936c383673b9e ("clk: imx: fix composite peripheral flags") Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reported-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/1604229834-25594-1-git-send-email-peng.fan@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Revision tags: v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55 |
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9a976cd2 |
| 29-Jul-2020 |
Anson Huang <Anson.Huang@nxp.com> |
clk: imx8m: Support module build
Change configuration to "tristate", add module author, description and license to support building i.MX8M SoCs clock driver as module.
Signed-off-by: Anson Huang <A
clk: imx8m: Support module build
Change configuration to "tristate", add module author, description and license to support building i.MX8M SoCs clock driver as module.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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