1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/net/ti-dp83867.h>
12
13#include "imx8mn.dtsi"
14
15/ {
16	model = "Gateworks Venice GW7902 i.MX8MN board";
17	compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
18
19	aliases {
20		usb0 = &usbotg1;
21	};
22
23	chosen {
24		stdout-path = &uart2;
25	};
26
27	memory@40000000 {
28		device_type = "memory";
29		reg = <0x0 0x40000000 0 0x80000000>;
30	};
31
32	can20m: can20m {
33		compatible = "fixed-clock";
34		#clock-cells = <0>;
35		clock-frequency = <20000000>;
36		clock-output-names = "can20m";
37	};
38
39	gpio-keys {
40		compatible = "gpio-keys";
41
42		key-user-pb {
43			label = "user_pb";
44			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
45			linux,code = <BTN_0>;
46		};
47
48		key-user-pb1x {
49			label = "user_pb1x";
50			linux,code = <BTN_1>;
51			interrupt-parent = <&gsc>;
52			interrupts = <0>;
53		};
54
55		key-erased {
56			label = "key_erased";
57			linux,code = <BTN_2>;
58			interrupt-parent = <&gsc>;
59			interrupts = <1>;
60		};
61
62		key-eeprom-wp {
63			label = "eeprom_wp";
64			linux,code = <BTN_3>;
65			interrupt-parent = <&gsc>;
66			interrupts = <2>;
67		};
68
69		key-tamper {
70			label = "tamper";
71			linux,code = <BTN_4>;
72			interrupt-parent = <&gsc>;
73			interrupts = <5>;
74		};
75
76		switch-hold {
77			label = "switch_hold";
78			linux,code = <BTN_5>;
79			interrupt-parent = <&gsc>;
80			interrupts = <7>;
81		};
82	};
83
84	led-controller {
85		compatible = "gpio-leds";
86		pinctrl-names = "default";
87		pinctrl-0 = <&pinctrl_gpio_leds>;
88
89		led-0 {
90			function = LED_FUNCTION_STATUS;
91			color = <LED_COLOR_ID_GREEN>;
92			label = "panel1";
93			gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
94			default-state = "off";
95		};
96
97		led-1 {
98			function = LED_FUNCTION_STATUS;
99			color = <LED_COLOR_ID_GREEN>;
100			label = "panel2";
101			gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
102			default-state = "off";
103		};
104
105		led-2 {
106			function = LED_FUNCTION_STATUS;
107			color = <LED_COLOR_ID_GREEN>;
108			label = "panel3";
109			gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
110			default-state = "off";
111		};
112
113		led-3 {
114			function = LED_FUNCTION_STATUS;
115			color = <LED_COLOR_ID_GREEN>;
116			label = "panel4";
117			gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
118			default-state = "off";
119		};
120
121		led-4 {
122			function = LED_FUNCTION_STATUS;
123			color = <LED_COLOR_ID_GREEN>;
124			label = "panel5";
125			gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
126			default-state = "off";
127		};
128	};
129
130	pps {
131		compatible = "pps-gpio";
132		pinctrl-names = "default";
133		pinctrl-0 = <&pinctrl_pps>;
134		gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
135		status = "okay";
136	};
137
138	reg_3p3v: regulator-3p3v {
139		compatible = "regulator-fixed";
140		regulator-name = "3P3V";
141		regulator-min-microvolt = <3300000>;
142		regulator-max-microvolt = <3300000>;
143		regulator-always-on;
144	};
145
146	reg_usb1_vbus: regulator-usb1 {
147		compatible = "regulator-fixed";
148		pinctrl-names = "default";
149		pinctrl-0 = <&pinctrl_reg_usb1>;
150		regulator-name = "usb_usb1_vbus";
151		gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
152		enable-active-high;
153		regulator-min-microvolt = <5000000>;
154		regulator-max-microvolt = <5000000>;
155	};
156
157	reg_wifi: regulator-wifi {
158		compatible = "regulator-fixed";
159		pinctrl-names = "default";
160		pinctrl-0 = <&pinctrl_reg_wl>;
161		regulator-name = "wifi";
162		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
163		enable-active-high;
164		startup-delay-us = <100>;
165		regulator-min-microvolt = <3300000>;
166		regulator-max-microvolt = <3300000>;
167	};
168};
169
170&A53_0 {
171	cpu-supply = <&buck2>;
172};
173
174&A53_1 {
175	cpu-supply = <&buck2>;
176};
177
178&A53_2 {
179	cpu-supply = <&buck2>;
180};
181
182&A53_3 {
183	cpu-supply = <&buck2>;
184};
185
186&ddrc {
187	operating-points-v2 = <&ddrc_opp_table>;
188
189	ddrc_opp_table: opp-table {
190		compatible = "operating-points-v2";
191
192		opp-25000000 {
193			opp-hz = /bits/ 64 <25000000>;
194		};
195
196		opp-100000000 {
197			opp-hz = /bits/ 64 <100000000>;
198		};
199
200		opp-750000000 {
201			opp-hz = /bits/ 64 <750000000>;
202		};
203	};
204};
205
206&ecspi1 {
207	pinctrl-names = "default";
208	pinctrl-0 = <&pinctrl_spi1>;
209	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
210	status = "okay";
211
212	can@0 {
213		compatible = "microchip,mcp2515";
214		reg = <0>;
215		clocks = <&can20m>;
216		interrupt-parent = <&gpio2>;
217		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
218		spi-max-frequency = <10000000>;
219	};
220};
221
222&disp_blk_ctrl {
223	status = "disabled";
224};
225
226/* off-board header */
227&ecspi2 {
228	pinctrl-names = "default";
229	pinctrl-0 = <&pinctrl_spi2>;
230	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
231	status = "okay";
232};
233
234&fec1 {
235	pinctrl-names = "default";
236	pinctrl-0 = <&pinctrl_fec1>;
237	phy-mode = "rgmii-id";
238	phy-handle = <&ethphy0>;
239	local-mac-address = [00 00 00 00 00 00];
240	status = "okay";
241
242	mdio {
243		#address-cells = <1>;
244		#size-cells = <0>;
245
246		ethphy0: ethernet-phy@0 {
247			compatible = "ethernet-phy-ieee802.3-c22";
248			reg = <0>;
249			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
250			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
251			tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
252			rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
253		};
254	};
255};
256
257&gpio1 {
258	gpio-line-names = "", "", "", "", "", "", "", "",
259		"m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
260		"", "", "", "", "", "", "", "",
261		"", "", "", "", "", "", "", "";
262};
263
264&gpio2 {
265	gpio-line-names = "", "", "", "", "", "", "", "",
266		"uart2_en#", "", "", "", "", "", "", "",
267		"", "", "", "", "", "", "", "",
268		"", "", "", "", "", "", "", "";
269};
270
271&gpio3 {
272	gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
273		"", "", "", "", "", "", "", "",
274		"", "", "", "", "", "", "", "",
275		"", "", "", "", "", "", "", "";
276};
277
278&gpio4 {
279	gpio-line-names = "", "", "", "", "", "", "", "",
280		"", "", "", "", "", "", "", "",
281		"", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
282		"", "uart1_term", "uart1_half", "app_gpio2",
283		"mipi_gpio1", "", "", "";
284};
285
286&gpio5 {
287	gpio-line-names = "", "", "", "mipi_gpio4",
288		"mipi_gpio3", "mipi_gpio2", "", "",
289		"", "", "", "", "", "", "", "",
290		"", "", "", "", "", "", "", "",
291		"", "", "", "", "", "", "", "";
292};
293
294&gpu {
295	status = "disabled";
296};
297
298&i2c1 {
299	clock-frequency = <100000>;
300	pinctrl-names = "default", "gpio";
301	pinctrl-0 = <&pinctrl_i2c1>;
302	pinctrl-1 = <&pinctrl_i2c1_gpio>;
303	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
304	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
305	status = "okay";
306
307	gsc: gsc@20 {
308		compatible = "gw,gsc";
309		reg = <0x20>;
310		pinctrl-0 = <&pinctrl_gsc>;
311		interrupt-parent = <&gpio2>;
312		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
313		interrupt-controller;
314		#interrupt-cells = <1>;
315
316		adc {
317			compatible = "gw,gsc-adc";
318			#address-cells = <1>;
319			#size-cells = <0>;
320
321			channel@6 {
322				gw,mode = <0>;
323				reg = <0x06>;
324				label = "temp";
325			};
326
327			channel@8 {
328				gw,mode = <3>;
329				reg = <0x08>;
330				label = "vdd_bat";
331			};
332
333			channel@82 {
334				gw,mode = <2>;
335				reg = <0x82>;
336				label = "vin";
337				gw,voltage-divider-ohms = <22100 1000>;
338				gw,voltage-offset-microvolt = <700000>;
339			};
340
341			channel@84 {
342				gw,mode = <2>;
343				reg = <0x84>;
344				label = "vin_4p0";
345				gw,voltage-divider-ohms = <10000 10000>;
346			};
347
348			channel@86 {
349				gw,mode = <2>;
350				reg = <0x86>;
351				label = "vdd_3p3";
352				gw,voltage-divider-ohms = <10000 10000>;
353			};
354
355			channel@88 {
356				gw,mode = <2>;
357				reg = <0x88>;
358				label = "vdd_0p9";
359			};
360
361			channel@8c {
362				gw,mode = <2>;
363				reg = <0x8c>;
364				label = "vdd_soc";
365			};
366
367			channel@8e {
368				gw,mode = <2>;
369				reg = <0x8e>;
370				label = "vdd_arm";
371			};
372
373			channel@90 {
374				gw,mode = <2>;
375				reg = <0x90>;
376				label = "vdd_1p8";
377			};
378
379			channel@92 {
380				gw,mode = <2>;
381				reg = <0x92>;
382				label = "vdd_dram";
383			};
384
385			channel@98 {
386				gw,mode = <2>;
387				reg = <0x98>;
388				label = "vdd_1p0";
389			};
390
391			channel@9a {
392				gw,mode = <2>;
393				reg = <0x9a>;
394				label = "vdd_2p5";
395				gw,voltage-divider-ohms = <10000 10000>;
396			};
397
398			channel@9c {
399				gw,mode = <2>;
400				reg = <0x9c>;
401				label = "vdd_5p0";
402				gw,voltage-divider-ohms = <10000 10000>;
403			};
404
405			channel@a2 {
406				gw,mode = <2>;
407				reg = <0xa2>;
408				label = "vdd_gsc";
409				gw,voltage-divider-ohms = <10000 10000>;
410			};
411		};
412	};
413
414	gpio: gpio@23 {
415		compatible = "nxp,pca9555";
416		reg = <0x23>;
417		gpio-controller;
418		#gpio-cells = <2>;
419		interrupt-parent = <&gsc>;
420		interrupts = <4>;
421	};
422
423	pmic@4b {
424		compatible = "rohm,bd71847";
425		reg = <0x4b>;
426		pinctrl-names = "default";
427		pinctrl-0 = <&pinctrl_pmic>;
428		interrupt-parent = <&gpio3>;
429		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
430		rohm,reset-snvs-powered;
431		#clock-cells = <0>;
432		clocks = <&osc_32k>;
433		clock-output-names = "clk-32k-out";
434
435		regulators {
436			/* vdd_soc: 0.805-0.900V (typ=0.8V) */
437			BUCK1 {
438				regulator-name = "buck1";
439				regulator-min-microvolt = <700000>;
440				regulator-max-microvolt = <1300000>;
441				regulator-boot-on;
442				regulator-always-on;
443				regulator-ramp-delay = <1250>;
444			};
445
446			/* vdd_arm: 0.805-1.0V (typ=0.9V) */
447			buck2: BUCK2 {
448				regulator-name = "buck2";
449				regulator-min-microvolt = <700000>;
450				regulator-max-microvolt = <1300000>;
451				regulator-boot-on;
452				regulator-always-on;
453				regulator-ramp-delay = <1250>;
454				rohm,dvs-run-voltage = <1000000>;
455				rohm,dvs-idle-voltage = <900000>;
456			};
457
458			/* vdd_0p9: 0.805-1.0V (typ=0.9V) */
459			BUCK3 {
460				regulator-name = "buck3";
461				regulator-min-microvolt = <700000>;
462				regulator-max-microvolt = <1350000>;
463				regulator-boot-on;
464				regulator-always-on;
465			};
466
467			/* vdd_3p3 */
468			BUCK4 {
469				regulator-name = "buck4";
470				regulator-min-microvolt = <3000000>;
471				regulator-max-microvolt = <3300000>;
472				regulator-boot-on;
473				regulator-always-on;
474			};
475
476			/* vdd_1p8 */
477			BUCK5 {
478				regulator-name = "buck5";
479				regulator-min-microvolt = <1605000>;
480				regulator-max-microvolt = <1995000>;
481				regulator-boot-on;
482				regulator-always-on;
483			};
484
485			/* vdd_dram */
486			BUCK6 {
487				regulator-name = "buck6";
488				regulator-min-microvolt = <800000>;
489				regulator-max-microvolt = <1400000>;
490				regulator-boot-on;
491				regulator-always-on;
492			};
493
494			/* nvcc_snvs_1p8 */
495			LDO1 {
496				regulator-name = "ldo1";
497				regulator-min-microvolt = <1600000>;
498				regulator-max-microvolt = <1900000>;
499				regulator-boot-on;
500				regulator-always-on;
501			};
502
503			/* vdd_snvs_0p8 */
504			LDO2 {
505				regulator-name = "ldo2";
506				regulator-min-microvolt = <800000>;
507				regulator-max-microvolt = <900000>;
508				regulator-boot-on;
509				regulator-always-on;
510			};
511
512			/* vdda_1p8 */
513			LDO3 {
514				regulator-name = "ldo3";
515				regulator-min-microvolt = <1800000>;
516				regulator-max-microvolt = <3300000>;
517				regulator-boot-on;
518				regulator-always-on;
519			};
520
521			LDO4 {
522				regulator-name = "ldo4";
523				regulator-min-microvolt = <900000>;
524				regulator-max-microvolt = <1800000>;
525				regulator-boot-on;
526				regulator-always-on;
527			};
528
529			LDO6 {
530				regulator-name = "ldo6";
531				regulator-min-microvolt = <900000>;
532				regulator-max-microvolt = <1800000>;
533				regulator-boot-on;
534				regulator-always-on;
535			};
536		};
537	};
538
539	eeprom@50 {
540		compatible = "atmel,24c02";
541		reg = <0x50>;
542		pagesize = <16>;
543	};
544
545	eeprom@51 {
546		compatible = "atmel,24c02";
547		reg = <0x51>;
548		pagesize = <16>;
549	};
550
551	eeprom@52 {
552		compatible = "atmel,24c02";
553		reg = <0x52>;
554		pagesize = <16>;
555	};
556
557	eeprom@53 {
558		compatible = "atmel,24c02";
559		reg = <0x53>;
560		pagesize = <16>;
561	};
562
563	rtc@68 {
564		compatible = "dallas,ds1672";
565		reg = <0x68>;
566	};
567};
568
569&i2c2 {
570	clock-frequency = <400000>;
571	pinctrl-names = "default", "gpio";
572	pinctrl-0 = <&pinctrl_i2c2>;
573	pinctrl-1 = <&pinctrl_i2c2_gpio>;
574	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
575	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
576	status = "okay";
577
578	accelerometer@19 {
579		compatible = "st,lis2de12";
580		pinctrl-names = "default";
581		pinctrl-0 = <&pinctrl_accel>;
582		reg = <0x19>;
583		st,drdy-int-pin = <1>;
584		interrupt-parent = <&gpio1>;
585		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
586		interrupt-names = "INT1";
587	};
588};
589
590/* off-board header */
591&i2c3 {
592	clock-frequency = <400000>;
593	pinctrl-names = "default", "gpio";
594	pinctrl-0 = <&pinctrl_i2c3>;
595	pinctrl-1 = <&pinctrl_i2c3_gpio>;
596	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
597	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
598	status = "okay";
599};
600
601/* off-board header */
602&i2c4 {
603	clock-frequency = <400000>;
604	pinctrl-names = "default", "gpio";
605	pinctrl-0 = <&pinctrl_i2c4>;
606	pinctrl-1 = <&pinctrl_i2c4_gpio>;
607	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
608	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
609	status = "okay";
610};
611
612&pgc_gpumix {
613	status = "disabled";
614};
615
616/* off-board header */
617&sai3 {
618	pinctrl-names = "default";
619	pinctrl-0 = <&pinctrl_sai3>;
620	assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
621	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
622	assigned-clock-rates = <24576000>;
623	status = "okay";
624};
625
626/* RS232/RS485/RS422 selectable */
627&uart1 {
628	pinctrl-names = "default";
629	pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
630	status = "okay";
631};
632
633/* RS232 console */
634&uart2 {
635	pinctrl-names = "default";
636	pinctrl-0 = <&pinctrl_uart2>;
637	status = "okay";
638};
639
640/* bluetooth HCI */
641&uart3 {
642	pinctrl-names = "default";
643	pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
644	rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
645	cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
646	status = "okay";
647
648	bluetooth {
649		compatible = "brcm,bcm4330-bt";
650		shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
651	};
652};
653
654/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
655&uart4 {
656	pinctrl-names = "default";
657	pinctrl-0 = <&pinctrl_uart4>;
658	status = "okay";
659};
660
661&usbotg1 {
662	dr_mode = "host";
663	vbus-supply = <&reg_usb1_vbus>;
664	disable-over-current;
665	status = "okay";
666};
667
668/* SDIO WiFi */
669&usdhc2 {
670	pinctrl-names = "default", "state_100mhz", "state_200mhz";
671	pinctrl-0 = <&pinctrl_usdhc2>;
672	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
673	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
674	bus-width = <4>;
675	non-removable;
676	vmmc-supply = <&reg_wifi>;
677	#address-cells = <1>;
678	#size-cells = <0>;
679	status = "okay";
680
681	wifi@0 {
682		compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac";
683		reg = <0>;
684	};
685};
686
687/* eMMC */
688&usdhc3 {
689	pinctrl-names = "default", "state_100mhz", "state_200mhz";
690	pinctrl-0 = <&pinctrl_usdhc3>;
691	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
692	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
693	bus-width = <8>;
694	non-removable;
695	status = "okay";
696};
697
698&wdog1 {
699	pinctrl-names = "default";
700	pinctrl-0 = <&pinctrl_wdog>;
701	fsl,ext-reset-output;
702	status = "okay";
703};
704
705&iomuxc {
706	pinctrl-names = "default";
707	pinctrl-0 = <&pinctrl_hog>;
708
709	pinctrl_hog: hoggrp {
710		fsl,pins = <
711			MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1	0x40000159 /* M2_GDIS# */
712			MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x40000041 /* M2_PWR_EN */
713			MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x40000041 /* M2_RESET */
714			MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7	0x40000119 /* M2_OFF# */
715			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x40000159 /* M2_WDIS# */
716			MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x40000041 /* APP GPIO1 */
717			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x40000041 /* VDD_4P0_EN */
718			MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27	0x40000041 /* APP GPIO2 */
719			MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8	0x40000041 /* UART2_EN# */
720			MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x40000041 /* MIPI_GPIO1 */
721			MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x40000041 /* MIPI_GPIO2 */
722			MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4		0x40000041 /* MIPI_GPIO3/PWM2 */
723			MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* MIPI_GPIO4/PWM3 */
724		>;
725	};
726
727	pinctrl_accel: accelgrp {
728		fsl,pins = <
729			MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x159
730		>;
731	};
732
733	pinctrl_fec1: fec1grp {
734		fsl,pins = <
735			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC			0x3
736			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
737			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
738			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
739			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
740			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
741			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
742			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
743			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
744			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
745			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
746			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
747			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
748			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
749			MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19 /* RST# */
750			MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19 /* IRQ# */
751		>;
752	};
753
754	pinctrl_gsc: gscgrp {
755		fsl,pins = <
756			MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6	0x40
757		>;
758	};
759
760	pinctrl_i2c1: i2c1grp {
761		fsl,pins = <
762			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
763			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
764		>;
765	};
766
767	pinctrl_i2c1_gpio: i2c1gpiogrp {
768		fsl,pins = <
769			MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3
770			MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3
771		>;
772	};
773
774	pinctrl_i2c2: i2c2grp {
775		fsl,pins = <
776			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
777			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
778		>;
779	};
780
781	pinctrl_i2c2_gpio: i2c2gpiogrp {
782		fsl,pins = <
783			MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3
784			MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3
785		>;
786	};
787
788	pinctrl_i2c3: i2c3grp {
789		fsl,pins = <
790			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
791			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
792		>;
793	};
794
795	pinctrl_i2c3_gpio: i2c3gpiogrp {
796		fsl,pins = <
797			MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18	0x400001c3
798			MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19	0x400001c3
799		>;
800	};
801
802	pinctrl_i2c4: i2c4grp {
803		fsl,pins = <
804			MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
805			MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
806		>;
807	};
808
809	pinctrl_i2c4_gpio: i2c4gpiogrp {
810		fsl,pins = <
811			MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20	0x400001c3
812			MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21	0x400001c3
813		>;
814	};
815
816	pinctrl_gpio_leds: gpioledgrp {
817		fsl,pins = <
818			MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21	0x19
819			MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23	0x19
820			MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22	0x19
821			MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20	0x19
822			MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x19
823		>;
824	};
825
826	pinctrl_pmic: pmicgrp {
827		fsl,pins = <
828			MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8	0x41
829		>;
830	};
831
832	pinctrl_pps: ppsgrp {
833		fsl,pins = <
834			MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24	0x141 /* PPS */
835		>;
836	};
837
838	pinctrl_reg_wl: regwlgrp {
839		fsl,pins = <
840			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41 /* WLAN_WLON */
841		>;
842	};
843
844	pinctrl_reg_usb1: regusb1grp {
845		fsl,pins = <
846			MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7	0x41
847		>;
848	};
849
850	pinctrl_sai3: sai3grp {
851		fsl,pins = <
852			MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK	0xd6
853			MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
854			MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK	0xd6
855			MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0	0xd6
856			MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC	0xd6
857		>;
858	};
859
860	pinctrl_spi1: spi1grp {
861		fsl,pins = <
862			MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x82
863			MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x82
864			MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x82
865			MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x40
866			MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3	0x140 /* CAN_IRQ# */
867		>;
868	};
869
870	pinctrl_spi2: spi2grp {
871		fsl,pins = <
872			MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x82
873			MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x82
874			MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x82
875			MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x40 /* SS0 */
876		>;
877	};
878
879	pinctrl_uart1: uart1grp {
880		fsl,pins = <
881			MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
882			MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
883		>;
884	};
885
886	pinctrl_uart1_gpio: uart1gpiogrp {
887		fsl,pins = <
888			MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26	0x40000110 /* HALF */
889			MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25	0x40000110 /* TERM */
890			MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23	0x40000110 /* RS485 */
891		>;
892	};
893
894	pinctrl_uart2: uart2grp {
895		fsl,pins = <
896			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
897			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
898		>;
899	};
900
901	pinctrl_uart3_gpio: uart3_gpiogrp {
902		fsl,pins = <
903			MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41 /* BT_EN# */
904		>;
905	};
906
907	pinctrl_uart3: uart3grp {
908		fsl,pins = <
909			MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
910			MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
911			MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0		0x140 /* CTS */
912			MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1		0x140 /* RTS */
913		>;
914	};
915
916	pinctrl_uart4: uart4grp {
917		fsl,pins = <
918			MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
919			MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
920			MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x141 /* GNSS_GASP */
921		>;
922	};
923
924	pinctrl_usdhc2: usdhc2grp {
925		fsl,pins = <
926			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
927			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
928			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
929			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
930			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
931			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
932		>;
933	};
934
935	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
936		fsl,pins = <
937			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
938			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
939			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
940			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
941			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
942			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
943		>;
944	};
945
946	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
947		fsl,pins = <
948			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
949			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
950			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
951			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
952			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
953			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
954		>;
955	};
956
957	pinctrl_usdhc3: usdhc3grp {
958		fsl,pins = <
959			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
960			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
961			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
962			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
963			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
964			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
965			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
966			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
967			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
968			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
969			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
970		>;
971	};
972
973	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
974		fsl,pins = <
975			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
976			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
977			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
978			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
979			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
980			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
981			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
982			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
983			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
984			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
985			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
986		>;
987	};
988
989	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
990		fsl,pins = <
991			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
992			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
993			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
994			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
995			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
996			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
997			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
998			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
999			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
1000			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
1001			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
1002		>;
1003	};
1004
1005	pinctrl_wdog: wdoggrp {
1006		fsl,pins = <
1007			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
1008		>;
1009	};
1010};
1011