| /openbmc/qemu/hw/net/ |
| H A D | npcm_gmac.c | 2 * Nuvoton NPCM7xx/8xx GMAC Module
136 static void npcm_gmac_soft_reset(NPCMGMACState *gmac) in npcm_gmac_soft_reset() argument
138 memcpy(gmac->regs, npcm_gmac_cold_reset_values, in npcm_gmac_soft_reset()
141 gmac->regs[R_NPCM_DMA_BUS_MODE] &= ~NPCM_DMA_BUS_MODE_SWR; in npcm_gmac_soft_reset()
144 static void gmac_phy_set_link(NPCMGMACState *gmac, bool active) in gmac_phy_set_link() argument
148 gmac->phy_regs[0][MII_BMSR] |= (MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); in gmac_phy_set_link()
150 gmac->phy_regs[0][MII_BMSR] &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); in gmac_phy_set_link()
156 NPCMGMACState *gmac = NPCM_GMAC(qemu_get_nic_opaque(nc)); in gmac_can_receive() local
158 /* If GMAC receive is disabled. */ in gmac_can_receive()
159 if (!(gmac->regs[R_NPCM_GMAC_MAC_CONFIG] & NPCM_GMAC_MAC_CONFIG_RX_EN)) { in gmac_can_receive()
[all …]
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| /openbmc/linux/drivers/net/ethernet/stmicro/stmmac/ |
| H A D | dwmac-ipq806x.c | 2 * Qualcomm Atheros IPQ806x GMAC glue layer
115 static int get_clk_div_sgmii(struct ipq806x_gmac *gmac, unsigned int speed) in get_clk_div_sgmii() argument
117 struct device *dev = &gmac->pdev->dev; in get_clk_div_sgmii()
141 static int get_clk_div_rgmii(struct ipq806x_gmac *gmac, unsigned int speed) in get_clk_div_rgmii() argument
143 struct device *dev = &gmac->pdev->dev; in get_clk_div_rgmii()
167 static int ipq806x_gmac_set_speed(struct ipq806x_gmac *gmac, unsigned int speed) in ipq806x_gmac_set_speed() argument
172 switch (gmac->phy_mode) { in ipq806x_gmac_set_speed()
174 div = get_clk_div_rgmii(gmac, speed); in ipq806x_gmac_set_speed()
175 clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) | in ipq806x_gmac_set_speed()
176 NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id); in ipq806x_gmac_set_speed()
[all …]
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| H A D | dwmac-sunxi.c | 32 struct sunxi_priv_data *gmac = priv; in sun7i_gmac_init() local
35 if (gmac->regulator) { in sun7i_gmac_init()
36 ret = regulator_enable(gmac->regulator); in sun7i_gmac_init()
41 /* Set GMAC interface port mode in sun7i_gmac_init()
43 * The GMAC TX clock lines are configured by setting the clock in sun7i_gmac_init()
47 if (phy_interface_mode_is_rgmii(gmac->interface)) { in sun7i_gmac_init()
48 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE); in sun7i_gmac_init()
49 clk_prepare_enable(gmac->tx_clk); in sun7i_gmac_init()
50 gmac->clk_enabled = 1; in sun7i_gmac_init()
52 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE); in sun7i_gmac_init()
[all …]
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| H A D | dwmac-anarion.c | 27 static uint32_t gmac_read_reg(struct anarion_gmac *gmac, uint8_t reg) in gmac_read_reg() argument
29 return readl(gmac->ctl_block + reg); in gmac_read_reg()
32 static void gmac_write_reg(struct anarion_gmac *gmac, uint8_t reg, uint32_t val) in gmac_write_reg() argument
34 writel(val, gmac->ctl_block + reg); in gmac_write_reg()
40 struct anarion_gmac *gmac = priv; in anarion_gmac_init() local
43 gmac_write_reg(gmac, GMAC_RESET_CONTROL_REG, 1); in anarion_gmac_init()
45 sw_config = gmac_read_reg(gmac, GMAC_SW_CONFIG_REG); in anarion_gmac_init()
47 sw_config |= (gmac->phy_intf_sel & GMAC_CONFIG_INTF_SEL_MASK); in anarion_gmac_init()
48 gmac_write_reg(gmac, GMAC_SW_CONFIG_REG, sw_config); in anarion_gmac_init()
50 gmac_write_reg(gmac, GMAC_RESET_CONTROL_REG, 0); in anarion_gmac_init()
[all …]
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| H A D | dwmac-sun8i.c | 38 * @syscon_field reg_field for the syscon's gmac register
588 struct sunxi_priv_data *gmac = priv; in sun8i_dwmac_init() local
591 if (gmac->regulator) { in sun8i_dwmac_init()
592 ret = regulator_enable(gmac->regulator); in sun8i_dwmac_init()
599 if (gmac->use_internal_phy) { in sun8i_dwmac_init()
608 if (gmac->regulator) in sun8i_dwmac_init()
609 regulator_disable(gmac->regulator); in sun8i_dwmac_init()
776 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; in get_ephy_nodes() local
797 gmac->ephy_clk = of_clk_get(iphynode, 0); in get_ephy_nodes()
798 if (IS_ERR(gmac->ephy_clk)) in get_ephy_nodes()
[all …]
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| H A D | Kconfig | 61 tristate "Adaptrum Anarion GMAC support"
65 Support for Adaptrum Anarion GMAC Ethernet controller.
106 tristate "MediaTek MT27xx GMAC support"
109 Support for MediaTek GMAC Ethernet controller.
173 tristate "STi GMAC support"
182 SOCs GMAC ethernet controller.
194 SOCs GMAC ethernet controller.
197 tristate "Allwinner GMAC support"
201 Support for Allwinner A20/A31 GMAC ethernet controllers.
205 GMAC ethernet controller.
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| H A D | hwif.c | 60 /* GMAC older than 3.50 has no extended descriptors */ in stmmac_dwmac1_quirks()
104 bool gmac; member
122 .gmac = false,
140 .gmac = true,
158 .gmac = false,
176 .gmac = false,
194 .gmac = false,
212 .gmac = false,
230 .gmac = false,
249 .gmac = false,
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | rockchip-dwmac.yaml | 7 title: Rockchip 10/100/1000 Ethernet driver(GMAC)
18 - rockchip,px30-gmac
19 - rockchip,rk3128-gmac
20 - rockchip,rk3228-gmac
21 - rockchip,rk3288-gmac
22 - rockchip,rk3308-gmac
23 - rockchip,rk3328-gmac
24 - rockchip,rk3366-gmac
25 - rockchip,rk3368-gmac
26 - rockchip,rk3399-gmac
[all …]
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| H A D | hisilicon-hix5hd2-gmac.txt | 1 Hisilicon hix5hd2 gmac controller
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
43 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
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| H A D | allwinner,sun7i-a20-gmac.yaml | 4 $id: http://devicetree.org/schemas/net/allwinner,sun7i-a20-gmac.yaml#
7 title: Allwinner A20 GMAC
18 const: allwinner,sun7i-a20-gmac
31 - description: GMAC main clock
56 gmac: ethernet@1c50000 {
57 compatible = "allwinner,sun7i-a20-gmac";
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| H A D | snps,dwmac.yaml | 38 - st,spear600-gmac
51 - allwinner,sun7i-a20-gmac
54 - allwinner,sun8i-r40-gmac
73 - renesas,r9a06g032-gmac
74 - renesas,rzn1-gmac
75 - rockchip,px30-gmac
76 - rockchip,rk3128-gmac
77 - rockchip,rk3228-gmac
78 - rockchip,rk3288-gmac
79 - rockchip,rk3328-gmac
[all …]
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| H A D | mediatek-dwmac.yaml | 21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
35 - mediatek,mt2712-gmac
39 - mediatek,mt8195-gmac
43 - mediatek,mt8188-gmac
44 - const: mediatek,mt8195-gmac
155 compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
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| H A D | ipq806x-dwmac.txt | 8 - compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac"
20 gmac: ethernet@37000000 {
22 compatible = "qcom,ipq806x-gmac";
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| /openbmc/linux/drivers/clk/sunxi/ |
| H A D | clk-a20-gmac.c | 19 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
23 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
24 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
28 * The external 125 MHz reference is optional, i.e. GMAC can use its
29 * internal TX clock just fine. The A31 GMAC clock module does not have
32 * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
33 * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
36 * Only the GMAC should use this clock. Altering the clock so that it doesn't
37 * match the GMAC's operation parameters will result in the GMAC not being
38 * able to send traffic out. The GMAC driver should set the clock rate and
[all …]
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| /openbmc/u-boot/doc/device-tree-bindings/net/ |
| H A D | allwinner,sun7i-a20-gmac.txt | 1 * Allwinner GMAC ethernet controller
7 - compatible: Should be "allwinner,sun7i-a20-gmac"
8 - clocks: Should contain the GMAC main clock, and tx clock
9 The tx clock type should be "allwinner,sun7i-a20-gmac-clk"
18 gmac: ethernet@01c50000 {
19 compatible = "allwinner,sun7i-a20-gmac";
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| H A D | stmmac.txt | 1 * STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
5 For backwards compatibility: "st,spear600-gmac" is also supported.
38 - clocks: If present, the first clock should be the GMAC main clock,
51 compatible = "st,spear600-gmac";
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| /openbmc/linux/drivers/net/ethernet/cortina/ |
| H A D | gemini.h | 2 /* Register definitions for Gemini GMAC Ethernet device driver
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
91 /* GMAC 0/1 DMA/TOE register */
145 /* GMAC Hash/Rx/Tx AHB Weighting register */
148 /* TOE GMAC 0/1 register */
332 /* GMAC DMA Control Register
366 /* GMAC Tx Weighting Control Register 0
386 /* GMAC Tx Weighting Control Register 1
410 /* GMAC DMA Tx Description Word 0 Register
434 /* GMAC DMA Tx Description Word 1 Register
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | allwinner,sun7i-a20-gmac-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-gmac-clk.yaml#
7 title: Allwinner A20 GMAC TX Clock
18 const: allwinner,sun7i-a20-gmac-clk
45 compatible = "allwinner,sun7i-a20-gmac-clk";
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| /openbmc/linux/drivers/net/ethernet/hisilicon/hns/ |
| H A D | hns_dsaf_mac.h | 221 u64 rx_bad_bytes; /* only for gmac */
228 u64 rx_minto64; /* only for gmac */
240 u64 rx_vlan_pkts; /* only for gmac */
241 u64 rx_data_err; /* only for gmac */
242 u64 rx_align_err; /* only for gmac */
243 u64 rx_long_err; /* only for gmac */
253 u64 rx_filter_pkts; /* only for gmac */
254 u64 rx_filter_bytes; /* only for gmac */
255 u64 rx_fifo_overrun_err;/* only for gmac */
256 u64 rx_len_err; /* only for gmac */
[all …]
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| /openbmc/u-boot/drivers/net/ |
| H A D | Kconfig | 67 bool "Broadcom SF2 (Starfighter2) GMAC Ethernet support"
71 GMAC such as Cygnus. This driver is based on the framework provided
278 bool "Intel Platform Controller Hub EG20T GMAC driver"
337 bool "Enable Allwinner GMAC Ethernet support"
339 Enable the support for Sun7i GMAC Ethernet controller
342 bool "Force PA17 as gmac function"
345 Some ethernet phys needs TXERR control. Since the GMAC
346 doesn't have such signal, setting PA17 as GMAC function
522 bool "MediaTek Ethernet GMAC Driver"
528 This Driver support MediaTek Ethernet GMAC
[all …]
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| H A D | gmac_rockchip.c | 5 * Rockchip GMAC ethernet IP driver for U-Boot
33 * Platform data for the gmac
461 * If the gmac clock is from internal pll, need to set and in gmac_rockchip_probe()
462 * check the return value for gmac clock at RGMII mode. If in gmac_rockchip_probe()
463 * the gmac clock is from external source, the clock rate in gmac_rockchip_probe()
603 { .compatible = "rockchip,rk3228-gmac",
605 { .compatible = "rockchip,rk3288-gmac",
607 { .compatible = "rockchip,rk3328-gmac",
609 { .compatible = "rockchip,rk3368-gmac",
611 { .compatible = "rockchip,rk3399-gmac",
[all …]
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| /openbmc/qemu/tests/qtest/ |
| H A D | npcm_gmac-test.c | 2 * QTests for Nuvoton NPCM7xx/8xx GMAC Modules.
23 /* Name of the GMAC Device */
24 #define TYPE_NPCM_GMAC "npcm-gmac"
51 /* Returns the index of the GMAC module. */
79 /* GMAC Registers */
177 /* Check that GMAC registers are reset to default value */
245 "npcm7xx_gmac/gmac[%d]/%s", gmac_module_index(td->module), name); in gmac_add_test()
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| /openbmc/linux/drivers/pinctrl/sunxi/ |
| H A D | pinctrl-sun6i-a31.c | 24 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
32 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
40 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
48 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
56 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
64 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
72 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
80 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
88 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
95 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
[all …]
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| H A D | pinctrl-sun8i-a83t.c | 185 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD3 */
190 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD2 */
195 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD1 */
200 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD0 */
205 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXCK */
210 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXDV */
215 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXERR */
220 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD3 */
225 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD2 */
230 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD1 */
[all …]
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | rk3399-ficus.dts | 21 clkin_gmac: external-gmac-clock {
29 &gmac {
50 gmac {
|