Lines Matching full:gmac
2 * Nuvoton NPCM7xx/8xx GMAC Module
136 static void npcm_gmac_soft_reset(NPCMGMACState *gmac) in npcm_gmac_soft_reset() argument
138 memcpy(gmac->regs, npcm_gmac_cold_reset_values, in npcm_gmac_soft_reset()
141 gmac->regs[R_NPCM_DMA_BUS_MODE] &= ~NPCM_DMA_BUS_MODE_SWR; in npcm_gmac_soft_reset()
144 static void gmac_phy_set_link(NPCMGMACState *gmac, bool active) in gmac_phy_set_link() argument
148 gmac->phy_regs[0][MII_BMSR] |= (MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); in gmac_phy_set_link()
150 gmac->phy_regs[0][MII_BMSR] &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); in gmac_phy_set_link()
156 NPCMGMACState *gmac = NPCM_GMAC(qemu_get_nic_opaque(nc)); in gmac_can_receive() local
158 /* If GMAC receive is disabled. */ in gmac_can_receive()
159 if (!(gmac->regs[R_NPCM_GMAC_MAC_CONFIG] & NPCM_GMAC_MAC_CONFIG_RX_EN)) { in gmac_can_receive()
163 /* If GMAC DMA RX is stopped. */ in gmac_can_receive()
164 if (!(gmac->regs[R_NPCM_DMA_CONTROL] & NPCM_DMA_CONTROL_START_STOP_RX)) { in gmac_can_receive()
171 * Function that updates the GMAC IRQ
175 static void gmac_update_irq(NPCMGMACState *gmac) in gmac_update_irq() argument
181 if (gmac->regs[R_NPCM_DMA_INTR_ENA] & gmac->regs[R_NPCM_DMA_STATUS] & in gmac_update_irq()
183 gmac->regs[R_NPCM_DMA_STATUS] |= NPCM_DMA_STATUS_NIS; in gmac_update_irq()
189 if (gmac->regs[R_NPCM_DMA_INTR_ENA] & gmac->regs[R_NPCM_DMA_STATUS] & in gmac_update_irq()
191 gmac->regs[R_NPCM_DMA_STATUS] |= NPCM_DMA_STATUS_AIS; in gmac_update_irq()
195 int level = !!((gmac->regs[R_NPCM_DMA_STATUS] & in gmac_update_irq()
196 gmac->regs[R_NPCM_DMA_INTR_ENA] & in gmac_update_irq()
198 (gmac->regs[R_NPCM_DMA_STATUS] & in gmac_update_irq()
199 gmac->regs[R_NPCM_DMA_INTR_ENA] & in gmac_update_irq()
203 trace_npcm_gmac_update_irq(DEVICE(gmac)->canonical_path, in gmac_update_irq()
204 gmac->regs[R_NPCM_DMA_STATUS], in gmac_update_irq()
205 gmac->regs[R_NPCM_DMA_INTR_ENA], in gmac_update_irq()
207 qemu_set_irq(gmac->irq, level); in gmac_update_irq()
306 static void gmac_dma_set_state(NPCMGMACState *gmac, int shift, uint32_t state) in gmac_dma_set_state() argument
308 gmac->regs[R_NPCM_DMA_STATUS] = deposit32(gmac->regs[R_NPCM_DMA_STATUS], in gmac_dma_set_state()
318 NPCMGMACState *gmac = NPCM_GMAC(qemu_get_nic_opaque(nc)); in gmac_receive() local
327 trace_npcm_gmac_packet_receive(DEVICE(gmac)->canonical_path, len); in gmac_receive()
329 qemu_log_mask(LOG_GUEST_ERROR, "GMAC Currently is not able for Rx"); in gmac_receive()
332 if (!gmac->regs[R_NPCM_DMA_HOST_RX_DESC]) { in gmac_receive()
333 gmac->regs[R_NPCM_DMA_HOST_RX_DESC] = in gmac_receive()
334 NPCM_DMA_HOST_RX_DESC_MASK(gmac->regs[R_NPCM_DMA_RX_BASE_ADDR]); in gmac_receive()
336 desc_addr = NPCM_DMA_HOST_RX_DESC_MASK(gmac->regs[R_NPCM_DMA_HOST_RX_DESC]); in gmac_receive()
339 gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT, in gmac_receive()
341 trace_npcm_gmac_packet_desc_read(DEVICE(gmac)->canonical_path, desc_addr); in gmac_receive()
345 gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT, in gmac_receive()
355 gmac->regs[R_NPCM_DMA_STATUS] |= NPCM_DMA_STATUS_RU; in gmac_receive()
356 gmac->regs[R_NPCM_DMA_STATUS] |= NPCM_DMA_STATUS_RI; in gmac_receive()
357 gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT, in gmac_receive()
359 gmac_update_irq(gmac); in gmac_receive()
367 trace_npcm_gmac_debug_desc_data(DEVICE(gmac)->canonical_path, &rx_desc, in gmac_receive()
373 gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT, in gmac_receive()
389 gmac->regs[R_NPCM_DMA_CUR_RX_BUF_ADDR] = rx_buf_addr; in gmac_receive()
394 trace_npcm_gmac_packet_receiving_buffer(DEVICE(gmac)->canonical_path, in gmac_receive()
402 gmac->regs[R_NPCM_DMA_CUR_RX_BUF_ADDR] = rx_buf_addr; in gmac_receive()
407 DEVICE(gmac)->canonical_path, in gmac_receive()
411 gmac->regs[R_NPCM_DMA_HOST_RX_DESC] = rx_buf_addr; in gmac_receive()
417 trace_npcm_gmac_debug_desc_data(DEVICE(gmac)->canonical_path, &rx_desc, in gmac_receive()
423 trace_npcm_gmac_debug_desc_data(DEVICE(gmac)->canonical_path, in gmac_receive()
431 desc_addr = gmac->regs[R_NPCM_DMA_RX_BASE_ADDR]; in gmac_receive()
437 trace_npcm_gmac_packet_desc_read(DEVICE(gmac)->canonical_path, in gmac_receive()
443 gmac->regs[R_NPCM_DMA_STATUS] |= NPCM_DMA_STATUS_RU; in gmac_receive()
444 gmac_update_irq(gmac); in gmac_receive()
450 if (!(gmac->regs[R_NPCM_DMA_CONTROL] & \ in gmac_receive()
460 gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT, in gmac_receive()
465 gmac->regs[R_NPCM_DMA_STATUS] |= NPCM_DMA_STATUS_RI; in gmac_receive()
466 gmac_update_irq(gmac); in gmac_receive()
468 trace_npcm_gmac_debug_desc_data(DEVICE(gmac)->canonical_path, &rx_desc, in gmac_receive()
473 gmac->regs[R_NPCM_DMA_CONTROL] |= NPCM_DMA_CONTROL_FLUSH_MASK; in gmac_receive()
476 trace_npcm_gmac_packet_received(DEVICE(gmac)->canonical_path, left_frame); in gmac_receive()
477 gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT, in gmac_receive()
483 desc_addr = gmac->regs[R_NPCM_DMA_RX_BASE_ADDR]; in gmac_receive()
489 gmac->regs[R_NPCM_DMA_HOST_RX_DESC] = desc_addr; in gmac_receive()
508 static void gmac_try_send_next_packet(NPCMGMACState *gmac) in gmac_try_send_next_packet() argument
525 if (!gmac->regs[R_NPCM_DMA_HOST_TX_DESC]) { in gmac_try_send_next_packet()
526 gmac->regs[R_NPCM_DMA_HOST_TX_DESC] = in gmac_try_send_next_packet()
527 NPCM_DMA_HOST_TX_DESC_MASK(gmac->regs[R_NPCM_DMA_TX_BASE_ADDR]); in gmac_try_send_next_packet()
529 desc_addr = gmac->regs[R_NPCM_DMA_HOST_TX_DESC]; in gmac_try_send_next_packet()
532 gmac_dma_set_state(gmac, NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT, in gmac_try_send_next_packet()
542 trace_npcm_gmac_packet_desc_read(DEVICE(gmac)->canonical_path, in gmac_try_send_next_packet()
544 trace_npcm_gmac_debug_desc_data(DEVICE(gmac)->canonical_path, &tx_desc, in gmac_try_send_next_packet()
549 trace_npcm_gmac_tx_desc_owner(DEVICE(gmac)->canonical_path, in gmac_try_send_next_packet()
551 gmac->regs[R_NPCM_DMA_STATUS] |= NPCM_DMA_STATUS_TU; in gmac_try_send_next_packet()
552 gmac_dma_set_state(gmac, NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT, in gmac_try_send_next_packet()
554 gmac_update_irq(gmac); in gmac_try_send_next_packet()
558 gmac_dma_set_state(gmac, NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT, in gmac_try_send_next_packet()
569 gmac->regs[R_NPCM_DMA_CUR_TX_BUF_ADDR] = tx_buf_addr; in gmac_try_send_next_packet()
592 gmac->regs[R_NPCM_DMA_CUR_TX_BUF_ADDR] = tx_buf_addr; in gmac_try_send_next_packet()
614 qemu_send_packet(qemu_get_queue(gmac->nic), tx_send_buffer, length); in gmac_try_send_next_packet()
615 trace_npcm_gmac_packet_sent(DEVICE(gmac)->canonical_path, length); in gmac_try_send_next_packet()
621 gmac_dma_set_state(gmac, NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT, in gmac_try_send_next_packet()
625 desc_addr = gmac->regs[R_NPCM_DMA_TX_BASE_ADDR]; in gmac_try_send_next_packet()
631 gmac->regs[R_NPCM_DMA_HOST_TX_DESC] = desc_addr; in gmac_try_send_next_packet()
635 gmac->regs[R_NPCM_DMA_STATUS] |= NPCM_DMA_STATUS_TI; in gmac_try_send_next_packet()
636 gmac_update_irq(gmac); in gmac_try_send_next_packet()
648 NPCMGMACState *gmac = qemu_get_nic_opaque(nc); in gmac_set_link() local
651 gmac_phy_set_link(gmac, !nc->link_down); in gmac_set_link()
654 static void npcm_gmac_mdio_access(NPCMGMACState *gmac, uint16_t v) in npcm_gmac_mdio_access() argument
671 data = gmac->regs[R_NPCM_GMAC_MII_DATA]; in npcm_gmac_mdio_access()
682 !(gmac->phy_regs[pa][MII_BMSR] & MII_BMSR_AN_COMP)) { in npcm_gmac_mdio_access()
684 gmac->phy_regs[pa][MII_BMSR] |= MII_BMSR_AN_COMP; in npcm_gmac_mdio_access()
686 gmac->phy_regs[0][MII_ANLPAR] = 0x0000; in npcm_gmac_mdio_access()
689 gmac->phy_regs[pa][gr] = data; in npcm_gmac_mdio_access()
691 data = gmac->phy_regs[pa][gr]; in npcm_gmac_mdio_access()
692 gmac->regs[R_NPCM_GMAC_MII_DATA] = data; in npcm_gmac_mdio_access()
694 trace_npcm_gmac_mdio_access(DEVICE(gmac)->canonical_path, is_write, pa, in npcm_gmac_mdio_access()
697 gmac->regs[R_NPCM_GMAC_MII_ADDR] = v & ~NPCM_GMAC_MII_ADDR_BUSY; in npcm_gmac_mdio_access()
702 NPCMGMACState *gmac = opaque; in npcm_gmac_read() local
711 "\n", DEVICE(gmac)->canonical_path, offset); in npcm_gmac_read()
715 v = gmac->regs[offset / sizeof(uint32_t)]; in npcm_gmac_read()
718 trace_npcm_gmac_reg_read(DEVICE(gmac)->canonical_path, offset, v); in npcm_gmac_read()
725 NPCMGMACState *gmac = opaque; in npcm_gmac_write() local
727 trace_npcm_gmac_reg_write(DEVICE(gmac)->canonical_path, offset, v); in npcm_gmac_write()
745 DEVICE(gmac)->canonical_path, offset, v); in npcm_gmac_write()
749 gmac->regs[offset / sizeof(uint32_t)] = v; in npcm_gmac_write()
753 npcm_gmac_mdio_access(gmac, v); in npcm_gmac_write()
757 gmac->regs[offset / sizeof(uint32_t)] = v; in npcm_gmac_write()
758 gmac->conf.macaddr.a[0] = v >> 8; in npcm_gmac_write()
759 gmac->conf.macaddr.a[1] = v >> 0; in npcm_gmac_write()
763 gmac->regs[offset / sizeof(uint32_t)] = v; in npcm_gmac_write()
764 gmac->conf.macaddr.a[2] = v >> 24; in npcm_gmac_write()
765 gmac->conf.macaddr.a[3] = v >> 16; in npcm_gmac_write()
766 gmac->conf.macaddr.a[4] = v >> 8; in npcm_gmac_write()
767 gmac->conf.macaddr.a[5] = v >> 0; in npcm_gmac_write()
776 gmac->regs[offset / sizeof(uint32_t)] = v; in npcm_gmac_write()
779 "is ignored.\n", DEVICE(gmac)->canonical_path); in npcm_gmac_write()
783 gmac->regs[offset / sizeof(uint32_t)] = v; in npcm_gmac_write()
785 npcm_gmac_soft_reset(gmac); in npcm_gmac_write()
791 gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT, in npcm_gmac_write()
797 gmac_try_send_next_packet(gmac); in npcm_gmac_write()
801 gmac->regs[offset / sizeof(uint32_t)] = v; in npcm_gmac_write()
803 gmac_try_send_next_packet(gmac); in npcm_gmac_write()
805 gmac_dma_set_state(gmac, NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT, in npcm_gmac_write()
809 gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT, in npcm_gmac_write()
811 qemu_flush_queued_packets(qemu_get_queue(gmac->nic)); in npcm_gmac_write()
813 gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT, in npcm_gmac_write()
824 DEVICE(gmac)->canonical_path, offset, v); in npcm_gmac_write()
827 gmac->regs[offset / sizeof(uint32_t)] &= ~NPCM_DMA_STATUS_W1C_MASK(v); in npcm_gmac_write()
830 gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT, in npcm_gmac_write()
832 qemu_flush_queued_packets(qemu_get_queue(gmac->nic)); in npcm_gmac_write()
837 gmac->regs[offset / sizeof(uint32_t)] = v; in npcm_gmac_write()
841 gmac_update_irq(gmac); in npcm_gmac_write()
846 NPCMGMACState *gmac = NPCM_GMAC(dev); in npcm_gmac_reset() local
848 npcm_gmac_soft_reset(gmac); in npcm_gmac_reset()
849 memcpy(gmac->phy_regs[0], phy_reg_init, sizeof(phy_reg_init)); in npcm_gmac_reset()
851 trace_npcm_gmac_reset(DEVICE(gmac)->canonical_path, in npcm_gmac_reset()
852 gmac->phy_regs[0][MII_BMSR]); in npcm_gmac_reset()
877 NPCMGMACState *gmac = NPCM_GMAC(dev); in npcm_gmac_realize() local
880 memory_region_init_io(&gmac->iomem, OBJECT(gmac), &npcm_gmac_ops, gmac, in npcm_gmac_realize()
882 sysbus_init_mmio(sbd, &gmac->iomem); in npcm_gmac_realize()
883 sysbus_init_irq(sbd, &gmac->irq); in npcm_gmac_realize()
885 qemu_macaddr_default_if_unset(&gmac->conf.macaddr); in npcm_gmac_realize()
887 gmac->nic = qemu_new_nic(&net_npcm_gmac_info, &gmac->conf, TYPE_NPCM_GMAC, in npcm_gmac_realize()
888 dev->id, &dev->mem_reentrancy_guard, gmac); in npcm_gmac_realize()
889 qemu_format_nic_info_str(qemu_get_queue(gmac->nic), gmac->conf.macaddr.a); in npcm_gmac_realize()
890 gmac->regs[R_NPCM_GMAC_MAC0_ADDR_HI] = (gmac->conf.macaddr.a[0] << 8) + \ in npcm_gmac_realize()
891 gmac->conf.macaddr.a[1]; in npcm_gmac_realize()
892 gmac->regs[R_NPCM_GMAC_MAC0_ADDR_LO] = (gmac->conf.macaddr.a[2] << 24) + \ in npcm_gmac_realize()
893 (gmac->conf.macaddr.a[3] << 16) + \ in npcm_gmac_realize()
894 (gmac->conf.macaddr.a[4] << 8) + \ in npcm_gmac_realize()
895 gmac->conf.macaddr.a[5]; in npcm_gmac_realize()
900 NPCMGMACState *gmac = NPCM_GMAC(dev); in npcm_gmac_unrealize() local
902 qemu_del_nic(gmac->nic); in npcm_gmac_unrealize()
925 dc->desc = "NPCM GMAC Controller"; in npcm_gmac_class_init()