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/openbmc/qemu/hw/intc/
H A Dmips_gic.c25 static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp, int pin) in mips_gic_set_vp_irq() argument
31 for (i = 0; i < gic->num_irq; i++) { in mips_gic_set_vp_irq()
32 if ((gic->irq_state[i].map_pin & GIC_MAP_MSK) == pin && in mips_gic_set_vp_irq()
33 gic->irq_state[i].map_vp == vp && in mips_gic_set_vp_irq()
34 gic->irq_state[i].enabled) { in mips_gic_set_vp_irq()
35 ored_level |= gic->irq_state[i].pending; in mips_gic_set_vp_irq()
42 if (((gic->vps[vp].compare_map & GIC_MAP_MSK) == pin) && in mips_gic_set_vp_irq()
43 (gic->vps[vp].mask & GIC_VP_MASK_CMP_MSK)) { in mips_gic_set_vp_irq()
45 ored_level |= (gic->vps[vp].pend & GIC_VP_MASK_CMP_MSK) >> in mips_gic_set_vp_irq()
49 kvm_mips_set_ipi_interrupt(env_archcpu(gic->vps[vp].env), in mips_gic_set_vp_irq()
[all …]
H A Drealview_gic.c21 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in realview_gic_set_irq()
35 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", numirq); in realview_gic_realize()
36 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { in realview_gic_realize()
39 busdev = SYS_BUS_DEVICE(&s->gic); in realview_gic_realize()
41 /* Pass through outbound IRQ lines from the GIC */ in realview_gic_realize()
44 /* Pass through inbound GPIO lines to the GIC */ in realview_gic_realize()
59 "realview-gic-container", 0x2000); in realview_gic_init()
62 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); in realview_gic_init()
63 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", 1); in realview_gic_init()
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Drtsm_ve-aemv8a.dts13 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 interrupt-parent = <&gic>;
99 gic: interrupt-controller@2c001000 { label
100 compatible = "arm,gic-400", "arm,cortex-a15-gic";
140 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
141 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
142 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
143 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
144 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
145 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dfoundation-v8.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 interrupt-parent = <&gic>;
137 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
138 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
139 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
140 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
141 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
142 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
143 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
144 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dfvp-base-revc.dts13 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
188 gic: interrupt-controller@2f000000 { label
189 compatible = "arm,gic-v3";
204 compatible = "arm,gic-v3-its";
237 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
238 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
239 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
240 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
273 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/openbmc/linux/drivers/irqchip/
H A Dirq-gic.c5 * Interrupt architecture for the GIC:
42 #include <linux/irqchip/arm-gic.h>
50 #include "irq-gic-common.h"
114 * The GIC mapping of CPU interfaces does not necessarily match
116 * by the GIC itself.
312 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16); in gic_set_type()
321 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ in gic_irq_set_vcpu_affinity()
340 struct gic_chip_data *gic = &gic_data[0]; in gic_handle_irq() local
341 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq()
356 * is read after we've read the ACK register on the GIC. in gic_handle_irq()
[all …]
H A Dirq-gic-pm.c9 #include <linux/irqchip/arm-gic.h>
28 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_resume() local
39 * want to restore the GIC on the very first resume. So if in gic_runtime_resume()
42 if (!gic) in gic_runtime_resume()
45 gic_dist_restore(gic); in gic_runtime_resume()
46 gic_cpu_restore(gic); in gic_runtime_resume()
54 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_suspend() local
57 gic_dist_save(gic); in gic_runtime_suspend()
58 gic_cpu_save(gic); in gic_runtime_suspend()
115 dev_info(dev, "GIC IRQ controller registered\n"); in gic_probe()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
13 ARM SMP cores are often associated with a GIC, providing per processor
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
34 - arm,eb11mp-gic
35 - arm,gic-400
[all …]
H A Dmti,gic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
16 interrupts which can be used as IPIs. The GIC also includes a free-running
21 const: mti,gic
27 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
28 GIC interrupt number. The 3d cell encodes the interrupt flags setting up
34 Base address and length of the GIC registers space. If not present,
42 Specifies the list of CPU interrupt vectors to which the GIC may not
55 Specifies the range of GIC interrupts that are reserved for IPIs.
69 MIPS GIC includes a free-running global timer, per-CPU count/compare
[all …]
H A Drenesas,rza1-irqc.yaml14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
43 description: Specifies the mapping from external interrupts to GIC interrupts.
63 #include <dt-bindings/interrupt-controller/arm-gic.h>
71 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
72 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
73 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
74 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
75 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
76 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Darm,gic-v3.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
26 - qcom,msm8996-gic-v3
27 - const: arm,gic-v3
28 - const: arm,gic-v3
73 Specifies base physical address(s) and size of the GIC
75 - GIC Distributor interface (GICD)
76 - GIC Redistributors (GICR), one range per redistributor region
77 - GIC CPU interface (GICC)
78 - GIC Hypervisor interface (GICH)
79 - GIC Virtual CPU interface (GICV)
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-ns.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
68 gic: interrupt-controller@21000 { label
69 compatible = "arm,cortex-a9-gic";
99 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
102 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
103 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
104 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
105 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
106 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dbcm53573.dtsi9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
41 gic: interrupt-controller@1000 { label
42 compatible = "arm,cortex-a7-gic";
82 <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
85 <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
88 <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
89 <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
90 <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91 <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2m-rs1.dtsi20 #include <dt-bindings/interrupt-controller/arm-gic.h>
111 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
112 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
113 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
114 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
115 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
116 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
117 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
118 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
119 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dvexpress-v2m.dtsi20 #include <dt-bindings/interrupt-controller/arm-gic.h>
32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
39 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
40 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/openbmc/qemu/hw/cpu/
H A Da15mpcore.c35 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in a15mp_priv_set_irq()
46 object_initialize_child(obj, "gic", &s->gic, gic_class_name()); in a15mp_priv_initfn()
47 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); in a15mp_priv_initfn()
61 gicdev = DEVICE(&s->gic); in a15mp_priv_realize()
66 /* Make the GIC's TZ support match the CPUs. We assume that in a15mp_priv_realize()
79 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { in a15mp_priv_realize()
82 busdev = SYS_BUS_DEVICE(&s->gic); in a15mp_priv_realize()
84 /* Pass through outbound IRQ lines from the GIC */ in a15mp_priv_realize()
87 /* Pass through inbound GPIO lines to the GIC */ in a15mp_priv_realize()
91 * appropriate GIC PPI inputs in a15mp_priv_realize()
[all …]
/openbmc/qemu/hw/arm/
H A Dallwinner-h3.c205 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); in allwinner_h3_init()
267 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI + in allwinner_h3_realize()
269 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); in allwinner_h3_realize()
270 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS); in allwinner_h3_realize()
271 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false); in allwinner_h3_realize()
272 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true); in allwinner_h3_realize()
273 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal); in allwinner_h3_realize()
275 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_DEV_GIC_DIST]); in allwinner_h3_realize()
276 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_DEV_GIC_CPU]); in allwinner_h3_realize()
277 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_DEV_GIC_HYP]); in allwinner_h3_realize()
[all …]
H A Dbcm2838.c25 /* Number of external interrupt lines to configure the GIC with */
44 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in bcm2838_gic_set_irq()
62 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); in bcm2838_init()
107 if (!object_property_set_uint(OBJECT(&s->gic), "revision", 2, errp)) { in bcm2838_realize()
111 if (!object_property_set_uint(OBJECT(&s->gic), "num-cpu", BCM283X_NCPUS, in bcm2838_realize()
116 if (!object_property_set_uint(OBJECT(&s->gic), "num-irq", in bcm2838_realize()
121 if (!object_property_set_bool(OBJECT(&s->gic), in bcm2838_realize()
127 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { in bcm2838_realize()
131 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, in bcm2838_realize()
133 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, in bcm2838_realize()
[all …]
H A Dallwinner-r40.c276 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); in allwinner_r40_init()
341 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_R40_GIC_NUM_SPI + in allwinner_r40_realize()
343 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); in allwinner_r40_realize()
344 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_R40_NUM_CPUS); in allwinner_r40_realize()
345 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false); in allwinner_r40_realize()
346 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true); in allwinner_r40_realize()
347 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal); in allwinner_r40_realize()
349 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_R40_DEV_GIC_DIST]); in allwinner_r40_realize()
350 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_R40_DEV_GIC_CPU]); in allwinner_r40_realize()
351 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_R40_DEV_GIC_HYP]); in allwinner_r40_realize()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dexynos4.dtsi30 gic: interrupt-controller@10490000 { label
31 compatible = "arm,cortex-a9-gic";
73 interrupt-parent = <&gic>;
82 interrupt-parent = <&gic>;
91 interrupt-parent = <&gic>;
100 interrupt-parent = <&gic>;
109 interrupt-parent = <&gic>;
118 interrupt-parent = <&gic>;
127 interrupt-parent = <&gic>;
136 interrupt-parent = <&gic>;
[all …]
H A Dzynqmp.dtsi107 interrupt-parent = <&gic>;
122 interrupt-parent = <&gic>;
128 interrupt-parent = <&gic>;
219 gic: interrupt-controller@f9010000 { label
220 compatible = "arm,gic-400", "arm,cortex-a15-gic";
227 interrupt-parent = <&gic>;
245 interrupt-parent = <&gic>;
256 interrupt-parent = <&gic>;
271 interrupt-parent = <&gic>;
285 interrupt-parent = <&gic>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi17 #include <dt-bindings/interrupt-controller/arm-gic.h>
135 interrupt-parent = <&gic>;
165 interrupt-parent = <&gic>;
191 interrupt-parent = <&gic>;
235 interrupt-parent = <&gic>;
280 interrupt-parent = <&gic>;
292 interrupt-parent = <&gic>;
309 interrupt-parent = <&gic>;
323 interrupt-parent = <&gic>;
336 interrupt-parent = <&gic>;
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Dmips-gic.h8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
16 /* The base address of the GIC registers */
19 /* Offsets from the GIC base address to various control blocks */
31 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
35 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
39 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
40 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
44 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
45 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
163 /* GIC_SH_CONFIG - Information about the GIC configuration */
[all …]
/openbmc/qemu/include/hw/timer/
H A Dmips_gictimer.h34 uint32_t mips_gictimer_get_freq(MIPSGICTimerState *gic);
35 uint32_t mips_gictimer_get_sh_count(MIPSGICTimerState *gic);
36 void mips_gictimer_store_sh_count(MIPSGICTimerState *gic, uint64_t count);
39 void mips_gictimer_store_vp_compare(MIPSGICTimerState *gic, uint32_t vp_index,
41 uint8_t mips_gictimer_get_countstop(MIPSGICTimerState *gic);
42 void mips_gictimer_start_count(MIPSGICTimerState *gic);
43 void mips_gictimer_stop_count(MIPSGICTimerState *gic);
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dbrcm,bus-axi.txt34 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
37 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
40 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
41 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
42 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
43 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
44 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
45 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;

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