Lines Matching full:gic

4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
13 ARM SMP cores are often associated with a GIC, providing per processor
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
34 - arm,eb11mp-gic
35 - arm,gic-400
37 - arm,tc11mp-gic
42 - const: arm,gic-400
44 - arm,cortex-a15-gic
45 - arm,cortex-a7-gic
48 - const: arm,arm1176jzf-devchip-gic
49 - const: arm,arm11mp-gic
52 - const: brcm,brahma-b15-gic
53 - const: arm,cortex-a15-gic
88 the 8 possible cpus attached to the GIC. A bit set to '1' indicated
97 Specifies base physical address(s) and size of the GIC registers. The
98 first region is the GIC distributor register base and size. The 2nd region
99 is the GIC cpu interface register base and size.
103 registers. The first additional region is the GIC virtual interface
104 control register base and size. The 2nd additional region is the GIC
113 secondary GICs, or VGIC maintenance interrupt on primary GIC (see
119 regions, used when the GIC doesn't have banked registers. The offset
128 description: List of names for the GIC clock input(s). Valid clock names
129 depend on the GIC variant.
131 - const: ic_clk # for "arm,arm11mp-gic"
132 - const: PERIPHCLKEN # for "arm,cortex-a15-gic"
133 - items: # for "arm,cortex-a9-gic"
136 - const: clk # for "arm,gic-400" and "nvidia,tegra210"
155 Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
160 const: arm,gic-v2m-frame
193 compatible = "arm,cortex-a9-gic";
204 compatible = "arm,cortex-a15-gic";
217 compatible = "arm,gic-400";
230 compatible = "arm,gic-v2m-frame";
238 compatible = "arm,gic-v2m-frame";