Home
last modified time | relevance | path

Searched full:dpll (Results 1 – 25 of 217) sorted by relevance

123456789

/openbmc/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt1 Binding for Texas Instruments DPLL clock.
6 register-mapped DPLL with usually two selectable input clocks
12 for the actual DPLL clock.
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
23 "ti,omap4-dpll-x2-clock",
24 "ti,omap4-dpll-core-clock",
[all …]
/openbmc/linux/drivers/clk/ti/
H A Ddpll3xxx.c3 * OMAP3/4 - specific DPLL control functions
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
60 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
129 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
130 * @clk: pointer to a DPLL struct clk
132 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
133 * readiness before returning. Will save and restore the DPLL's
134 * autoidle state across the enable, per the CDP code. If the DPLL
135 * locked successfully, return 0; if the DPLL did not lock in the time
145 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock()
[all …]
H A Dclkt_dpll.c3 * OMAP2/3/4 DPLL clock functions
25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
33 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
44 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
45 * From device data manual section 4.3 "DPLL and DLL Specifications".
57 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
58 * @clk: DPLL struct clk to test
61 * Tests whether a particular divider @n will result in a valid DPLL
62 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
75 /* DPLL divider must result in a valid jitter correction val */ in _dpll_test_fint()
[all …]
H A Ddpll44xx.c3 * OMAP4-specific DPLL control functions
19 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
20 * can supported when using the DPLL low-power mode. Frequencies are
79 * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
80 * @dd: pointer to the dpll data structure
104 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
106 * @parent_rate: clock rate of the DPLL parent
108 * Compute the output rate for the OMAP4 DPLL represented by @clk.
110 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
128 /* regm4xen adds a multiplier of 4 to DPLL calculations */ in omap4_dpll_regm4xen_recalc()
[all …]
H A Ddpll.c3 * OMAP DPLL clock support
145 * _register_dpll - low level registration of a DPLL clock
149 * Finalizes DPLL registration process. In case a failure (clk-ref or
215 * Initializes a DPLL x 2 clock from device tree data.
272 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
273 * @node: device node containing the DPLL info
274 * @ops: ops for the DPLL
275 * @ddt: DPLL data template to use
277 * Initializes a DPLL clock from device tree data.
322 * Special case for OMAP2 DPLL, register order is different due to in of_ti_dpll_setup()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c313 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
325 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) in i9xx_dpll_compute_m() argument
327 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
330 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
342 int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
354 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
373 const struct dpll *clock) in intel_pll_is_valid()
444 const struct dpll *match_clock, in i9xx_find_best_dpll()
445 struct dpll *best_clock) in i9xx_find_best_dpll()
448 struct dpll clock; in i9xx_find_best_dpll()
[all …]
H A Dintel_dpll.h11 struct dpll;
23 int vlv_calc_dpll_params(int refclk, struct dpll *clock);
24 int pnv_calc_dpll_params(int refclk, struct dpll *clock);
25 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
26 u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
31 const struct dpll *dpll);
41 struct dpll *best_clock);
42 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
H A Dintel_dpll_mgr.h42 * enum intel_dpll_id - possible DPLL ids
44 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
48 * @DPLL_ID_PRIVATE: non-shared dpll in use
53 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
57 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
180 u32 dpll; member
191 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
194 * the DPLL.
228 * struct intel_shared_dpll_state - hold the DPLL atomic state
230 * This structure holds an atomic state for the DPLL, that can represent
[all …]
H A Dintel_dpll_mgr.c78 * Hook for reading the values currently programmed to the DPLL
120 /* Copy shared dpll state */ in intel_atomic_duplicate_dpll_state()
121 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
122 struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
146 * intel_get_shared_dpll_by_id - get a DPLL given its id
151 * A pointer to the DPLL with @id
157 return &dev_priv->display.dpll.shared_dplls[id]; in intel_get_shared_dpll_by_id()
169 "asserting DPLL %s with no DPLL\n", str_on_off(state))) in assert_shared_dpll()
216 * intel_enable_shared_dpll - enable a CRTC's shared DPLL
217 * @crtc_state: CRTC, and its state, which has a shared DPLL
[all …]
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c107 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
158 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
160 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
161 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
163 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
167 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
168 dpll |= in psb_intel_crtc_mode_set()
173 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
176 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
179 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
[all …]
H A Doaktrail_crtc.c244 /* Enable the DPLL */ in oaktrail_crtc_dpms()
245 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
247 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
248 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
251 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
253 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
256 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
258 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
317 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
319 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
[all …]
H A Dcdv_intel_display.c207 /* Unlike most Intel display engines, on Cedarview the DPLL registers
209 * DPLL reference clock is on in the DPLL control register, but before
210 * the DPLL is enabled in the DPLL control register.
261 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n"); in cdv_dpll_set_clock_cdv()
584 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
665 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
676 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
678 dpll |= DPLLB_MODE_LVDS; in cdv_intel_crtc_mode_set()
680 dpll |= DPLLB_MODE_DAC_SERIAL; */ in cdv_intel_crtc_mode_set()
681 /* dpll |= (2 << 11); */ in cdv_intel_crtc_mode_set()
[all …]
/openbmc/linux/include/linux/clk/
H A Dti.h26 * struct dpll_data - DPLL registers and integration data
27 * @mult_div1_reg: register containing the DPLL M and N bitfields
28 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
29 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
32 * @control_reg: register containing the DPLL mode bitfield
33 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
44 * @max_rate: maximum clock rate for the DPLL
46 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
47 * @idlest_reg: register containing the DPLL idle status bitfield
48 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dclkt2xxx_dpll.c3 * OMAP2-specific DPLL control functions
21 * _allow_idle - enable DPLL autoidle bits
22 * @clk: struct clk * of the DPLL to operate on
24 * Enable DPLL automatic idle control. The DPLL will enter low-power
26 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
38 * _deny_idle - prevent DPLL from automatically idling
39 * @clk: struct clk * of the DPLL to operate on
41 * Disable DPLL automatic idle control. No return value.
H A Dsleep24xx.S35 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
37 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
44 * Post sleep we will shift back to using the DPLL. Apparently,
60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
69 /* The DPLL has to be on before we take the DDR out of self refresh */
H A Dopp2xxx.h14 * respect to each other. These ratio sets are for a given voltage/DPLL
15 * setting. All configurations can be described by a DPLL setting and a ratio
45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
65 * Voltage/DPLL ratios
218 * describe DPLL combinations to go along with a ratio.
230 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
247 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
265 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
286 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
305 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/clk/
H A DMakefile5 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o
6 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o
7 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o
8 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o
9 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
10 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
14 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o
15 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o
16 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o
H A Ddpll-sld8.c17 * Set DPLL SSC parameters for DPLLCTRL3 in uniphier_sld8_dpll_init()
31 * Set DPLL SSC parameters for DPLLCTRL in uniphier_sld8_dpll_init()
46 * Set DPLL SSC parameters for DPLLCTRL2 in uniphier_sld8_dpll_init()
57 /* Wait 500 usec until dpll gets stable */ in uniphier_sld8_dpll_init()
/openbmc/linux/Documentation/devicetree/bindings/media/i2c/
H A Dadv748x.yaml38 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
39 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
40 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
41 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
42 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
43 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
44 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
45 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
46 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
47 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7xx-clocks.dtsi229 compatible = "ti,omap4-dpll-m4xen-clock";
235 dpll_abe_x2_ck: clock-dpll-abe-x2 {
237 compatible = "ti,omap4-dpll-x2-clock";
242 dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {
264 dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
276 dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
288 dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {
299 compatible = "ti,omap4-dpll-core-clock";
305 dpll_core_x2_ck: clock-dpll-core-x2 {
307 compatible = "ti,omap4-dpll-x2-clock";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmicrochip,sparx5-dpll.yaml4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
7 title: Microchip Sparx5 DPLL Clock
13 The Sparx5 DPLL clock controller generates and supplies clock to
18 const: microchip,sparx5-dpll
46 compatible = "microchip,sparx5-dpll";
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Dclocks_omap3.h17 * and hence are defined here. All the other DPLL related values are
21 /* CORE DPLL */
31 /* PER DPLL */
39 /* MPU DPLL */
116 /* IVA DPLL */
193 /* CORE DPLL */
245 /* PER DPLL */
272 /* PER2 DPLL */
298 /* 36XX PER DPLL */
325 /* 36XX PER2 DPLL */
/openbmc/u-boot/arch/arm/mach-omap2/
H A Dclocks-common.c57 /* SYS_CLKSEL - 1 to match the dpll param array indices */ in __get_sys_clk_index()
116 printf("Bypassing DPLL failed %x\n", base); in wait_for_bypass()
135 printf("DPLL locking failed for %x\n", base); in wait_for_lock()
211 u8 lock, char *dpll) in do_setup_dpll() argument
223 * The Dpll has already been locked by rom code using CH. in do_setup_dpll()
230 debug("\n %s Dpll locked, but not for ideal M = %d," in do_setup_dpll()
232 "N= %d" , dpll, params->m, params->n, in do_setup_dpll()
235 /* Dpll locked with ideal values for nominal opps. */ in do_setup_dpll()
236 debug("\n %s Dpll already locked with ideal" in do_setup_dpll()
237 "nominal opp values", dpll); in do_setup_dpll()
[all …]
/openbmc/u-boot/arch/arm/lib/
H A Dasm-offsets.c32 * - struct dpll in main()
190 /* DPLL */ in main()
191 DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl)); in main()
192 DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config)); in main()
193 DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op)); in main()
194 DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd)); in main()
195 DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn)); in main()
196 DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op)); in main()
197 DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd)); in main()
198 DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn)); in main()
/openbmc/linux/arch/arm/mach-omap1/
H A Dsram.S36 strh r0, [r2] @ set dpll into bypass mode
41 strh r0, [r2] @ write new dpll value
49 lock: ldrh r4, [r2], #0 @ read back dpll value
52 tst r4, #1 << 0 @ dpll rate locked?

123456789