Lines Matching full:dpll
78 * Hook for reading the values currently programmed to the DPLL
120 /* Copy shared dpll state */ in intel_atomic_duplicate_dpll_state()
121 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
122 struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
146 * intel_get_shared_dpll_by_id - get a DPLL given its id
151 * A pointer to the DPLL with @id
157 return &dev_priv->display.dpll.shared_dplls[id]; in intel_get_shared_dpll_by_id()
169 "asserting DPLL %s with no DPLL\n", str_on_off(state))) in assert_shared_dpll()
216 * intel_enable_shared_dpll - enable a CRTC's shared DPLL
217 * @crtc_state: CRTC, and its state, which has a shared DPLL
219 * Enable the shared DPLL used by @crtc.
232 mutex_lock(&dev_priv->display.dpll.lock); in intel_enable_shared_dpll()
258 mutex_unlock(&dev_priv->display.dpll.lock); in intel_enable_shared_dpll()
262 * intel_disable_shared_dpll - disable a CRTC's shared DPLL
263 * @crtc_state: CRTC, and its state, which has a shared DPLL
265 * Disable the shared DPLL used by @crtc.
281 mutex_lock(&dev_priv->display.dpll.lock); in intel_disable_shared_dpll()
304 mutex_unlock(&dev_priv->display.dpll.lock); in intel_disable_shared_dpll()
323 pll = &dev_priv->display.dpll.shared_dplls[i]; in intel_find_shared_dpll()
357 * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
359 * @pll: DPLL for which the reference is taken
360 * @shared_dpll_state: the DPLL atomic state in which the reference is tracked
397 * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC
399 * @pll: DPLL for which the reference is dropped
400 * @shared_dpll_state: the DPLL atomic state in which the reference is tracked
448 * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
451 * This is the dpll version of drm_atomic_helper_swap_state() since the
467 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in intel_shared_dpll_swap_state()
469 &dev_priv->display.dpll.shared_dplls[i]; in intel_shared_dpll_swap_state()
489 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state()
521 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
528 * DPLL is enabled and the clocks are stable. in ibx_pch_dpll_enable()
532 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
567 pll = &dev_priv->display.dpll.shared_dplls[i]; in ibx_get_dpll()
596 "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " in ibx_dump_hw_state()
598 hw_state->dpll, in ibx_dump_hw_state()
611 { "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
612 { "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
654 if (dev_priv->display.dpll.pch_ssc_use & BIT(id)) in hsw_ddi_wrpll_disable()
670 if (dev_priv->display.dpll.pch_ssc_use & BIT(id)) in hsw_ddi_spll_disable()
933 refclk = dev_priv->display.dpll.ref_clks.nssc; in hsw_ddi_wrpll_get_freq()
943 refclk = dev_priv->display.dpll.ref_clks.ssc; in hsw_ddi_wrpll_get_freq()
1165 i915->display.dpll.ref_clks.ssc = 135000; in hsw_update_dpll_ref_clks()
1168 i915->display.dpll.ref_clks.nssc = 24000; in hsw_update_dpll_ref_clks()
1170 i915->display.dpll.ref_clks.nssc = 135000; in hsw_update_dpll_ref_clks()
1244 /* DPLL 0 */
1246 /* DPLL 0 doesn't support HDMI mode */
1249 /* DPLL 1 */
1255 /* DPLL 2 */
1261 /* DPLL 3 */
1296 drm_err(&dev_priv->drm, "DPLL %d not locked\n", id); in skl_ddi_pll_enable()
1634 int ref_clock = i915->display.dpll.ref_clks.nssc; in skl_ddi_wrpll_get_freq()
1710 * as the DPLL id in this function. in skl_ddi_hdmi_pll_dividers()
1717 i915->display.dpll.ref_clks.nssc, &wrpll_params); in skl_ddi_hdmi_pll_dividers()
1748 * as the DPLL id in this function. in skl_ddi_dp_set_dpll_hw_state()
1873 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in skl_update_dpll_ref_clks()
1901 { "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },
1902 { "DPLL 1", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
1903 { "DPLL 2", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
1904 { "DPLL 3", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL3, 0 },
2118 static const struct dpll bxt_dp_clk_val[] = {
2131 struct dpll *clk_div) in bxt_ddi_hdmi_pll_dividers()
2149 struct dpll *clk_div) in bxt_ddi_dp_pll_dividers()
2162 chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div); in bxt_ddi_dp_pll_dividers()
2169 const struct dpll *clk_div) in bxt_ddi_set_dpll_hw_state()
2240 struct dpll clock; in bxt_ddi_pll_get_freq()
2250 return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock); in bxt_ddi_pll_get_freq()
2256 struct dpll clk_div = {}; in bxt_ddi_dp_set_dpll_hw_state()
2267 struct dpll clk_div = {}; in bxt_ddi_hdmi_set_dpll_hw_state()
2324 i915->display.dpll.ref_clks.ssc = 100000; in bxt_update_dpll_ref_clks()
2325 i915->display.dpll.ref_clks.nssc = 100000; in bxt_update_dpll_ref_clks()
2468 i915->display.dpll.ref_clks.nssc == 38400; in ehl_combo_pll_div_frac_wa_needed()
2562 dev_priv->display.dpll.ref_clks.nssc == 24000 ? in icl_calc_dp_combo_pll()
2585 switch (dev_priv->display.dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2587 MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2598 switch (dev_priv->display.dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2600 MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2630 int ref_clock = i915->display.dpll.ref_clks.nssc; in icl_wrpll_ref_clock()
2634 * use 19.2 because the DPLL automatically divides that by 2. in icl_wrpll_ref_clock()
2857 int refclk_khz = dev_priv->display.dpll.ref_clks.nssc; in icl_calc_mg_pll_state()
3063 ref_clock = dev_priv->display.dpll.ref_clks.nssc; in icl_ddi_mg_pll_get_freq()
3129 * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
3130 * @crtc_state: state for the CRTC to select the DPLL for
3445 if (dev_priv->display.dpll.ref_clks.nssc == 38400) { in mg_pll_get_hw_state()
3818 * We need to disable DC states when this DPLL is enabled. in combo_pll_enable()
3945 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in icl_update_dpll_ref_clks()
3994 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
3995 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4015 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4016 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4017 { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
4038 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4039 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4061 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4062 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4063 { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
4077 { "DPLL 0", &combo_pll_funcs, DPLL_ID_DG1_DPLL0, 0 },
4078 { "DPLL 1", &combo_pll_funcs, DPLL_ID_DG1_DPLL1, 0 },
4079 { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
4080 { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
4094 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4095 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4096 { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
4097 { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
4111 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4112 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4143 mutex_init(&dev_priv->display.dpll.lock); in intel_shared_dpll_init()
4172 dev_priv->display.dpll.num_shared_dpll = 0; in intel_shared_dpll_init()
4180 i >= ARRAY_SIZE(dev_priv->display.dpll.shared_dplls))) in intel_shared_dpll_init()
4184 dev_priv->display.dpll.shared_dplls[i].info = &dpll_info[i]; in intel_shared_dpll_init()
4187 dev_priv->display.dpll.mgr = dpll_mgr; in intel_shared_dpll_init()
4188 dev_priv->display.dpll.num_shared_dpll = i; in intel_shared_dpll_init()
4192 * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
4197 * This function computes the DPLL state for the given CRTC and encoder.
4210 const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; in intel_compute_shared_dplls()
4243 const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; in intel_reserve_shared_dplls()
4266 const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; in intel_release_shared_dplls()
4271 * the shared DPLL framework and intel_reserve_shared_dplls() is not in intel_release_shared_dplls()
4281 * intel_update_active_dpll - update the active DPLL for a CRTC/encoder
4283 * @crtc: the CRTC for which to update the active DPLL
4284 * @encoder: encoder determining the type of port DPLL
4286 * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
4288 * DPLL selected will be based on the current mode of the encoder's port.
4295 const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; in intel_update_active_dpll()
4304 * intel_dpll_get_freq - calculate the DPLL's output frequency
4306 * @pll: DPLL for which to calculate the output frequency
4307 * @pll_state: DPLL state from which to calculate the output frequency
4322 * intel_dpll_get_hw_state - readout the DPLL's hardware state
4324 * @pll: DPLL for which to calculate the output frequency
4325 * @hw_state: DPLL's hardware state
4367 if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks) in intel_dpll_update_ref_clks()
4368 i915->display.dpll.mgr->update_ref_clks(i915); in intel_dpll_update_ref_clks()
4375 for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) in intel_dpll_readout_hw_state()
4376 readout_dpll_hw_state(i915, &i915->display.dpll.shared_dplls[i]); in intel_dpll_readout_hw_state()
4402 for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) in intel_dpll_sanitize_state()
4403 sanitize_dpll_state(i915, &i915->display.dpll.shared_dplls[i]); in intel_dpll_sanitize_state()
4416 if (dev_priv->display.dpll.mgr) { in intel_dpll_dump_hw_state()
4417 dev_priv->display.dpll.mgr->dump_hw_state(dev_priv, hw_state); in intel_dpll_dump_hw_state()
4419 /* fallback for platforms that don't use the shared dpll in intel_dpll_dump_hw_state()
4423 "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " in intel_dpll_dump_hw_state()
4425 hw_state->dpll, in intel_dpll_dump_hw_state()
4516 for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) in intel_shared_dpll_verify_disabled()
4517 verify_single_dpll_state(i915, &i915->display.dpll.shared_dplls[i], in intel_shared_dpll_verify_disabled()