1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2fcc238baSMasahiro Yamada /* 3fcc238baSMasahiro Yamada * Copyright (C) 2013-2014 Panasonic Corporation 4fcc238baSMasahiro Yamada * Copyright (C) 2015-2016 Socionext Inc. 5fcc238baSMasahiro Yamada */ 6fcc238baSMasahiro Yamada 7d9a70368SMasahiro Yamada #include <linux/delay.h> 8fcc238baSMasahiro Yamada #include <linux/io.h> 9fcc238baSMasahiro Yamada 10fcc238baSMasahiro Yamada #include "../init.h" 11fcc238baSMasahiro Yamada #include "../sc-regs.h" 12fcc238baSMasahiro Yamada uniphier_sld8_dpll_init(const struct uniphier_board_data * bd)13fcc238baSMasahiro Yamadaint uniphier_sld8_dpll_init(const struct uniphier_board_data *bd) 14fcc238baSMasahiro Yamada { 15fcc238baSMasahiro Yamada u32 tmp; 16fcc238baSMasahiro Yamada /* 17fcc238baSMasahiro Yamada * Set DPLL SSC parameters for DPLLCTRL3 18fcc238baSMasahiro Yamada * [23] DIVN_TEST 0x1 19fcc238baSMasahiro Yamada * [22:16] DIVN 0x50 20fcc238baSMasahiro Yamada * [10] FREFSEL_TEST 0x1 21fcc238baSMasahiro Yamada * [9:8] FREFSEL 0x2 22fcc238baSMasahiro Yamada * [4] ICPD_TEST 0x1 23fcc238baSMasahiro Yamada * [3:0] ICPD 0xb 24fcc238baSMasahiro Yamada */ 25fcc238baSMasahiro Yamada tmp = readl(SC_DPLLCTRL3); 26fcc238baSMasahiro Yamada tmp &= ~0x00ff0717; 27fcc238baSMasahiro Yamada tmp |= 0x00d0061b; 28fcc238baSMasahiro Yamada writel(tmp, SC_DPLLCTRL3); 29fcc238baSMasahiro Yamada 30fcc238baSMasahiro Yamada /* 31fcc238baSMasahiro Yamada * Set DPLL SSC parameters for DPLLCTRL 32fcc238baSMasahiro Yamada * <-1%> <-2%> 33fcc238baSMasahiro Yamada * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) 34fcc238baSMasahiro Yamada * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) 35fcc238baSMasahiro Yamada */ 36fcc238baSMasahiro Yamada tmp = readl(SC_DPLLCTRL); 37fcc238baSMasahiro Yamada tmp &= ~0x3ff07fff; 38fcc238baSMasahiro Yamada #ifdef DPLL_SSC_RATE_1PER 39fcc238baSMasahiro Yamada tmp |= 0x084018bf; 40fcc238baSMasahiro Yamada #else 41fcc238baSMasahiro Yamada tmp |= 0x084031a6; 42fcc238baSMasahiro Yamada #endif 43fcc238baSMasahiro Yamada writel(tmp, SC_DPLLCTRL); 44fcc238baSMasahiro Yamada 45fcc238baSMasahiro Yamada /* 46fcc238baSMasahiro Yamada * Set DPLL SSC parameters for DPLLCTRL2 47fcc238baSMasahiro Yamada * [31:29] SSC_STEP 0 48fcc238baSMasahiro Yamada * [27] SSC_REG_REF 1 49fcc238baSMasahiro Yamada * [26:20] SSC_M 79 (0x4f) 50fcc238baSMasahiro Yamada * [19:0] SSC_K 964689 (0xeb851) 51fcc238baSMasahiro Yamada */ 52fcc238baSMasahiro Yamada tmp = readl(SC_DPLLCTRL2); 53fcc238baSMasahiro Yamada tmp &= ~0xefffffff; 54fcc238baSMasahiro Yamada tmp |= 0x0cfeb851; 55fcc238baSMasahiro Yamada writel(tmp, SC_DPLLCTRL2); 56fcc238baSMasahiro Yamada 57fcc238baSMasahiro Yamada /* Wait 500 usec until dpll gets stable */ 58fcc238baSMasahiro Yamada udelay(500); 59fcc238baSMasahiro Yamada 60fcc238baSMasahiro Yamada return 0; 61fcc238baSMasahiro Yamada } 62