Lines Matching full:dpll

14  * respect to each other. These ratio sets are for a given voltage/DPLL
15  * setting. All configurations can be described by a DPLL setting and a ratio
45 	unsigned long dpll_speed;	/* dpll: out*xtal*M/(N-1)table_recalc */
65  * Voltage/DPLL ratios
218  * describe DPLL combinations to go along with a ratio.
230  * #5a	(ratio1) baseport-target, target DPLL = 266*2 = 532MHz
247 /* #5b	(ratio1) target DPLL = 200*2 = 400MHz */
265  * #4	(ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
286  * #3	(ratio2) baseport-target, target DPLL = 330*2 = 660MHz
305  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
353 /* PRCM I target DPLL = 2*330MHz = 660MHz */
362  * PRCM II , target DPLL = 2*300MHz = 600MHz
375 /* PRCM III target DPLL = 2*266 = 532MHz*/