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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dst,stm32-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/st,stm32-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Fabien Dessenne <fabien.dessenne@foss.st.com>
15 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
19 const: st,stm32mp1-m4
31 reset-names:
33 - const: mcu_rst
34 - const: hold_boot
[all …]
H A Dmtk,scp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tinghan Shen <tinghan.shen@mediatek.com>
13 This binding provides support for ARM Cortex M4 Co-processor found on some
19 - mediatek,mt8183-scp
20 - mediatek,mt8186-scp
21 - mediatek,mt8188-scp
22 - mediatek,mt8192-scp
23 - mediatek,mt8195-scp
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7m/
H A Dtune-cortexm4.inc2 # Tune Settings for Cortex-M4
6 TUNEVALID[cortexm4] = "Enable Cortex-M4 specific processor optimizations"
7 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexm4', ' -mcpu=cortex-m4', '', d)}"
9 require conf/machine/include/arm/arch-armv7em.inc
12 ARMPKGARCH:tune-cortexm4 = "cortexm4"
13 TUNE_FEATURES:tune-cortexm4 = "${TUNE_FEATURES:tune-armv7em} cortexm4"
14 PACKAGE_EXTRA_ARCHS:tune-cortexm4 = "${PACKAGE_EXTRA_ARCHS:tune-armv7em} cortexm4"
/openbmc/linux/Documentation/arch/arm/stm32/
H A Dstm32f429-overview.rst6 ------------
8 The STM32F429 is a Cortex-M4 MCU aimed at various applications.
11 - ARM Cortex-M4 up to 180MHz with FPU
12 - 2MB internal Flash Memory
13 - External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
14 - I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers
15 - LCD controller & Camera interface
16 - Cryptographic processor
19 ---------
23 …www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013
/openbmc/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610m4-colibri.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Device tree for Colibri VF61 Cortex-M4 support
8 /dts-v1/;
12 model = "VF610 Cortex-M4";
17 stdout-path = "serial2:115200";
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_uart2>;
53 vf610-colibri {
H A Dvf610m4-cosmic.dts2 * Device tree for Cosmic+ VF6xx Cortex-M4 support
8 * This file is dual-licensed: you can use it either under the terms
47 /dts-v1/;
51 model = "VF610 Cortex-M4";
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_uart3>;
82 vf610-cosmic {
H A Dvf610m4.dtsi2 * Device tree for VF6xx Cortex-M4 support
6 * This file is dual-licensed: you can use it either under the terms
45 #include "../../armv7-m.dtsi"
49 #address-cells = <1>;
50 #size-cells = <1>;
56 interrupt-parent = <&nvic>;
/openbmc/linux/arch/arm/mm/
H A Dproc-v7m.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7m.S
8 * This is the "shell" of the ARMv7-M processor support.
14 #include "proc-macros.S"
31 * - loc - location to jump to for soft reset
104 * This should be able to cover all ARMv7-M cores.
140 ldmia sp, {r0-r3, r12}
144 @ Special-purpose control register
150 stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
152 teq r8, #0 @ re-evalutae condition
[all …]
/openbmc/u-boot/arch/arm/mach-imx/
H A Dimx_bootaux.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <asm/mach-imx/sys_proto.h>
18 return -EINVAL; in arch_auxiliary_core_up()
23 /* Set the stack and pc to M4 bootROM */ in arch_auxiliary_core_up()
27 /* Enable M4 */ in arch_auxiliary_core_up()
59 * Per the cortex-M reference manual, the reset vector of M4 needs
61 * of that vector. So to boot M4, the A core must build the M4's reset
63 * TCMUL. When M4 is kicked, it will load the PC and SP by itself.
65 * accessing the M4 TCMUL.
/openbmc/qemu/hw/arm/
H A Dnetduinoplus2.c28 #include "hw/qdev-properties.h"
29 #include "hw/qdev-clock.h"
30 #include "qemu/error-report.h"
42 /* This clock doesn't need migration because it is fixed-frequency */ in netduinoplus2_init()
52 machine->kernel_filename, in netduinoplus2_init()
59 ARM_CPU_TYPE_NAME("cortex-m4"), in netduinoplus2_machine_init()
63 mc->desc = "Netduino Plus 2 Machine (Cortex-M4)"; in netduinoplus2_machine_init()
64 mc->init = netduinoplus2_init; in netduinoplus2_machine_init()
65 mc->valid_cpu_types = valid_cpu_types; in netduinoplus2_machine_init()
H A Dolimex-stm32-h405.c3 * Olimex STM32-H405 machine
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-clock.h"
31 #include "qemu/error-report.h"
35 /* olimex-stm32-h405 implementation is derived from netduinoplus2 */
45 /* This clock doesn't need migration because it is fixed-frequency */ in olimex_stm32_h405_init()
55 machine->kernel_filename, in olimex_stm32_h405_init()
62 ARM_CPU_TYPE_NAME("cortex-m4"), in olimex_stm32_h405_machine_init()
66 mc->desc = "Olimex STM32-H405 (Cortex-M4)"; in olimex_stm32_h405_machine_init()
67 mc->init = olimex_stm32_h405_init; in olimex_stm32_h405_machine_init()
[all …]
H A Dmps2.c17 * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
18 * "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
19 * "mps2-an500" -- Cortex-M7 as documented in ARM Application Note AN500
20 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
24 * https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
31 #include "qemu/error-report.h"
34 #include "hw/or-irq.h"
36 #include "exec/address-spaces.h"
38 #include "hw/qdev-properties.h"
40 #include "hw/char/cmsdk-apb-uart.h"
[all …]
H A Db-l475e-iot01a.c2 * B-L475E-IOT01A Discovery Kit machine
3 * (B-L475E-IOT01A IoT Node)
5 * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
6 * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
8 * SPDX-License-Identifier: GPL-2.0-or-later
11 * See the COPYING file in the top-level directory.
21 * Discovery kit for IoT node, multi-channel communication with STM32L4.
22 * https://www.st.com/en/evaluation-tools/b-l475e-iot01a.html#documentation
28 #include "hw/qdev-properties.h"
29 #include "qemu/error-report.h"
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/stm32/
H A Dst,mlahb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 ML-AHB interconnect
10 - Fabien Dessenne <fabien.dessenne@foss.st.com>
11 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
17 using different buses (see [2]): balancing the Cortex-M firmware accesses
23 - $ref: /schemas/simple-bus.yaml#
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7m/
H A Dsystick-timer.c1 // SPDX-License-Identifier: GPL-2.0+
3 * ARM Cortex M3/M4/M7 SysTick timer driver
6 * Based on arch/arm/mach-stm32/stm32f1/timer.c
13 * The SysTick timer is a 24-bit count down timer. The clock can be either the
29 /* SysTick Base Address - fixed for all Cortex M3, M4 and M7 devices */
47 /* read the 24-bit timer */
53 return TIMER_MAX_VAL - readl(&systick->current_val); in read_timer()
61 writel(TIMER_MAX_VAL, &systick->reload_val); in timer_init()
63 writel(0, &systick->current_val); in timer_init()
65 cal = readl(&systick->calibration); in timer_init()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/freescale/
H A Dfsl,vf610-mscm-ir.txt1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
8 which comes with a Cortex-A5/Cortex-M4 combination).
11 - compatible: "fsl,vf610-mscm-ir"
12 - reg: the register range of the MSCM Interrupt Router
13 - fsl,cpucfg: The handle to the MSCM CPU configuration node, required
15 - interrupt-controller: Identifies the node as an interrupt controller
16 - #interrupt-cells: Two cells, interrupt number and cells.
23 mscm_ir: interrupt-controller@40001800 {
24 compatible = "fsl,vf610-mscm-ir";
27 interrupt-controller;
[all …]
/openbmc/qemu/docs/system/arm/
H A Dmps2.rst1 …ards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521…
4 These board models use Arm M-profile or R-profile CPUs.
16 FPGA images using M-profile CPUs:
18 ``mps2-an385``
19 Cortex-M3 as documented in Arm Application Note AN385
20 ``mps2-an386``
21 Cortex-M4 as documented in Arm Application Note AN386
22 ``mps2-an500``
23 Cortex-M7 as documented in Arm Application Note AN500
24 ``mps2-an505``
[all …]
H A Demcraft-sf2.rst1 Emcraft SmartFusion2 SOM kit (``emcraft-sf2``)
4 The ``emcraft-sf2`` board emulates the SmartFusion2 SOM kit from
5 Emcraft (M2S010). This is a System-on-Module from EmCraft systems,
7 The SoC is based on a Cortex-M4 processor.
11 - System timer
12 - System registers
13 - SPI controller
14 - UART
15 - EMAC
/openbmc/linux/arch/arm/mach-imx/
H A Dmach-imx7d-cm4.c1 // SPDX-License-Identifier: GPL-2.0
11 "fsl,imx7d-cm4",
15 DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual Cortex-M4 (Device Tree)")
/openbmc/linux/drivers/firmware/imx/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
18 The System Controller Firmware (SCFW) is a low-level system function
19 which runs on a dedicated Cortex-M core to provide power, clock, and
24 SCU firmware running on M4.
/openbmc/linux/drivers/remoteproc/
H A Dimx_rproc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 u32 da; /* device address (From Cortex M4 view)*/
/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc4350.dtsi9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
25 compatible = "mmio-sram";
30 compatible = "mmio-sram";
35 compatible = "mmio-sram";
H A Dlpc4357.dtsi9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
25 compatible = "mmio-sram";
30 compatible = "mmio-sram";
35 compatible = "mmio-sram";
/openbmc/qemu/docs/system/
H A Dtarget-arm.rst1 .. _ARM-System-emulator:
4 -------------------
6 QEMU can emulate both 32-bit and 64-bit Arm CPUs. Use the
7 ``qemu-system-aarch64`` executable to simulate a 64-bit Arm machine.
8 You can use either ``qemu-system-arm`` or ``qemu-system-aarch64``
9 to simulate a 32-bit Arm machine: in general, command lines that
10 work for ``qemu-system-arm`` will behave the same when used with
11 ``qemu-system-aarch64``.
16 are generally built into "system-on-chip" (SoC) designs created by
22 The situation for 64-bit Arm is fairly similar, except that we don't
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
[all …]

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